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[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Nicolai Haehnle <prefect_@gmx.net>
34 */
35
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
43
44 #include "drm.h"
45 #include "radeon_drm.h"
46
47 #include "radeon_buffer.h"
48 #include "radeon_ioctl.h"
49 #include "r300_context.h"
50 #include "r300_ioctl.h"
51 #include "radeon_reg.h"
52 #include "r300_reg.h"
53 #include "r300_cmdbuf.h"
54 #include "r300_emit.h"
55 #include "radeon_mipmap_tree.h"
56 #include "r300_state.h"
57 #include "radeon_cs_legacy.h"
58 #include "radeon_cs_gem.h"
59 #include "radeon_reg.h"
60
61 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
62 # define RADEON_ONE_REG_WR (1 << 15)
63
64 // Set this to 1 for extremely verbose debugging of command buffers
65 #define DEBUG_CMDBUF 0
66
67 /** # of dwords reserved for additional instructions that may need to be written
68 * during flushing.
69 */
70 #define SPACE_FOR_FLUSHING 4
71
72 static void r300PrintStateAtom(r300ContextPtr r300,
73 struct radeon_state_atom *state)
74 {
75 int i;
76 int dwords = (*state->check) (r300->radeon.glCtx, state);
77
78 fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size);
79
80 if (RADEON_DEBUG & DEBUG_VERBOSE) {
81 for (i = 0; i < dwords; i++) {
82 fprintf(stderr, " %s[%d]: %08x\n",
83 state->name, i, state->cmd[i]);
84 }
85 }
86 }
87
88 /**
89 * Emit all atoms with a dirty field equal to dirty.
90 *
91 * The caller must have ensured that there is enough space in the command
92 * buffer.
93 */
94 static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty)
95 {
96 BATCH_LOCALS(&r300->radeon);
97 struct radeon_state_atom *atom;
98 int dwords;
99
100 cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
101 BEGIN_BATCH_NO_AUTOSTATE(2);
102 OUT_BATCH(cmdpacket0(r300->radeon.radeonScreen, R300_TX_INVALTAGS, 1));
103 OUT_BATCH(R300_TX_FLUSH);
104 END_BATCH();
105 end_3d(r300);
106
107 /* Emit actual atoms */
108 foreach(atom, &r300->hw.atomlist) {
109 if ((atom->dirty || r300->hw.all_dirty) == dirty) {
110 dwords = (*atom->check) (r300->radeon.glCtx, atom);
111 if (dwords) {
112 if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
113 r300PrintStateAtom(r300, atom);
114 }
115 if (atom->emit) {
116 (*atom->emit)(r300->radeon.glCtx, atom);
117 } else {
118 BEGIN_BATCH_NO_AUTOSTATE(dwords);
119 OUT_BATCH_TABLE(atom->cmd, dwords);
120 END_BATCH();
121 }
122 atom->dirty = GL_FALSE;
123 } else {
124 if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
125 fprintf(stderr, " skip state %s\n",
126 atom->name);
127 }
128 }
129 }
130 }
131
132 COMMIT_BATCH();
133 }
134
135 /**
136 * Copy dirty hardware state atoms into the command buffer.
137 *
138 * We also copy out clean state if we're at the start of a buffer. That makes
139 * it easy to recover from lost contexts.
140 */
141 void r300EmitState(r300ContextPtr r300)
142 {
143 if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_PRIMS))
144 fprintf(stderr, "%s\n", __FUNCTION__);
145
146 if (r300->radeon.cmdbuf.cs->cdw && !r300->hw.is_dirty && !r300->hw.all_dirty)
147 return;
148
149 /* To avoid going across the entire set of states multiple times, just check
150 * for enough space for the case of emitting all state.
151 */
152 rcommonEnsureCmdBufSpace(&r300->radeon, r300->hw.max_state_size, __FUNCTION__);
153
154 if (!r300->radeon.cmdbuf.cs->cdw) {
155 if (RADEON_DEBUG & DEBUG_STATE)
156 fprintf(stderr, "Begin reemit state\n");
157
158 r300EmitAtoms(r300, GL_FALSE);
159 }
160
161 if (RADEON_DEBUG & DEBUG_STATE)
162 fprintf(stderr, "Begin dirty state\n");
163
164 r300EmitAtoms(r300, GL_TRUE);
165 r300->hw.is_dirty = GL_FALSE;
166 r300->hw.all_dirty = GL_FALSE;
167 }
168
169 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
170 {
171 if (r300->radeon.radeonScreen->kernel_mm) {
172 return ((((*pkt) >> 16) & 0x3FFF) + 1);
173 } else {
174 drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
175 return t->packet0.count;
176 }
177 return 0;
178 }
179
180 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
181 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
182
183 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
184 {
185 r300ContextPtr r300 = R300_CONTEXT(ctx);
186 BATCH_LOCALS(&r300->radeon);
187 drm_r300_cmd_header_t cmd;
188 uint32_t addr, ndw, i;
189
190 if (!r300->radeon.radeonScreen->kernel_mm) {
191 uint32_t dwords;
192 dwords = (*atom->check) (ctx, atom);
193 BEGIN_BATCH_NO_AUTOSTATE(dwords);
194 OUT_BATCH_TABLE(atom->cmd, dwords);
195 END_BATCH();
196 return;
197 }
198
199 cmd.u = atom->cmd[0];
200 addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
201 ndw = cmd.vpu.count * 4;
202 if (ndw) {
203 BEGIN_BATCH_NO_AUTOSTATE(11 + ndw);
204
205 /* flush processing vertices */
206 OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
207 OUT_BATCH(0x0);
208 OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
209 OUT_BATCH((1 << 15) | (1 << 28));
210 OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
211 OUT_BATCH(0x00FFFFFF);
212 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
213 OUT_BATCH(1);
214 /* write vpu */
215 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0));
216 OUT_BATCH(addr);
217 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
218 for (i = 0; i < ndw; i++) {
219 OUT_BATCH(atom->cmd[i+1]);
220 }
221 END_BATCH();
222 }
223 }
224
225 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
226 {
227 r300ContextPtr r300 = R300_CONTEXT(ctx);
228 BATCH_LOCALS(&r300->radeon);
229 drm_r300_cmd_header_t cmd;
230 uint32_t addr, ndw, i, sz;
231 int type, clamp, stride;
232
233 if (!r300->radeon.radeonScreen->kernel_mm) {
234 uint32_t dwords;
235 dwords = (*atom->check) (ctx, atom);
236 BEGIN_BATCH_NO_AUTOSTATE(dwords);
237 OUT_BATCH_TABLE(atom->cmd, dwords);
238 END_BATCH();
239 return;
240 }
241
242 cmd.u = atom->cmd[0];
243 sz = cmd.r500fp.count;
244 addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
245 type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
246 clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
247
248 addr |= (type << 16);
249 addr |= (clamp << 17);
250
251 stride = type ? 4 : 6;
252
253 ndw = sz * stride;
254 if (ndw) {
255
256 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
257 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
258 OUT_BATCH(addr);
259 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
260 for (i = 0; i < ndw; i++) {
261 OUT_BATCH(atom->cmd[i+1]);
262 }
263 END_BATCH();
264 }
265 }
266
267 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
268 {
269 r300ContextPtr r300 = R300_CONTEXT(ctx);
270 BATCH_LOCALS(&r300->radeon);
271 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
272
273 if (numtmus) {
274 int i;
275
276 for(i = 0; i < numtmus; ++i) {
277 radeonTexObj *t = r300->hw.textures[i];
278 if (t && !t->image_override) {
279 BEGIN_BATCH_NO_AUTOSTATE(4);
280 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
281 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
282 RADEON_GEM_DOMAIN_VRAM, 0, 0);
283 END_BATCH();
284 } else if (!t) {
285 assert(0);
286 } else {
287 if (t->bo) {
288 BEGIN_BATCH_NO_AUTOSTATE(4);
289 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
290 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
291 RADEON_GEM_DOMAIN_VRAM, 0, 0);
292 END_BATCH();
293 } else if (!r300->radeon.radeonScreen->kernel_mm) {
294 BEGIN_BATCH_NO_AUTOSTATE(2);
295 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
296 OUT_BATCH(t->override_offset);
297 END_BATCH();
298 }
299 }
300 }
301 }
302 }
303
304 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
305 {
306 r300ContextPtr r300 = R300_CONTEXT(ctx);
307 BATCH_LOCALS(&r300->radeon);
308 struct radeon_renderbuffer *rrb;
309 uint32_t cbpitch;
310
311 rrb = radeon_get_colorbuffer(&r300->radeon);
312 if (!rrb || !rrb->bo) {
313 fprintf(stderr, "no rrb\n");
314 return;
315 }
316
317 cbpitch = (rrb->pitch / rrb->cpp);
318 if (rrb->cpp == 4)
319 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
320 else
321 cbpitch |= R300_COLOR_FORMAT_RGB565;
322
323 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
324 cbpitch |= R300_COLOR_TILE_ENABLE;
325
326 BEGIN_BATCH_NO_AUTOSTATE(6);
327 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
328 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
329 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
330 OUT_BATCH(cbpitch);
331 END_BATCH();
332 }
333
334 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
335 {
336 r300ContextPtr r300 = R300_CONTEXT(ctx);
337 BATCH_LOCALS(&r300->radeon);
338 struct radeon_renderbuffer *rrb;
339 uint32_t zbpitch;
340
341 rrb = radeon_get_depthbuffer(&r300->radeon);
342 if (!rrb)
343 return;
344
345 zbpitch = (rrb->pitch / rrb->cpp);
346 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
347 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
348 }
349 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
350 zbpitch |= R300_DEPTHMICROTILE_TILED;
351 }
352
353 BEGIN_BATCH_NO_AUTOSTATE(6);
354 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
355 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
356 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
357 END_BATCH();
358 }
359
360 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
361 {
362 return atom->cmd_size;
363 }
364
365 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
366 {
367 r300ContextPtr r300 = R300_CONTEXT(ctx);
368 int cnt;
369 if (atom->cmd[0] == CP_PACKET2) {
370 return 0;
371 }
372 cnt = packet0_count(r300, atom->cmd);
373 return cnt ? cnt + 1 : 0;
374 }
375
376 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
377 {
378 int cnt;
379
380 cnt = vpu_count(atom->cmd);
381 return cnt ? (cnt * 4) + 1 : 0;
382 }
383
384 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
385 {
386 int cnt;
387
388 cnt = r500fp_count(atom->cmd);
389 return cnt ? (cnt * 6) + 1 : 0;
390 }
391
392 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
393 {
394 int cnt;
395
396 cnt = r500fp_count(atom->cmd);
397 return cnt ? (cnt * 4) + 1 : 0;
398 }
399
400 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
401 do { \
402 r300->hw.ATOM.cmd_size = (SZ); \
403 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
404 r300->hw.ATOM.name = #ATOM; \
405 r300->hw.ATOM.idx = (IDX); \
406 r300->hw.ATOM.check = check_##CHK; \
407 r300->hw.ATOM.dirty = GL_FALSE; \
408 r300->hw.max_state_size += (SZ); \
409 insert_at_tail(&r300->hw.atomlist, &r300->hw.ATOM); \
410 } while (0)
411 /**
412 * Allocate memory for the command buffer and initialize the state atom
413 * list. Note that the initial hardware state is set by r300InitState().
414 */
415 void r300InitCmdBuf(r300ContextPtr r300)
416 {
417 int mtu;
418 int has_tcl = 1;
419 int is_r500 = 0;
420 int i;
421
422 if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
423 has_tcl = 0;
424
425 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
426 is_r500 = 1;
427
428 r300->hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
429
430 mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
431 if (RADEON_DEBUG & DEBUG_TEXTURE) {
432 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
433 }
434
435 /* Setup the atom linked list */
436 make_empty_list(&r300->hw.atomlist);
437 r300->hw.atomlist.name = "atom-list";
438
439 /* Initialize state atoms */
440 ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
441 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
442 ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
443 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
444 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
445 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
446 if (is_r500) {
447 ALLOC_STATE(vap_index_offset, always, 2, 0);
448 r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
449 r300->hw.vap_index_offset.cmd[1] = 0;
450 }
451 ALLOC_STATE(vte, always, 3, 0);
452 r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
453 ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
454 r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
455 ALLOC_STATE(vap_cntl_status, always, 2, 0);
456 r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
457 ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
458 r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
459 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
460 ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
461 r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
462 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
463 ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
464 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
465 ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
466 r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
467
468 if (has_tcl) {
469 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
470 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
471 ALLOC_STATE(vap_clip, always, 5, 0);
472 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
473 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
474 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
475 }
476
477 ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
478 r300->hw.vof.cmd[R300_VOF_CMD_0] =
479 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
480
481 if (has_tcl) {
482 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
483 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
484 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
485 }
486
487 ALLOC_STATE(gb_enable, always, 2, 0);
488 r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
489 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
490 r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5);
491 ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
492 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
493 ALLOC_STATE(ga_point_s0, always, 5, 0);
494 r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
495 ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
496 r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
497 ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
498 r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
499 ALLOC_STATE(ga_point_minmax, always, 4, 0);
500 r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
501 ALLOC_STATE(lcntl, always, 2, 0);
502 r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
503 ALLOC_STATE(ga_line_stipple, always, 4, 0);
504 r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
505 ALLOC_STATE(shade, always, 5, 0);
506 r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4);
507 ALLOC_STATE(polygon_mode, always, 4, 0);
508 r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
509 ALLOC_STATE(fogp, always, 3, 0);
510 r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
511 ALLOC_STATE(zbias_cntl, always, 2, 0);
512 r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
513 ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
514 r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
515 cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
516 ALLOC_STATE(occlusion_cntl, always, 2, 0);
517 r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
518 ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
519 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
520 ALLOC_STATE(su_depth_scale, always, 3, 0);
521 r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
522 ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
523 r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
524 if (is_r500) {
525 ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
526 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
527 for (i = 0; i < 8; i++) {
528 r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
529 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
530 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
531 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
532 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
533 }
534 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
535 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
536 } else {
537 ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
538 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
539 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
540 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
541 }
542 ALLOC_STATE(sc_hyperz, always, 3, 0);
543 r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
544 ALLOC_STATE(sc_screendoor, always, 2, 0);
545 r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
546 ALLOC_STATE(us_out_fmt, always, 6, 0);
547 r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
548
549 if (is_r500) {
550 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
551 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
552 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
553 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
554 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
555 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
556
557 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
558 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
559 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
560 r300->hw.r500fp.emit = emit_r500fp;
561 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
562 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
563 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
564 r300->hw.r500fp_const.emit = emit_r500fp;
565 } else {
566 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
567 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
568 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
569
570 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
571 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
572
573 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
574 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
575 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
576 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
577 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
578 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
579 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
580 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
581 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
582 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
583 }
584 ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
585 r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
586 ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
587 r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
588 ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
589 r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
590 ALLOC_STATE(fg_depth_src, always, 2, 0);
591 r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
592 ALLOC_STATE(rb3d_cctl, always, 2, 0);
593 r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
594 ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
595 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
596 ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
597 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
598 if (is_r500) {
599 ALLOC_STATE(blend_color, always, 3, 0);
600 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
601 } else {
602 ALLOC_STATE(blend_color, always, 2, 0);
603 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
604 }
605 ALLOC_STATE(rop, always, 2, 0);
606 r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
607 ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
608 r300->hw.cb.emit = &emit_cb_offset;
609 ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
610 r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
611 ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
612 r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
613 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
614 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
615 ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
616 r300->hw.zs.cmd[R300_ZS_CMD_0] =
617 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
618 ALLOC_STATE(zstencil_format, always, 5, 0);
619 r300->hw.zstencil_format.cmd[0] =
620 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
621 ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
622 r300->hw.zb.emit = emit_zb_offset;
623 ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
624 r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
625 ALLOC_STATE(unk4F30, always, 3, 0);
626 r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2);
627 ALLOC_STATE(zb_hiz_offset, always, 2, 0);
628 r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
629 ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
630 r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
631
632 /* VPU only on TCL */
633 if (has_tcl) {
634 int i;
635 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
636 r300->hw.vpi.cmd[0] =
637 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
638 r300->hw.vpi.emit = emit_vpu;
639
640 if (is_r500) {
641 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
642 r300->hw.vpp.cmd[0] =
643 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
644 r300->hw.vpp.emit = emit_vpu;
645
646 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
647 r300->hw.vps.cmd[0] =
648 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
649 r300->hw.vps.emit = emit_vpu;
650
651 for (i = 0; i < 6; i++) {
652 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
653 r300->hw.vpucp[i].cmd[0] =
654 cmdvpu(r300->radeon.radeonScreen,
655 R500_PVS_UCP_START + i, 1);
656 r300->hw.vpucp[i].emit = emit_vpu;
657 }
658 } else {
659 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
660 r300->hw.vpp.cmd[0] =
661 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
662 r300->hw.vpp.emit = emit_vpu;
663
664 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
665 r300->hw.vps.cmd[0] =
666 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
667 r300->hw.vps.emit = emit_vpu;
668
669 for (i = 0; i < 6; i++) {
670 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
671 r300->hw.vpucp[i].cmd[0] =
672 cmdvpu(r300->radeon.radeonScreen,
673 R300_PVS_UCP_START + i, 1);
674 r300->hw.vpucp[i].emit = emit_vpu;
675 }
676 }
677 }
678
679 /* Textures */
680 ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
681 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
682 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
683
684 ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
685 r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
686 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
687
688 ALLOC_STATE(tex.size, variable, mtu + 1, 0);
689 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
690
691 ALLOC_STATE(tex.format, variable, mtu + 1, 0);
692 r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
693 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
694
695 ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
696 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
697
698 ALLOC_STATE(tex.offset, variable, 1, 0);
699 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
700 cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
701 r300->hw.tex.offset.emit = &emit_tex_offsets;
702
703 ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
704 r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
705 cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
706
707 ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
708 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
709 cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
710
711 r300->hw.is_dirty = GL_TRUE;
712 r300->hw.all_dirty = GL_TRUE;
713
714 rcommonInitCmdBuf(&r300->radeon, r300->hw.max_state_size);
715 }
716
717 /**
718 * Destroy the command buffer and state atoms.
719 */
720 void r300DestroyCmdBuf(r300ContextPtr r300)
721 {
722 struct radeon_state_atom *atom;
723
724 foreach(atom, &r300->hw.atomlist) {
725 FREE(atom->cmd);
726 }
727
728 }