src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Nicolai Haehnle <prefect_@gmx.net>
  33  */
  34
  35 #include "glheader.h"
  36 #include "state.h"
  37 #include "imports.h"
  38 #include "macros.h"
  39 #include "context.h"
  40 #include "swrast/swrast.h"
  41 #include "simple_list.h"
  42
  43 #include "drm.h"
  44 #include "radeon_drm.h"
  45
  46 #include "radeon_ioctl.h"
  47 #include "r300_context.h"
  48 #include "r300_ioctl.h"
  49 #include "radeon_reg.h"
  50 #include "r300_reg.h"
  51 #include "r300_cmdbuf.h"
  52 #include "r300_emit.h"
  53 #include "r300_state.h"
  54
  55
  56 // Set this to 1 for extremely verbose debugging of command buffers
  57 #define DEBUG_CMDBUF            0
  58
  59
  60 /**
  61  * Send the current command buffer via ioctl to the hardware.
  62  */
  63 int r300FlushCmdBufLocked(r300ContextPtr r300, const char* caller)
  64 {
  65         int ret;
  66         int i;
  67         drm_radeon_cmd_buffer_t cmd;
  68         int start;
  69
  70         if (r300->radeon.lost_context) {
  71                 start = 0;
  72                 r300->radeon.lost_context = GL_FALSE;
  73         } else
  74                 start = r300->cmdbuf.count_reemit;
  75
  76         if (RADEON_DEBUG & DEBUG_IOCTL) {
  77                 fprintf(stderr, "%s from %s - %i cliprects\n",
  78                         __FUNCTION__, caller, r300->radeon.numClipRects);
  79
  80                 if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_VERBOSE)
  81                         for (i = start; i < r300->cmdbuf.count_used; ++i)
  82                                 fprintf(stderr, "%d: %08x\n", i,
  83                                         r300->cmdbuf.cmd_buf[i]);
  84         }
  85
  86         cmd.buf = (char*)(r300->cmdbuf.cmd_buf + start);
  87         cmd.bufsz = (r300->cmdbuf.count_used - start) * 4;
  88
  89         if (r300->radeon.state.scissor.enabled) {
  90                 cmd.nbox = r300->radeon.state.scissor.numClipRects;
  91                 cmd.boxes = (drm_clip_rect_t *)r300->radeon.state.scissor.pClipRects;
  92         } else {
  93                 cmd.nbox = r300->radeon.numClipRects;
  94                 cmd.boxes = (drm_clip_rect_t *)r300->radeon.pClipRects;
  95         }
  96
  97         ret = drmCommandWrite(r300->radeon.dri.fd,
  98                         DRM_RADEON_CMDBUF, &cmd, sizeof(cmd));
  99
 100         if (RADEON_DEBUG & DEBUG_SYNC) {
 101                 fprintf(stderr, "Syncing in %s (from %s)\n\n", __FUNCTION__, caller);
 102                 radeonWaitForIdleLocked(&r300->radeon);
 103         }
 104
 105         r300->dma.nr_released_bufs = 0;
 106         r300->cmdbuf.count_used = 0;
 107         r300->cmdbuf.count_reemit = 0;
 108
 109         return ret;
 110 }
 111
 112
 113 int r300FlushCmdBuf(r300ContextPtr r300, const char* caller)
 114 {
 115         int ret;
 116
 117         LOCK_HARDWARE(&r300->radeon);
 118
 119         ret=r300FlushCmdBufLocked(r300, caller);
 120
 121         UNLOCK_HARDWARE(&r300->radeon);
 122
 123         if (ret) {
 124                 fprintf(stderr, "drmRadeonCmdBuffer: %d (exiting)\n", ret);
 125                 exit(ret);
 126         }
 127
 128         return ret;
 129 }
 130
 131
 132 void r300_print_state_atom(r300ContextPtr r300, struct r300_state_atom *state)
 133 {
 134         int i;
 135         int dwords = (*state->check)(r300, state);
 136
 137         fprintf(stderr, "  emit %s/%d/%d\n", state->name, dwords, state->cmd_size);
 138
 139         if (RADEON_DEBUG & DEBUG_VERBOSE)
 140                 for (i = 0; i < dwords; i++)
 141                         fprintf(stderr, "      %s[%d]: %08X\n", state->name, i,
 142                                 state->cmd[i]);
 143 }
 144
 145 /**
 146  * Emit all atoms with a dirty field equal to dirty.
 147  *
 148  * The caller must have ensured that there is enough space in the command
 149  * buffer.
 150  */
 151 static __inline__ void r300DoEmitState(r300ContextPtr r300, GLboolean dirty)
 152 {
 153         struct r300_state_atom* atom;
 154         uint32_t* dest;
 155
 156         dest = r300->cmdbuf.cmd_buf + r300->cmdbuf.count_used;
 157
 158         if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
 159                 foreach(atom, &r300->hw.atomlist) {
 160                         if ((atom->dirty || r300->hw.all_dirty) == dirty) {
 161                                 int dwords = (*atom->check)(r300, atom);
 162
 163                                 if (dwords)
 164                                         r300_print_state_atom(r300, atom);
 165                                 else
 166                                         fprintf(stderr, "  skip state %s\n",
 167                                                 atom->name);
 168                         }
 169                 }
 170         }
 171
 172         /* Emit WAIT */
 173         *dest = cmdwait(R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 174         dest ++;
 175         r300->cmdbuf.count_used ++;
 176
 177         *dest = cmdpacket0(R300_TX_CNTL, 1);
 178         dest ++;
 179         r300->cmdbuf.count_used ++;
 180
 181         *dest = 0x0;
 182         dest ++;
 183         r300->cmdbuf.count_used ++;
 184
 185         /* Emit END3D */
 186         *dest = cmdpacify();
 187         dest ++;
 188         r300->cmdbuf.count_used ++;
 189
 190
 191         /* Emit actual atoms */
 192
 193         foreach(atom, &r300->hw.atomlist) {
 194                 if ((atom->dirty || r300->hw.all_dirty) == dirty) {
 195                         int dwords = (*atom->check)(r300, atom);
 196
 197                         if (dwords) {
 198                                 memcpy(dest, atom->cmd, dwords*4);
 199                                 dest += dwords;
 200                                 r300->cmdbuf.count_used += dwords;
 201                                 atom->dirty = GL_FALSE;
 202                         }
 203                 }
 204         }
 205 }
 206
 207 /**
 208  * Copy dirty hardware state atoms into the command buffer.
 209  *
 210  * We also copy out clean state if we're at the start of a buffer. That makes
 211  * it easy to recover from lost contexts.
 212  */
 213 void r300EmitState(r300ContextPtr r300)
 214 {
 215         if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_PRIMS))
 216                 fprintf(stderr, "%s\n", __FUNCTION__);
 217
 218         if (r300->cmdbuf.count_used && !r300->hw.is_dirty && !r300->hw.all_dirty)
 219                 return;
 220
 221         /* To avoid going across the entire set of states multiple times, just check
 222          * for enough space for the case of emitting all state, and inline the
 223          * r300AllocCmdBuf code here without all the checks.
 224          */
 225         r300EnsureCmdBufSpace(r300, r300->hw.max_state_size, __FUNCTION__);
 226
 227         if (!r300->cmdbuf.count_used) {
 228                 if (RADEON_DEBUG & DEBUG_STATE)
 229                         fprintf(stderr, "Begin reemit state\n");
 230
 231                 r300DoEmitState(r300, GL_FALSE);
 232                 r300->cmdbuf.count_reemit = r300->cmdbuf.count_used;
 233         }
 234
 235         if (RADEON_DEBUG & DEBUG_STATE)
 236                 fprintf(stderr, "Begin dirty state\n");
 237
 238         r300DoEmitState(r300, GL_TRUE);
 239
 240         assert(r300->cmdbuf.count_used < r300->cmdbuf.size);
 241
 242         r300->hw.is_dirty = GL_FALSE;
 243         r300->hw.all_dirty = GL_FALSE;
 244 }
 245
 246 #define CHECK( NM, COUNT )                              \
 247 static int check_##NM( r300ContextPtr r300,             \
 248                         struct r300_state_atom* atom )  \
 249 {                                                       \
 250    (void) atom; (void) r300;                            \
 251    return (COUNT);                                      \
 252 }
 253
 254 #define packet0_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->packet0.count)
 255 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
 256
 257 CHECK( always, atom->cmd_size )
 258 CHECK( variable, packet0_count(atom->cmd) ? (1 + packet0_count(atom->cmd)) : 0 )
 259 CHECK( vpu, vpu_count(atom->cmd) ? (1 + vpu_count(atom->cmd)*4) : 0 )
 260
 261 #undef packet0_count
 262 #undef vpu_count
 263
 264 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX )                           \
 265    do {                                                                 \
 266       r300->hw.ATOM.cmd_size = (SZ);                                    \
 267       r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 268       r300->hw.ATOM.name = (NM);                                        \
 269       r300->hw.ATOM.idx = (IDX);                                        \
 270       r300->hw.ATOM.check = check_##CHK;                                \
 271       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 272       r300->hw.max_state_size += (SZ);                                  \
 273    } while (0)
 274
 275
 276 /**
 277  * Allocate memory for the command buffer and initialize the state atom
 278  * list. Note that the initial hardware state is set by r300InitState().
 279  */
 280 void r300InitCmdBuf(r300ContextPtr r300)
 281 {
 282         int size, mtu;
 283
 284         r300->hw.max_state_size = 2+2; /* reserve extra space for WAIT_IDLE and tex cache flush */
 285
 286         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 287         if (RADEON_DEBUG & DEBUG_TEXTURE) {
 288                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 289         }
 290
 291         /* Initialize state atoms */
 292         ALLOC_STATE( vpt, always, R300_VPT_CMDSIZE, "vpt", 0 );
 293                 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(R300_SE_VPORT_XSCALE, 6);
 294         ALLOC_STATE( unk2080, always, 2, "unk2080", 0 );
 295                 r300->hw.unk2080.cmd[0] = cmdpacket0(0x2080, 1);
 296         ALLOC_STATE( vte, always, 3, "vte", 0 );
 297                 r300->hw.vte.cmd[0] = cmdpacket0(R300_SE_VTE_CNTL, 2);
 298         ALLOC_STATE( unk2134, always, 3, "unk2134", 0 );
 299                 r300->hw.unk2134.cmd[0] = cmdpacket0(0x2134, 2);
 300         ALLOC_STATE( unk2140, always, 2, "unk2140", 0 );
 301                 r300->hw.unk2140.cmd[0] = cmdpacket0(0x2140, 1);
 302         ALLOC_STATE( vir[0], variable, R300_VIR_CMDSIZE, "vir/0", 0 );
 303                 r300->hw.vir[0].cmd[R300_VIR_CMD_0] = cmdpacket0(R300_VAP_INPUT_ROUTE_0_0, 1);
 304         ALLOC_STATE( vir[1], variable, R300_VIR_CMDSIZE, "vir/1", 1 );
 305                 r300->hw.vir[1].cmd[R300_VIR_CMD_0] = cmdpacket0(R300_VAP_INPUT_ROUTE_1_0, 1);
 306         ALLOC_STATE( vic, always, R300_VIC_CMDSIZE, "vic", 0 );
 307                 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(R300_VAP_INPUT_CNTL_0, 2);
 308         ALLOC_STATE( unk21DC, always, 2, "unk21DC", 0 );
 309                 r300->hw.unk21DC.cmd[0] = cmdpacket0(0x21DC, 1);
 310         ALLOC_STATE( unk221C, always, 2, "unk221C", 0 );
 311                 r300->hw.unk221C.cmd[0] = cmdpacket0(0x221C, 1);
 312         ALLOC_STATE( unk2220, always, 5, "unk2220", 0 );
 313                 r300->hw.unk2220.cmd[0] = cmdpacket0(0x2220, 4);
 314         ALLOC_STATE( unk2288, always, 2, "unk2288", 0 );
 315                 r300->hw.unk2288.cmd[0] = cmdpacket0(0x2288, 1);
 316         ALLOC_STATE( vof, always, R300_VOF_CMDSIZE, "vof", 0 );
 317                 r300->hw.vof.cmd[R300_VOF_CMD_0] = cmdpacket0(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 318         ALLOC_STATE( pvs, always, R300_PVS_CMDSIZE, "pvs", 0 );
 319                 r300->hw.pvs.cmd[R300_PVS_CMD_0] = cmdpacket0(R300_VAP_PVS_CNTL_1, 3);
 320         ALLOC_STATE( gb_enable, always, 2, "gb_enable", 0 );
 321                 r300->hw.gb_enable.cmd[0] = cmdpacket0(R300_GB_ENABLE, 1);
 322         ALLOC_STATE( gb_misc, always, R300_GB_MISC_CMDSIZE, "gb_misc", 0 );
 323                 r300->hw.gb_misc.cmd[0] = cmdpacket0(R300_GB_MSPOS0, 5);
 324         ALLOC_STATE( txe, always, R300_TXE_CMDSIZE, "txe", 0 );
 325                 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(R300_TX_ENABLE, 1);
 326         ALLOC_STATE( unk4200, always, 5, "unk4200", 0 );
 327                 r300->hw.unk4200.cmd[0] = cmdpacket0(0x4200, 4);
 328         ALLOC_STATE( unk4214, always, 2, "unk4214", 0 );
 329                 r300->hw.unk4214.cmd[0] = cmdpacket0(0x4214, 1);
 330         ALLOC_STATE( ps, always, R300_PS_CMDSIZE, "ps", 0 );
 331                 r300->hw.ps.cmd[0] = cmdpacket0(R300_RE_POINTSIZE, 1);
 332         ALLOC_STATE( unk4230, always, 4, "unk4230", 0 );
 333                 r300->hw.unk4230.cmd[0] = cmdpacket0(0x4230, 3);
 334         ALLOC_STATE( lcntl, always, 2, "lcntl", 0 );
 335                 r300->hw.lcntl.cmd[0] = cmdpacket0(R300_RE_LINE_CNT, 1);
 336         ALLOC_STATE( unk4260, always, 4, "unk4260", 0 );
 337                 r300->hw.unk4260.cmd[0] = cmdpacket0(0x4260, 3);
 338         ALLOC_STATE( unk4274, always, 5, "unk4274", 0 );
 339                 r300->hw.unk4274.cmd[0] = cmdpacket0(0x4274, 4);
 340         ALLOC_STATE( unk4288, always, 4, "unk4288", 0 );
 341                 r300->hw.unk4288.cmd[0] = cmdpacket0(0x4288, 3);
 342         ALLOC_STATE( fogp, always, 3, "fogp", 0 );
 343                 r300->hw.fogp.cmd[0] = cmdpacket0(R300_RE_FOG_SCALE, 2);
 344         ALLOC_STATE( unk42A0, always, 2, "unk42A0", 0 );
 345                 r300->hw.unk42A0.cmd[0] = cmdpacket0(0x42A0, 1);
 346         ALLOC_STATE( zbs, always, R300_ZBS_CMDSIZE, "zbs", 0 );
 347                 r300->hw.zbs.cmd[R300_ZBS_CMD_0] = cmdpacket0(R300_RE_ZBIAS_T_FACTOR, 4);
 348         ALLOC_STATE( unk42B4, always, 2, "unk42B4", 0 );
 349                 r300->hw.unk42B4.cmd[0] = cmdpacket0(0x42B4, 1);
 350         ALLOC_STATE( cul, always, R300_CUL_CMDSIZE, "cul", 0 );
 351                 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(R300_RE_CULL_CNTL, 1);
 352         ALLOC_STATE( unk42C0, always, 3, "unk42C0", 0 );
 353                 r300->hw.unk42C0.cmd[0] = cmdpacket0(0x42C0, 2);
 354         ALLOC_STATE( rc, always, R300_RC_CMDSIZE, "rc", 0 );
 355                 r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(R300_RS_CNTL_0, 2);
 356         ALLOC_STATE( ri, always, R300_RI_CMDSIZE, "ri", 0 );
 357                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(R300_RS_INTERP_0, 8);
 358         ALLOC_STATE( rr, variable, R300_RR_CMDSIZE, "rr", 0 );
 359                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_ROUTE_0, 1);
 360         ALLOC_STATE( unk43A4, always, 3, "unk43A4", 0 );
 361                 r300->hw.unk43A4.cmd[0] = cmdpacket0(0x43A4, 2);
 362         ALLOC_STATE( unk43E8, always, 2, "unk43E8", 0 );
 363                 r300->hw.unk43E8.cmd[0] = cmdpacket0(0x43E8, 1);
 364         ALLOC_STATE( fp, always, R300_FP_CMDSIZE, "fp", 0 );
 365                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(R300_PFS_CNTL_0, 3);
 366                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(R300_PFS_NODE_0, 4);
 367         ALLOC_STATE( fpt, variable, R300_FPT_CMDSIZE, "fpt", 0 );
 368                 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(R300_PFS_TEXI_0, 0);
 369         ALLOC_STATE( unk46A4, always, 6, "unk46A4", 0 );
 370                 r300->hw.unk46A4.cmd[0] = cmdpacket0(0x46A4, 5);
 371         ALLOC_STATE( fpi[0], variable, R300_FPI_CMDSIZE, "fpi/0", 0 );
 372                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR0_0, 1);
 373         ALLOC_STATE( fpi[1], variable, R300_FPI_CMDSIZE, "fpi/1", 1 );
 374                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR1_0, 1);
 375         ALLOC_STATE( fpi[2], variable, R300_FPI_CMDSIZE, "fpi/2", 2 );
 376                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR2_0, 1);
 377         ALLOC_STATE( fpi[3], variable, R300_FPI_CMDSIZE, "fpi/3", 3 );
 378                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR3_0, 1);
 379         ALLOC_STATE( fogs, always, R300_FOGS_CMDSIZE, "fogs", 0 );
 380                 r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(R300_RE_FOG_STATE, 1);
 381         ALLOC_STATE( fogc, always, R300_FOGC_CMDSIZE, "fogc", 0 );
 382                 r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(R300_FOG_COLOR_R, 3);
 383         ALLOC_STATE( at, always, R300_AT_CMDSIZE, "at", 0 );
 384                 r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(R300_PP_ALPHA_TEST, 2);
 385         ALLOC_STATE( unk4BD8, always, 2, "unk4BD8", 0 );
 386                 r300->hw.unk4BD8.cmd[0] = cmdpacket0(0x4BD8, 1);
 387         ALLOC_STATE( fpp, variable, R300_FPP_CMDSIZE, "fpp", 0 );
 388                 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(R300_PFS_PARAM_0_X, 0);
 389         ALLOC_STATE( unk4E00, always, 2, "unk4E00", 0 );
 390                 r300->hw.unk4E00.cmd[0] = cmdpacket0(0x4E00, 1);
 391         ALLOC_STATE( bld, always, R300_BLD_CMDSIZE, "bld", 0 );
 392                 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(R300_RB3D_CBLEND, 2);
 393         ALLOC_STATE( cmk, always, R300_CMK_CMDSIZE, "cmk", 0 );
 394                 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(R300_RB3D_COLORMASK, 1);
 395         ALLOC_STATE( unk4E10, always, 4, "unk4E10", 0 );
 396                 r300->hw.unk4E10.cmd[0] = cmdpacket0(0x4E10, 3);
 397         ALLOC_STATE( cb, always, R300_CB_CMDSIZE, "cb", 0 );
 398                 r300->hw.cb.cmd[R300_CB_CMD_0] = cmdpacket0(R300_RB3D_COLOROFFSET0, 1);
 399                 r300->hw.cb.cmd[R300_CB_CMD_1] = cmdpacket0(R300_RB3D_COLORPITCH0, 1);
 400         ALLOC_STATE( unk4E50, always, 10, "unk4E50", 0 );
 401                 r300->hw.unk4E50.cmd[0] = cmdpacket0(0x4E50, 9);
 402         ALLOC_STATE( unk4E88, always, 2, "unk4E88", 0 );
 403                 r300->hw.unk4E88.cmd[0] = cmdpacket0(0x4E88, 1);
 404         ALLOC_STATE( unk4EA0, always, 3, "unk4EA0 R350 only", 0 );
 405                 r300->hw.unk4EA0.cmd[0] = cmdpacket0(0x4EA0, 2);
 406         ALLOC_STATE( zs, always, R300_ZS_CMDSIZE, "zstencil", 0 );
 407                 r300->hw.zs.cmd[R300_ZS_CMD_0] = cmdpacket0(R300_RB3D_ZSTENCIL_CNTL_0, 3);
 408         ALLOC_STATE( unk4F10, always, 5, "unk4F10", 0 );
 409                 r300->hw.unk4F10.cmd[0] = cmdpacket0(0x4F10, 4);
 410         ALLOC_STATE( zb, always, R300_ZB_CMDSIZE, "zb", 0 );
 411                 r300->hw.zb.cmd[R300_ZB_CMD_0] = cmdpacket0(R300_RB3D_DEPTHOFFSET, 2);
 412         ALLOC_STATE( unk4F28, always, 2, "unk4F28", 0 );
 413                 r300->hw.unk4F28.cmd[0] = cmdpacket0(0x4F28, 1);
 414         ALLOC_STATE( unk4F30, always, 3, "unk4F30", 0 );
 415                 r300->hw.unk4F30.cmd[0] = cmdpacket0(0x4F30, 2);
 416         ALLOC_STATE( unk4F44, always, 2, "unk4F44", 0 );
 417                 r300->hw.unk4F44.cmd[0] = cmdpacket0(0x4F44, 1);
 418         ALLOC_STATE( unk4F54, always, 2, "unk4F54", 0 );
 419                 r300->hw.unk4F54.cmd[0] = cmdpacket0(0x4F54, 1);
 420
 421         ALLOC_STATE( vpi, vpu, R300_VPI_CMDSIZE, "vpi", 0 );
 422                 r300->hw.vpi.cmd[R300_VPI_CMD_0] = cmdvpu(R300_PVS_UPLOAD_PROGRAM, 0);
 423         ALLOC_STATE( vpp, vpu, R300_VPP_CMDSIZE, "vpp", 0 );
 424                 r300->hw.vpp.cmd[R300_VPP_CMD_0] = cmdvpu(R300_PVS_UPLOAD_PARAMETERS, 0);
 425         ALLOC_STATE( vps, vpu, R300_VPS_CMDSIZE, "vps", 0 );
 426                 r300->hw.vps.cmd[R300_VPS_CMD_0] = cmdvpu(R300_PVS_UPLOAD_POINTSIZE, 1);
 427
 428         /* Textures */
 429         ALLOC_STATE( tex.filter, variable, mtu+1, "tex_filter", 0 );
 430                 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FILTER_0, 0);
 431
 432         ALLOC_STATE( tex.unknown1, variable, mtu+1, "tex_unknown1", 0 );
 433                 r300->hw.tex.unknown1.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FILTER1_0, 0);
 434
 435         ALLOC_STATE( tex.size, variable, mtu+1, "tex_size", 0 );
 436                 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_SIZE_0, 0);
 437
 438         ALLOC_STATE( tex.format, variable, mtu+1, "tex_format", 0 );
 439                 r300->hw.tex.format.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FORMAT_0, 0);
 440
 441         ALLOC_STATE( tex.pitch, variable, mtu+1, "tex_pitch", 0 );
 442                 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_PITCH_0, 0);
 443
 444         ALLOC_STATE( tex.offset, variable, mtu+1, "tex_offset", 0 );
 445                 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_OFFSET_0, 0);
 446
 447         ALLOC_STATE( tex.unknown4, variable, mtu+1, "tex_unknown4", 0 );
 448                 r300->hw.tex.unknown4.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_CHROMA_KEY_0, 0);
 449
 450         ALLOC_STATE( tex.border_color, variable, mtu+1, "tex_border_color", 0 );
 451                 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_BORDER_COLOR_0, 0);
 452
 453
 454         /* Setup the atom linked list */
 455         make_empty_list(&r300->hw.atomlist);
 456         r300->hw.atomlist.name = "atom-list";
 457
 458         insert_at_tail(&r300->hw.atomlist, &r300->hw.vpt);
 459         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2080);
 460         insert_at_tail(&r300->hw.atomlist, &r300->hw.vte);
 461         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2134);
 462         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2140);
 463         insert_at_tail(&r300->hw.atomlist, &r300->hw.vir[0]);
 464         insert_at_tail(&r300->hw.atomlist, &r300->hw.vir[1]);
 465         insert_at_tail(&r300->hw.atomlist, &r300->hw.vic);
 466         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk21DC);
 467         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk221C);
 468         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2220);
 469         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2288);
 470         insert_at_tail(&r300->hw.atomlist, &r300->hw.vof);
 471         insert_at_tail(&r300->hw.atomlist, &r300->hw.pvs);
 472         insert_at_tail(&r300->hw.atomlist, &r300->hw.gb_enable);
 473         insert_at_tail(&r300->hw.atomlist, &r300->hw.gb_misc);
 474         insert_at_tail(&r300->hw.atomlist, &r300->hw.txe);
 475         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4200);
 476         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4214);
 477         insert_at_tail(&r300->hw.atomlist, &r300->hw.ps);
 478         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4230);
 479         insert_at_tail(&r300->hw.atomlist, &r300->hw.lcntl);
 480         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4260);
 481         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4274);
 482         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4288);
 483         insert_at_tail(&r300->hw.atomlist, &r300->hw.fogp);
 484         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk42A0);
 485         insert_at_tail(&r300->hw.atomlist, &r300->hw.zbs);
 486         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk42B4);
 487         insert_at_tail(&r300->hw.atomlist, &r300->hw.cul);
 488         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk42C0);
 489         insert_at_tail(&r300->hw.atomlist, &r300->hw.rc);
 490         insert_at_tail(&r300->hw.atomlist, &r300->hw.ri);
 491         insert_at_tail(&r300->hw.atomlist, &r300->hw.rr);
 492         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk43A4);
 493         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk43E8);
 494         insert_at_tail(&r300->hw.atomlist, &r300->hw.fp);
 495         insert_at_tail(&r300->hw.atomlist, &r300->hw.fpt);
 496         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk46A4);
 497         insert_at_tail(&r300->hw.atomlist, &r300->hw.fpi[0]);
 498         insert_at_tail(&r300->hw.atomlist, &r300->hw.fpi[1]);
 499         insert_at_tail(&r300->hw.atomlist, &r300->hw.fpi[2]);
 500         insert_at_tail(&r300->hw.atomlist, &r300->hw.fpi[3]);
 501         insert_at_tail(&r300->hw.atomlist, &r300->hw.fogs);
 502         insert_at_tail(&r300->hw.atomlist, &r300->hw.fogc);
 503         insert_at_tail(&r300->hw.atomlist, &r300->hw.at);
 504         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4BD8);
 505         insert_at_tail(&r300->hw.atomlist, &r300->hw.fpp);
 506         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E00);
 507         insert_at_tail(&r300->hw.atomlist, &r300->hw.bld);
 508         insert_at_tail(&r300->hw.atomlist, &r300->hw.cmk);
 509         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E10);
 510         insert_at_tail(&r300->hw.atomlist, &r300->hw.cb);
 511         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E50);
 512         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E88);
 513         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4EA0);
 514         insert_at_tail(&r300->hw.atomlist, &r300->hw.zs);
 515         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F10);
 516         insert_at_tail(&r300->hw.atomlist, &r300->hw.zb);
 517         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F28);
 518         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F30);
 519         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F44);
 520         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F54);
 521
 522         insert_at_tail(&r300->hw.atomlist, &r300->hw.vpi);
 523         insert_at_tail(&r300->hw.atomlist, &r300->hw.vpp);
 524         insert_at_tail(&r300->hw.atomlist, &r300->hw.vps);
 525
 526         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.filter);
 527         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.unknown1);
 528         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.size);
 529         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.format);
 530         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.pitch);
 531         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.offset);
 532         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.unknown4);
 533         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.border_color);
 534
 535         r300->hw.is_dirty = GL_TRUE;
 536         r300->hw.all_dirty = GL_TRUE;
 537
 538         /* Initialize command buffer */
 539         size = 256 * driQueryOptioni(&r300->radeon.optionCache, "command_buffer_size");
 540         if (size < 2*r300->hw.max_state_size) {
 541                 size = 2*r300->hw.max_state_size+65535;
 542         }
 543         if (size > 64*256)
 544                 size = 64*256;
 545
 546         if (RADEON_DEBUG & (DEBUG_IOCTL|DEBUG_DMA)) {
 547                 fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%ld\n",
 548                         sizeof(drm_r300_cmd_header_t));
 549                 fprintf(stderr, "sizeof(drm_radeon_cmd_buffer_t)=%ld\n",
 550                         sizeof(drm_radeon_cmd_buffer_t));
 551                 fprintf(stderr,
 552                         "Allocating %d bytes command buffer (max state is %d bytes)\n",
 553                         size*4, r300->hw.max_state_size*4);
 554         }
 555
 556         r300->cmdbuf.size = size;
 557         r300->cmdbuf.cmd_buf = (uint32_t*)CALLOC(size*4);
 558         r300->cmdbuf.count_used = 0;
 559         r300->cmdbuf.count_reemit = 0;
 560 }
 561
 562
 563 /**
 564  * Destroy the command buffer and state atoms.
 565  */
 566 void r300DestroyCmdBuf(r300ContextPtr r300)
 567 {
 568         struct r300_state_atom* atom;
 569
 570         FREE(r300->cmdbuf.cmd_buf);
 571
 572         foreach(atom, &r300->hw.atomlist) {
 573                 FREE(atom->cmd);
 574         }
 575 }
 576
 577 void r300EmitBlit(r300ContextPtr rmesa,
 578                   GLuint color_fmt,
 579                   GLuint src_pitch,
 580                   GLuint src_offset,
 581                   GLuint dst_pitch,
 582                   GLuint dst_offset,
 583                   GLint srcx, GLint srcy,
 584                   GLint dstx, GLint dsty, GLuint w, GLuint h)
 585 {
 586         drm_r300_cmd_header_t *cmd;
 587
 588         if (RADEON_DEBUG & DEBUG_IOCTL)
 589                 fprintf(stderr,
 590                         "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
 591                         __FUNCTION__, src_pitch, src_offset, srcx, srcy,
 592                         dst_pitch, dst_offset, dstx, dsty, w, h);
 593
 594         assert((src_pitch & 63) == 0);
 595         assert((dst_pitch & 63) == 0);
 596         assert((src_offset & 1023) == 0);
 597         assert((dst_offset & 1023) == 0);
 598         assert(w < (1 << 16));
 599         assert(h < (1 << 16));
 600
 601         cmd = (drm_r300_cmd_header_t *) r300AllocCmdBuf(rmesa, 8,
 602                                                         __FUNCTION__);
 603
 604         cmd[0].header.cmd_type = R300_CMD_PACKET3;
 605         cmd[0].header.pad0 = R300_CMD_PACKET3_RAW;
 606         cmd[1].u = R200_CP_CMD_BITBLT_MULTI | (5 << 16);
 607         cmd[2].u = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 608                     RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 609                     RADEON_GMC_BRUSH_NONE |
 610                     (color_fmt << 8) |
 611                     RADEON_GMC_SRC_DATATYPE_COLOR |
 612                     RADEON_ROP3_S |
 613                     RADEON_DP_SRC_SOURCE_MEMORY |
 614                     RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
 615
 616         cmd[3].u = ((src_pitch / 64) << 22) | (src_offset >> 10);
 617         cmd[4].u = ((dst_pitch / 64) << 22) | (dst_offset >> 10);
 618         cmd[5].u = (srcx << 16) | srcy;
 619         cmd[6].u = (dstx << 16) | dsty; /* dst */
 620         cmd[7].u = (w << 16) | h;
 621 }
 622
 623 void r300EmitWait(r300ContextPtr rmesa, GLuint flags)
 624 {
 625         drm_r300_cmd_header_t *cmd;
 626
 627         assert(!(flags & ~(R300_WAIT_2D | R300_WAIT_3D)));
 628
 629         cmd = (drm_r300_cmd_header_t *) r300AllocCmdBuf(rmesa, 1,
 630                                                         __FUNCTION__);
 631         cmd[0].u = 0;
 632         cmd[0].wait.cmd_type = R300_CMD_WAIT;
 633         cmd[0].wait.flags = flags;
 634 }
 635
 636 void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
 637 {
 638     int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
 639     int i;
 640     LOCAL_VARS
 641
 642     if (RADEON_DEBUG & DEBUG_VERTS)
 643         fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __func__, nr, offset);
 644
 645     start_packet3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, sz-1);
 646     e32(nr);
 647     for(i=0;i+1<nr;i+=2){
 648         e32(  (rmesa->state.aos[i].aos_size << 0)
 649              |(rmesa->state.aos[i].aos_stride << 8)
 650              |(rmesa->state.aos[i+1].aos_size << 16)
 651              |(rmesa->state.aos[i+1].aos_stride << 24)
 652         );
 653         e32(rmesa->state.aos[i].aos_offset+offset*4*rmesa->state.aos[i].aos_stride);
 654         e32(rmesa->state.aos[i+1].aos_offset+offset*4*rmesa->state.aos[i+1].aos_stride);
 655     }
 656     if(nr & 1){
 657         e32(  (rmesa->state.aos[nr-1].aos_size << 0)
 658              |(rmesa->state.aos[nr-1].aos_stride << 8)
 659         );
 660         e32(rmesa->state.aos[nr-1].aos_offset+offset*4*rmesa->state.aos[nr-1].aos_stride);
 661     }
 662
 663 }
 664