src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #include "main/glheader.h"
  37 #include "main/state.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "swrast/swrast.h"
  43
  44 #include "drm.h"
  45 #include "radeon_drm.h"
  46
  47 #include "r300_context.h"
  48 #include "r300_ioctl.h"
  49 #include "radeon_reg.h"
  50 #include "r300_reg.h"
  51 #include "r300_cmdbuf.h"
  52 #include "r300_emit.h"
  53 #include "radeon_bocs_wrapper.h"
  54 #include "radeon_mipmap_tree.h"
  55 #include "r300_state.h"
  56 #include "radeon_reg.h"
  57
  58 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
  59 #   define RADEON_ONE_REG_WR        (1 << 15)
  60
  61 /** # of dwords reserved for additional instructions that may need to be written
  62  * during flushing.
  63  */
  64 #define SPACE_FOR_FLUSHING      4
  65
  66 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
  67 {
  68     if (r300->radeon.radeonScreen->kernel_mm) {
  69         return ((((*pkt) >> 16) & 0x3FFF) + 1);
  70     } else {
  71         drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
  72         return t->packet0.count;
  73     }
  74     return 0;
  75 }
  76
  77 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
  78 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
  79
  80 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
  81 {
  82         r300ContextPtr r300 = R300_CONTEXT(ctx);
  83         BATCH_LOCALS(&r300->radeon);
  84         drm_r300_cmd_header_t cmd;
  85         uint32_t addr, ndw, i;
  86
  87         if (!r300->radeon.radeonScreen->kernel_mm) {
  88                 uint32_t dwords;
  89                 dwords = (*atom->check) (ctx, atom);
  90                 BEGIN_BATCH_NO_AUTOSTATE(dwords);
  91                 OUT_BATCH_TABLE(atom->cmd, dwords);
  92                 END_BATCH();
  93                 return;
  94         }
  95
  96         cmd.u = atom->cmd[0];
  97         addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
  98         ndw = cmd.vpu.count * 4;
  99         if (ndw) {
 100
 101                 if (r300->vap_flush_needed) {
 102                         BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
 103
 104                         /* flush processing vertices */
 105                         OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
 106                         OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 107                         OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 108                         OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
 109                         OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 110                         r300->vap_flush_needed = GL_FALSE;
 111                 } else {
 112                         BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
 113                 }
 114                 OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
 115                 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
 116                 for (i = 0; i < ndw; i++) {
 117                         OUT_BATCH(atom->cmd[i+1]);
 118                 }
 119                 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 120                 END_BATCH();
 121         }
 122 }
 123
 124 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
 125 {
 126         r300ContextPtr r300 = R300_CONTEXT(ctx);
 127         BATCH_LOCALS(&r300->radeon);
 128         drm_r300_cmd_header_t cmd;
 129         uint32_t addr, ndw, i, sz;
 130         int type, clamp, stride;
 131
 132         if (!r300->radeon.radeonScreen->kernel_mm) {
 133                 uint32_t dwords;
 134                 dwords = (*atom->check) (ctx, atom);
 135                 BEGIN_BATCH_NO_AUTOSTATE(dwords);
 136                 OUT_BATCH_TABLE(atom->cmd, dwords);
 137                 END_BATCH();
 138                 return;
 139         }
 140
 141         cmd.u = atom->cmd[0];
 142         sz = cmd.r500fp.count;
 143         addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
 144         type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
 145         clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
 146
 147         addr |= (type << 16);
 148         addr |= (clamp << 17);
 149
 150         stride = type ? 4 : 6;
 151
 152         ndw = sz * stride;
 153         if (ndw) {
 154
 155                 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
 156                 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
 157                 OUT_BATCH(addr);
 158                 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
 159                 for (i = 0; i < ndw; i++) {
 160                         OUT_BATCH(atom->cmd[i+1]);
 161                 }
 162                 END_BATCH();
 163         }
 164 }
 165
 166 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 167 {
 168         r300ContextPtr r300 = R300_CONTEXT(ctx);
 169         BATCH_LOCALS(&r300->radeon);
 170         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 171         int notexture = 0;
 172
 173         if (numtmus) {
 174                 int i;
 175
 176                 for(i = 0; i < numtmus; ++i) {
 177                     radeonTexObj *t = r300->hw.textures[i];
 178
 179                     if (!t)
 180                         notexture = 1;
 181                 }
 182
 183                 if (r300->radeon.radeonScreen->kernel_mm && notexture) {
 184                         return;
 185                 }
 186                 BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus);
 187                 for(i = 0; i < numtmus; ++i) {
 188                     radeonTexObj *t = r300->hw.textures[i];
 189                     OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 190                     if (t && !t->image_override) {
 191                             OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
 192                                             RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 193                     } else if (!t) {
 194                             OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
 195                     } else { /* override cases */
 196                             if (t->bo) {
 197                                     OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
 198                                                     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 199                             } else if (!r300->radeon.radeonScreen->kernel_mm) {
 200                                     OUT_BATCH(t->override_offset);
 201                             }
 202                             else
 203                                 OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
 204                     }
 205                 }
 206                 END_BATCH();
 207         }
 208 }
 209
 210 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 211 {
 212         r300ContextPtr r300 = R300_CONTEXT(ctx);
 213         BATCH_LOCALS(&r300->radeon);
 214         struct radeon_renderbuffer *rrb;
 215         uint32_t cbpitch;
 216         uint32_t offset = r300->radeon.state.color.draw_offset;
 217         uint32_t dw = 6;
 218
 219         rrb = radeon_get_colorbuffer(&r300->radeon);
 220         if (!rrb || !rrb->bo) {
 221                 fprintf(stderr, "no rrb\n");
 222                 return;
 223         }
 224
 225         cbpitch = (rrb->pitch / rrb->cpp);
 226         if (rrb->cpp == 4)
 227                 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
 228         else
 229                 cbpitch |= R300_COLOR_FORMAT_RGB565;
 230
 231         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 232                 cbpitch |= R300_COLOR_TILE_ENABLE;
 233
 234         if (r300->radeon.radeonScreen->kernel_mm)
 235                 dw += 2;
 236         BEGIN_BATCH_NO_AUTOSTATE(dw);
 237         OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
 238         OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 239         OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
 240         if (!r300->radeon.radeonScreen->kernel_mm)
 241                 OUT_BATCH(cbpitch);
 242         else
 243                 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 244         END_BATCH();
 245     if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 246         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 247             BEGIN_BATCH_NO_AUTOSTATE(3);
 248             OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 249             OUT_BATCH(0);
 250             OUT_BATCH((rrb->width << R300_SCISSORS_X_SHIFT) |
 251                     (rrb->height << R300_SCISSORS_Y_SHIFT));
 252             END_BATCH();
 253         } else {
 254             BEGIN_BATCH_NO_AUTOSTATE(3);
 255             OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 256             OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
 257                     (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
 258             OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET) << R300_SCISSORS_X_SHIFT) |
 259                     ((rrb->height + R300_SCISSORS_OFFSET) << R300_SCISSORS_Y_SHIFT));
 260             END_BATCH();
 261         }
 262     }
 263 }
 264
 265 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 266 {
 267         r300ContextPtr r300 = R300_CONTEXT(ctx);
 268         BATCH_LOCALS(&r300->radeon);
 269         struct radeon_renderbuffer *rrb;
 270         uint32_t zbpitch;
 271
 272         rrb = radeon_get_depthbuffer(&r300->radeon);
 273         if (!rrb)
 274                 return;
 275
 276         zbpitch = (rrb->pitch / rrb->cpp);
 277         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
 278                 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
 279         }
 280         if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 281                 zbpitch |= R300_DEPTHMICROTILE_TILED;
 282         }
 283
 284         BEGIN_BATCH_NO_AUTOSTATE(6);
 285         OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 286         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 287         OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
 288         END_BATCH();
 289 }
 290
 291 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
 292 {
 293         r300ContextPtr r300 = R300_CONTEXT(ctx);
 294         BATCH_LOCALS(&r300->radeon);
 295         struct radeon_renderbuffer *rrb;
 296         uint32_t format = 0;
 297
 298         rrb = radeon_get_depthbuffer(&r300->radeon);
 299         if (!rrb)
 300           format = 0;
 301         else {
 302           if (rrb->cpp == 2)
 303             format = R300_DEPTHFORMAT_16BIT_INT_Z;
 304           else if (rrb->cpp == 4)
 305             format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
 306         }
 307
 308         OUT_BATCH(atom->cmd[0]);
 309         atom->cmd[1] &= ~0xf;
 310         atom->cmd[1] |= format;
 311         OUT_BATCH(atom->cmd[1]);
 312         OUT_BATCH(atom->cmd[2]);
 313         OUT_BATCH(atom->cmd[3]);
 314         OUT_BATCH(atom->cmd[4]);
 315 }
 316
 317 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 318 {
 319         return atom->cmd_size;
 320 }
 321
 322 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
 323 {
 324         r300ContextPtr r300 = R300_CONTEXT(ctx);
 325         int cnt;
 326         if (atom->cmd[0] == CP_PACKET2) {
 327                 return 0;
 328         }
 329         cnt = packet0_count(r300, atom->cmd);
 330         return cnt ? cnt + 1 : 0;
 331 }
 332
 333 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
 334 {
 335         int cnt;
 336
 337         cnt = vpu_count(atom->cmd);
 338         return cnt ? (cnt * 4) + 1 : 0;
 339 }
 340
 341 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
 342 {
 343         int cnt;
 344
 345         cnt = r500fp_count(atom->cmd);
 346         return cnt ? (cnt * 6) + 1 : 0;
 347 }
 348
 349 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
 350 {
 351         int cnt;
 352
 353         cnt = r500fp_count(atom->cmd);
 354         return cnt ? (cnt * 4) + 1 : 0;
 355 }
 356
 357 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )                               \
 358    do {                                                                 \
 359       r300->hw.ATOM.cmd_size = (SZ);                                    \
 360       r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 361       r300->hw.ATOM.name = #ATOM;                                       \
 362       r300->hw.ATOM.idx = (IDX);                                        \
 363       r300->hw.ATOM.check = check_##CHK;                                \
 364       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 365       r300->radeon.hw.max_state_size += (SZ);                                   \
 366       insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM);                \
 367    } while (0)
 368 /**
 369  * Allocate memory for the command buffer and initialize the state atom
 370  * list. Note that the initial hardware state is set by r300InitState().
 371  */
 372 void r300InitCmdBuf(r300ContextPtr r300)
 373 {
 374         int mtu;
 375         int has_tcl = 1;
 376         int is_r500 = 0;
 377         int i;
 378
 379         if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
 380                 has_tcl = 0;
 381
 382         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 383                 is_r500 = 1;
 384
 385         r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
 386
 387         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 388         if (RADEON_DEBUG & DEBUG_TEXTURE) {
 389                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 390         }
 391
 392         /* Setup the atom linked list */
 393         make_empty_list(&r300->radeon.hw.atomlist);
 394         r300->radeon.hw.atomlist.name = "atom-list";
 395
 396         /* Initialize state atoms */
 397         ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
 398         r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
 399         ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
 400         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 401         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
 402         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
 403         if (is_r500) {
 404             ALLOC_STATE(vap_index_offset, always, 2, 0);
 405             r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
 406             r300->hw.vap_index_offset.cmd[1] = 0;
 407         }
 408         ALLOC_STATE(vte, always, 3, 0);
 409         r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
 410         ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
 411         r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
 412         ALLOC_STATE(vap_cntl_status, always, 2, 0);
 413         r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
 414         ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
 415         r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
 416             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
 417         ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
 418         r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
 419             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 420         ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
 421         r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
 422         ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 423         r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 424
 425         if (has_tcl) {
 426                 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 427                 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
 428                 ALLOC_STATE(vap_clip, always, 5, 0);
 429                 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
 430                 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
 431                 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
 432         }
 433
 434         ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
 435         r300->hw.vof.cmd[R300_VOF_CMD_0] =
 436             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
 437
 438         if (has_tcl) {
 439                 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
 440                 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
 441                     cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
 442         }
 443
 444         ALLOC_STATE(gb_enable, always, 2, 0);
 445         r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
 446         ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
 447         r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5);
 448         ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
 449         r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
 450         ALLOC_STATE(ga_point_s0, always, 5, 0);
 451         r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
 452         ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
 453         r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
 454         ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
 455         r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
 456         ALLOC_STATE(ga_point_minmax, always, 4, 0);
 457         r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
 458         ALLOC_STATE(lcntl, always, 2, 0);
 459         r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
 460         ALLOC_STATE(ga_line_stipple, always, 4, 0);
 461         r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
 462         ALLOC_STATE(shade, always, 5, 0);
 463         r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4);
 464         ALLOC_STATE(polygon_mode, always, 4, 0);
 465         r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
 466         ALLOC_STATE(fogp, always, 3, 0);
 467         r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
 468         ALLOC_STATE(zbias_cntl, always, 2, 0);
 469         r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
 470         ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
 471         r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
 472             cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 473         ALLOC_STATE(occlusion_cntl, always, 2, 0);
 474         r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
 475         ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
 476         r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
 477         ALLOC_STATE(su_depth_scale, always, 3, 0);
 478         r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
 479         ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
 480         r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
 481         if (is_r500) {
 482                 ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
 483                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
 484                 for (i = 0; i < 8; i++) {
 485                         r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
 486                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 487                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 488                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 489                           (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
 490                 }
 491                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 492                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
 493         } else {
 494                 ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
 495                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
 496                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 497                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
 498         }
 499         ALLOC_STATE(sc_hyperz, always, 3, 0);
 500         r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
 501         ALLOC_STATE(sc_screendoor, always, 2, 0);
 502         r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 503         ALLOC_STATE(us_out_fmt, always, 6, 0);
 504         r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
 505
 506         if (is_r500) {
 507                 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
 508                 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
 509                 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
 510                 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
 511                 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
 512                 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
 513
 514                 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
 515                 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
 516                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
 517                 r300->hw.r500fp.emit = emit_r500fp;
 518                 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
 519                 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
 520                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
 521                 r300->hw.r500fp_const.emit = emit_r500fp;
 522         } else {
 523                 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 524                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
 525                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
 526
 527                 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
 528                 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
 529
 530                 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
 531                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
 532                 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
 533                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
 534                 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
 535                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
 536                 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
 537                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
 538                 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
 539                 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
 540         }
 541         ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
 542         r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
 543         ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
 544         r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
 545         ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
 546         r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
 547         ALLOC_STATE(fg_depth_src, always, 2, 0);
 548         r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
 549         ALLOC_STATE(rb3d_cctl, always, 2, 0);
 550         r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
 551         ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
 552         r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
 553         ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
 554         r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
 555         if (is_r500) {
 556                 ALLOC_STATE(blend_color, always, 3, 0);
 557                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
 558         } else {
 559                 ALLOC_STATE(blend_color, always, 2, 0);
 560                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
 561         }
 562         ALLOC_STATE(rop, always, 2, 0);
 563         r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
 564         ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
 565         r300->hw.cb.emit = &emit_cb_offset;
 566         ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
 567         r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
 568         ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 569         r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
 570         ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
 571         r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
 572         ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
 573         r300->hw.zs.cmd[R300_ZS_CMD_0] =
 574             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
 575
 576         ALLOC_STATE(zstencil_format, always, 5, 0);
 577         r300->hw.zstencil_format.cmd[0] =
 578             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
 579         r300->hw.zstencil_format.emit = emit_zstencil_format;
 580
 581         ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
 582         r300->hw.zb.emit = emit_zb_offset;
 583         ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
 584         r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
 585         ALLOC_STATE(unk4F30, always, 3, 0);
 586         r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2);
 587         ALLOC_STATE(zb_hiz_offset, always, 2, 0);
 588         r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
 589         ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
 590         r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
 591
 592         /* VPU only on TCL */
 593         if (has_tcl) {
 594                 int i;
 595                 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 596                 r300->hw.vpi.cmd[0] =
 597                     cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
 598                 r300->hw.vpi.emit = emit_vpu;
 599
 600                 if (is_r500) {
 601                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 602                     r300->hw.vpp.cmd[0] =
 603                         cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
 604                     r300->hw.vpp.emit = emit_vpu;
 605
 606                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 607                     r300->hw.vps.cmd[0] =
 608                         cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
 609                     r300->hw.vps.emit = emit_vpu;
 610
 611                         for (i = 0; i < 6; i++) {
 612                           ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 613                           r300->hw.vpucp[i].cmd[0] =
 614                                   cmdvpu(r300->radeon.radeonScreen,
 615                            R500_PVS_UCP_START + i, 1);
 616                                 r300->hw.vpucp[i].emit = emit_vpu;
 617                         }
 618                 } else {
 619                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 620                     r300->hw.vpp.cmd[0] =
 621                         cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
 622                     r300->hw.vpp.emit = emit_vpu;
 623
 624                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 625                     r300->hw.vps.cmd[0] =
 626                         cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
 627                     r300->hw.vps.emit = emit_vpu;
 628
 629                         for (i = 0; i < 6; i++) {
 630                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 631                                 r300->hw.vpucp[i].cmd[0] =
 632                                         cmdvpu(r300->radeon.radeonScreen,
 633                                                R300_PVS_UCP_START + i, 1);
 634                                 r300->hw.vpucp[i].emit = emit_vpu;
 635                         }
 636                 }
 637         }
 638
 639         /* Textures */
 640         ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
 641         r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
 642             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
 643
 644         ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
 645         r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
 646             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
 647
 648         ALLOC_STATE(tex.size, variable, mtu + 1, 0);
 649         r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
 650
 651         ALLOC_STATE(tex.format, variable, mtu + 1, 0);
 652         r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
 653             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
 654
 655         ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
 656         r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
 657
 658         ALLOC_STATE(tex.offset, variable, 1, 0);
 659         r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
 660             cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
 661         r300->hw.tex.offset.emit = &emit_tex_offsets;
 662
 663         ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
 664         r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
 665             cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
 666
 667         ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
 668         r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
 669             cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
 670
 671         r300->radeon.hw.is_dirty = GL_TRUE;
 672         r300->radeon.hw.all_dirty = GL_TRUE;
 673
 674         rcommonInitCmdBuf(&r300->radeon);
 675 }