src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #include "main/glheader.h"
  37 #include "main/state.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "swrast/swrast.h"
  43
  44 #include "drm.h"
  45 #include "radeon_drm.h"
  46
  47 #include "r300_context.h"
  48 #include "r300_reg.h"
  49 #include "r300_cmdbuf.h"
  50 #include "r300_emit.h"
  51 #include "radeon_bocs_wrapper.h"
  52 #include "radeon_mipmap_tree.h"
  53 #include "r300_state.h"
  54 #include "radeon_queryobj.h"
  55
  56 /** # of dwords reserved for additional instructions that may need to be written
  57  * during flushing.
  58  */
  59 #define SPACE_FOR_FLUSHING      4
  60
  61 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
  62 {
  63     if (r300->radeon.radeonScreen->kernel_mm) {
  64         return ((((*pkt) >> 16) & 0x3FFF) + 1);
  65     } else {
  66         drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
  67         return t->packet0.count;
  68     }
  69 }
  70
  71 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
  72 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
  73
  74 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
  75 {
  76         r300ContextPtr r300 = R300_CONTEXT(ctx);
  77         int cnt;
  78         int extra = 1;
  79         cnt = vpu_count(atom->cmd);
  80
  81         if (r300->radeon.radeonScreen->kernel_mm) {
  82                 extra = 5;
  83         }
  84
  85         return cnt ? (cnt * 4) + extra : 0;
  86 }
  87
  88
  89 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
  90 {
  91         r300ContextPtr r300 = R300_CONTEXT(ctx);
  92         BATCH_LOCALS(&r300->radeon);
  93         drm_r300_cmd_header_t cmd;
  94         uint32_t addr, ndw;
  95
  96         cmd.u = atom->cmd[0];
  97         addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
  98         ndw = atom->check(ctx, atom);
  99
 100         BEGIN_BATCH_NO_AUTOSTATE(ndw);
 101
 102         ndw -= 5;
 103         OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
 104         OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
 105         OUT_BATCH_TABLE(&atom->cmd[1], ndw);
 106         OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 107         END_BATCH();
 108 }
 109
 110 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
 111 {
 112         r300ContextPtr r300 = R300_CONTEXT(ctx);
 113         BATCH_LOCALS(&r300->radeon);
 114         drm_r300_cmd_header_t cmd;
 115         uint32_t addr, ndw, sz;
 116         int type, clamp;
 117
 118         ndw = atom->check(ctx, atom);
 119
 120         cmd.u = atom->cmd[0];
 121         sz = cmd.r500fp.count;
 122         addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
 123         type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
 124         clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
 125
 126         addr |= (type << 16);
 127         addr |= (clamp << 17);
 128
 129         BEGIN_BATCH_NO_AUTOSTATE(ndw);
 130         OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
 131         OUT_BATCH(addr);
 132         ndw-=3;
 133         OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
 134         OUT_BATCH_TABLE(&atom->cmd[1], ndw);
 135         END_BATCH();
 136 }
 137
 138 static int check_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 139 {
 140         r300ContextPtr r300 = R300_CONTEXT(ctx);
 141         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 142         int dw = 0, i;
 143         if (atom->cmd[0] == CP_PACKET2) {
 144                 return dw;
 145         }
 146         for(i = 0; i < numtmus; ++i) {
 147                 radeonTexObj *t = r300->hw.textures[i];
 148                 if (!t && !r300->radeon.radeonScreen->kernel_mm) {
 149                         dw += 0;
 150                 } else if (t && t->image_override && !t->bo) {
 151                         if (!r300->radeon.radeonScreen->kernel_mm)
 152                                 dw += 2;
 153                 } else
 154                         dw += 4;
 155         }
 156         return dw;
 157 }
 158
 159 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 160 {
 161         r300ContextPtr r300 = R300_CONTEXT(ctx);
 162         BATCH_LOCALS(&r300->radeon);
 163         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 164         int i;
 165
 166         for(i = 0; i < numtmus; ++i) {
 167                 radeonTexObj *t = r300->hw.textures[i];
 168                 if (t && !t->image_override) {
 169                         BEGIN_BATCH_NO_AUTOSTATE(4);
 170                         OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 171                         OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
 172                                         RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 173                         END_BATCH();
 174                 } else if (!t) {
 175                         /* Texture unit hasn't a texture bound.
 176                          * We assign the current color buffer as a fakery to make
 177                          * KIL work on KMS (without it, the CS checker will complain).
 178                          */
 179                         if (r300->radeon.radeonScreen->kernel_mm) {
 180                                 struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
 181                                 if (rrb && rrb->bo) {
 182                                         BEGIN_BATCH_NO_AUTOSTATE(4);
 183                                         OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 184                                         OUT_BATCH_RELOC(0, rrb->bo, 0,
 185                                                         RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 186                                         END_BATCH();
 187                                 }
 188                         }
 189                 } else { /* override cases */
 190                         if (t->bo) {
 191                                 BEGIN_BATCH_NO_AUTOSTATE(4);
 192                                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 193                                 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
 194                                                 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 195                                 END_BATCH();
 196                         } else if (!r300->radeon.radeonScreen->kernel_mm) {
 197                                 BEGIN_BATCH_NO_AUTOSTATE(2);
 198                                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 199                                 OUT_BATCH(t->override_offset);
 200                                 END_BATCH();
 201                         } else {
 202                                 /* Texture unit hasn't a texture bound nothings to do */
 203                         }
 204                 }
 205         }
 206 }
 207
 208 void r300_emit_scissor(GLcontext *ctx)
 209 {
 210         r300ContextPtr r300 = R300_CONTEXT(ctx);
 211         BATCH_LOCALS(&r300->radeon);
 212     unsigned x1, y1, x2, y2;
 213         struct radeon_renderbuffer *rrb;
 214
 215     if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 216         return;
 217     }
 218         rrb = radeon_get_colorbuffer(&r300->radeon);
 219         if (!rrb || !rrb->bo) {
 220                 fprintf(stderr, "no rrb\n");
 221                 return;
 222         }
 223     if (r300->radeon.state.scissor.enabled) {
 224         x1 = r300->radeon.state.scissor.rect.x1;
 225         y1 = r300->radeon.state.scissor.rect.y1;
 226         x2 = r300->radeon.state.scissor.rect.x2;
 227         y2 = r300->radeon.state.scissor.rect.y2;
 228     } else {
 229         x1 = 0;
 230         y1 = 0;
 231         x2 = rrb->base.Width - 1;
 232         y2 = rrb->base.Height - 1;
 233     }
 234     if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
 235         x1 += R300_SCISSORS_OFFSET;
 236         y1 += R300_SCISSORS_OFFSET;
 237         x2 += R300_SCISSORS_OFFSET;
 238         y2 += R300_SCISSORS_OFFSET;
 239     }
 240     BEGIN_BATCH_NO_AUTOSTATE(3);
 241     OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 242     OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
 243     OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
 244     END_BATCH();
 245 }
 246 static int check_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 247 {
 248         r300ContextPtr r300 = R300_CONTEXT(ctx);
 249         uint32_t dw = 6 + 3 + 16;
 250         if (r300->radeon.radeonScreen->kernel_mm)
 251                 dw += 2;
 252         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 253                 dw -= 3 + 16;
 254         }
 255         return dw;
 256 }
 257
 258 static void emit_scissor(struct r300_context *r300,
 259                          unsigned width,
 260                          unsigned height)
 261 {
 262     int i;
 263     BATCH_LOCALS(&r300->radeon);
 264     if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 265         BEGIN_BATCH_NO_AUTOSTATE(3);
 266         OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 267         OUT_BATCH(0);
 268         OUT_BATCH(((width - 1) << R300_SCISSORS_X_SHIFT) |
 269                 ((height - 1) << R300_SCISSORS_Y_SHIFT));
 270         END_BATCH();
 271         BEGIN_BATCH_NO_AUTOSTATE(16);
 272         for (i = 0; i < 4; i++) {
 273             OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 274             OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
 275             OUT_BATCH(((width - 1) << R300_CLIPRECT_X_SHIFT) | ((height - 1) << R300_CLIPRECT_Y_SHIFT));
 276         }
 277         OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 278         OUT_BATCH(0xAAAA);
 279         OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 280         OUT_BATCH(0xffffff);
 281         END_BATCH();
 282     } else {
 283         BEGIN_BATCH_NO_AUTOSTATE(3);
 284         OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 285         OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
 286                 (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
 287         OUT_BATCH(((width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
 288                 ((height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
 289         END_BATCH();
 290         BEGIN_BATCH_NO_AUTOSTATE(16);
 291         for (i = 0; i < 4; i++) {
 292             OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 293             OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
 294             OUT_BATCH(((R300_SCISSORS_OFFSET + width - 1) << R300_CLIPRECT_X_SHIFT) |
 295                         ((R300_SCISSORS_OFFSET + height - 1) << R300_CLIPRECT_Y_SHIFT));
 296         }
 297         OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 298         OUT_BATCH(0xAAAA);
 299         OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 300         OUT_BATCH(0xffffff);
 301         END_BATCH();
 302     }
 303 }
 304
 305 void r300_emit_cb_setup(struct r300_context *r300,
 306                         struct radeon_bo *bo,
 307                         uint32_t offset,
 308                         GLuint format,
 309                         unsigned cpp,
 310                         unsigned pitch)
 311 {
 312     BATCH_LOCALS(&r300->radeon);
 313     uint32_t cbpitch = pitch / cpp;
 314     uint32_t dw = 6;
 315
 316     assert(offset % 256 == 0);
 317
 318     switch (format) {
 319         case MESA_FORMAT_RGB565:
 320             assert(_mesa_little_endian());
 321             cbpitch |= R300_COLOR_FORMAT_RGB565;
 322             break;
 323         case MESA_FORMAT_RGB565_REV:
 324             assert(!_mesa_little_endian());
 325             cbpitch |= R300_COLOR_FORMAT_RGB565;
 326             break;
 327         case MESA_FORMAT_ARGB4444:
 328             assert(_mesa_little_endian());
 329             cbpitch |= R300_COLOR_FORMAT_ARGB4444;
 330             break;
 331         case MESA_FORMAT_ARGB4444_REV:
 332             assert(!_mesa_little_endian());
 333             cbpitch |= R300_COLOR_FORMAT_ARGB4444;
 334             break;
 335         case MESA_FORMAT_ARGB1555:
 336             assert(_mesa_little_endian());
 337             cbpitch |= R300_COLOR_FORMAT_ARGB1555;
 338             break;
 339         case MESA_FORMAT_ARGB1555_REV:
 340             assert(!_mesa_little_endian());
 341             cbpitch |= R300_COLOR_FORMAT_ARGB1555;
 342             break;
 343         default:
 344             if (cpp == 4) {
 345                 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
 346             } else {
 347                 _mesa_problem(r300->radeon.glCtx, "unexpected format in emit_cb_offset()");;
 348             }
 349             break;
 350     }
 351
 352     if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 353         cbpitch |= R300_COLOR_TILE_ENABLE;
 354
 355     if (r300->radeon.radeonScreen->kernel_mm)
 356         dw += 2;
 357
 358     BEGIN_BATCH_NO_AUTOSTATE(dw);
 359     OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
 360     OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 361     OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
 362     if (!r300->radeon.radeonScreen->kernel_mm)
 363         OUT_BATCH(cbpitch);
 364     else
 365         OUT_BATCH_RELOC(cbpitch, bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 366     END_BATCH();
 367 }
 368
 369 static void emit_cb_offset_atom(GLcontext *ctx, struct radeon_state_atom * atom)
 370 {
 371     r300ContextPtr r300 = R300_CONTEXT(ctx);
 372     struct radeon_renderbuffer *rrb;
 373     uint32_t offset = r300->radeon.state.color.draw_offset;
 374
 375     rrb = radeon_get_colorbuffer(&r300->radeon);
 376     if (!rrb || !rrb->bo) {
 377         fprintf(stderr, "no rrb\n");
 378         return;
 379     }
 380
 381     if (RADEON_DEBUG & RADEON_STATE)
 382         fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
 383
 384     r300_emit_cb_setup(r300, rrb->bo, offset, rrb->base.Format, rrb->cpp, rrb->pitch);
 385
 386     if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 387         emit_scissor(r300, rrb->base.Width, rrb->base.Height);
 388     }
 389 }
 390
 391 static int check_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 392 {
 393         r300ContextPtr r300 = R300_CONTEXT(ctx);
 394         uint32_t dw;
 395         dw = 6;
 396         if (r300->radeon.radeonScreen->kernel_mm)
 397                 dw += 2;
 398         return dw;
 399 }
 400
 401 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 402 {
 403         r300ContextPtr r300 = R300_CONTEXT(ctx);
 404         BATCH_LOCALS(&r300->radeon);
 405         struct radeon_renderbuffer *rrb;
 406         uint32_t zbpitch;
 407         uint32_t dw = atom->check(ctx, atom);
 408
 409         rrb = radeon_get_depthbuffer(&r300->radeon);
 410         if (!rrb)
 411                 return;
 412
 413         zbpitch = (rrb->pitch / rrb->cpp);
 414         if (!r300->radeon.radeonScreen->kernel_mm) {
 415             if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
 416                 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
 417            }
 418             if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 419                 zbpitch |= R300_DEPTHMICROTILE_TILED;
 420             }
 421         }
 422
 423         BEGIN_BATCH_NO_AUTOSTATE(dw);
 424         OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 425         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 426         OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
 427         if (!r300->radeon.radeonScreen->kernel_mm)
 428             OUT_BATCH(zbpitch);
 429         else
 430             OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 431         END_BATCH();
 432 }
 433
 434 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
 435 {
 436         r300ContextPtr r300 = R300_CONTEXT(ctx);
 437         BATCH_LOCALS(&r300->radeon);
 438         struct radeon_renderbuffer *rrb;
 439         uint32_t format = 0;
 440
 441         rrb = radeon_get_depthbuffer(&r300->radeon);
 442         if (!rrb)
 443           format = 0;
 444         else {
 445           if (rrb->cpp == 2)
 446             format = R300_DEPTHFORMAT_16BIT_INT_Z;
 447           else if (rrb->cpp == 4)
 448             format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
 449         }
 450
 451         BEGIN_BATCH_NO_AUTOSTATE(atom->cmd_size);
 452         OUT_BATCH(atom->cmd[0]);
 453         atom->cmd[1] &= ~0xf;
 454         atom->cmd[1] |= format;
 455         OUT_BATCH(atom->cmd[1]);
 456         OUT_BATCH(atom->cmd[2]);
 457         OUT_BATCH(atom->cmd[3]);
 458         OUT_BATCH(atom->cmd[4]);
 459         END_BATCH();
 460 }
 461
 462 static int check_never(GLcontext *ctx, struct radeon_state_atom *atom)
 463 {
 464    return 0;
 465 }
 466
 467 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 468 {
 469         return atom->cmd_size;
 470 }
 471
 472 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
 473 {
 474         r300ContextPtr r300 = R300_CONTEXT(ctx);
 475         int cnt;
 476         if (atom->cmd[0] == CP_PACKET2) {
 477                 return 0;
 478         }
 479         cnt = packet0_count(r300, atom->cmd);
 480         return cnt ? cnt + 1 : 0;
 481 }
 482
 483 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
 484 {
 485         int cnt;
 486         r300ContextPtr r300 = R300_CONTEXT(ctx);
 487         int extra = 1;
 488         cnt = r500fp_count(atom->cmd);
 489         if (r300->radeon.radeonScreen->kernel_mm)
 490                 extra = 3;
 491
 492         return cnt ? (cnt * 6) + extra : 0;
 493 }
 494
 495 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
 496 {
 497         int cnt;
 498         r300ContextPtr r300 = R300_CONTEXT(ctx);
 499         int extra = 1;
 500         cnt = r500fp_count(atom->cmd);
 501         if (r300->radeon.radeonScreen->kernel_mm)
 502                 extra = 3;
 503
 504         cnt = r500fp_count(atom->cmd);
 505         return cnt ? (cnt * 4) + extra : 0;
 506 }
 507
 508 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )                               \
 509    do {                                                                 \
 510       r300->hw.ATOM.cmd_size = (SZ);                                    \
 511       r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 512       r300->hw.ATOM.name = #ATOM;                                       \
 513       r300->hw.ATOM.idx = (IDX);                                        \
 514       r300->hw.ATOM.check = check_##CHK;                                \
 515       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 516       r300->radeon.hw.max_state_size += (SZ);                                   \
 517       insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM);                \
 518    } while (0)
 519 /**
 520  * Allocate memory for the command buffer and initialize the state atom
 521  * list. Note that the initial hardware state is set by r300InitState().
 522  */
 523 void r300InitCmdBuf(r300ContextPtr r300)
 524 {
 525         int mtu;
 526         int has_tcl;
 527         int is_r500 = 0;
 528
 529         has_tcl = r300->options.hw_tcl_enabled;
 530
 531         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 532                 is_r500 = 1;
 533
 534         r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
 535
 536         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 537         if (RADEON_DEBUG & RADEON_TEXTURE) {
 538                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 539         }
 540
 541         /* Setup the atom linked list */
 542         make_empty_list(&r300->radeon.hw.atomlist);
 543         r300->radeon.hw.atomlist.name = "atom-list";
 544
 545         /* Initialize state atoms */
 546         ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
 547         r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
 548         ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
 549         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 550         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
 551         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
 552         if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
 553             ALLOC_STATE(vap_index_offset, always, 2, 0);
 554             r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
 555             r300->hw.vap_index_offset.cmd[1] = 0;
 556         }
 557         ALLOC_STATE(vte, always, 3, 0);
 558         r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
 559         ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
 560         r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
 561         ALLOC_STATE(vap_cntl_status, always, 2, 0);
 562         r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
 563         ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
 564         r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
 565             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
 566         ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
 567         r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
 568             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 569         ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
 570         r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
 571         ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 572         r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 573
 574         if (has_tcl) {
 575                 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 576                 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
 577                 ALLOC_STATE(vap_clip, always, 5, 0);
 578                 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
 579                 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
 580                 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
 581         }
 582
 583         ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
 584         r300->hw.vof.cmd[R300_VOF_CMD_0] =
 585             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
 586
 587         if (has_tcl) {
 588                 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
 589                 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
 590                     cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
 591         }
 592
 593         ALLOC_STATE(gb_enable, always, 2, 0);
 594         r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
 595         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 596                 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
 597         } else {
 598                 ALLOC_STATE(gb_misc, never, R300_GB_MISC_CMDSIZE, 0);
 599         }
 600         r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
 601         ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
 602         r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
 603         ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
 604         r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
 605         ALLOC_STATE(ga_point_s0, always, 5, 0);
 606         r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
 607         ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
 608         r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
 609         ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
 610         r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
 611         ALLOC_STATE(ga_point_minmax, always, 4, 0);
 612         r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
 613         ALLOC_STATE(lcntl, always, 2, 0);
 614         r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
 615         ALLOC_STATE(ga_line_stipple, always, 4, 0);
 616         r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
 617         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 618                 ALLOC_STATE(shade, always, 2, 0);
 619         } else {
 620                 ALLOC_STATE(shade, never, 2, 0);
 621         }
 622         r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
 623         ALLOC_STATE(shade2, always, 4, 0);
 624         r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
 625         ALLOC_STATE(polygon_mode, always, 4, 0);
 626         r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
 627         ALLOC_STATE(fogp, always, 3, 0);
 628         r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
 629         ALLOC_STATE(zbias_cntl, always, 2, 0);
 630         r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
 631         ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
 632         r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
 633             cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 634         ALLOC_STATE(occlusion_cntl, always, 2, 0);
 635         r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
 636         ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
 637         r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
 638         ALLOC_STATE(su_depth_scale, always, 3, 0);
 639         r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
 640         ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
 641         r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
 642         if (is_r500) {
 643                 ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0);
 644                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
 645                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 646                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
 647         } else {
 648                 ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0);
 649                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
 650                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 651                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
 652         }
 653         ALLOC_STATE(sc_hyperz, always, 3, 0);
 654         r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
 655         ALLOC_STATE(sc_screendoor, always, 2, 0);
 656         r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 657         ALLOC_STATE(us_out_fmt, always, 6, 0);
 658         r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
 659
 660         if (is_r500) {
 661                 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
 662                 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
 663                 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
 664                 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
 665                 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
 666                 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
 667
 668                 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
 669                 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
 670                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
 671                 if (r300->radeon.radeonScreen->kernel_mm)
 672                         r300->hw.r500fp.emit = emit_r500fp;
 673
 674                 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
 675                 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
 676                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
 677                 if (r300->radeon.radeonScreen->kernel_mm)
 678                         r300->hw.r500fp_const.emit = emit_r500fp;
 679         } else {
 680                 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 681                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
 682                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
 683
 684                 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
 685                 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
 686
 687                 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
 688                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
 689                 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
 690                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
 691                 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
 692                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
 693                 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
 694                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
 695                 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
 696                 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
 697         }
 698         ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
 699         r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
 700         ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
 701         r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
 702         ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
 703         r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
 704         ALLOC_STATE(fg_depth_src, always, 2, 0);
 705         r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
 706         ALLOC_STATE(rb3d_cctl, always, 2, 0);
 707         r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
 708         ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
 709         r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
 710         ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
 711         r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
 712         if (is_r500) {
 713                 ALLOC_STATE(blend_color, always, 3, 0);
 714                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
 715         } else {
 716                 ALLOC_STATE(blend_color, always, 2, 0);
 717                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
 718         }
 719         ALLOC_STATE(rop, always, 2, 0);
 720         r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
 721         ALLOC_STATE(cb, cb_offset, R300_CB_CMDSIZE, 0);
 722         r300->hw.cb.emit = &emit_cb_offset_atom;
 723         ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
 724         r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
 725         ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 726         r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
 727         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350) {
 728                 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
 729         } else {
 730                 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);
 731         }
 732         r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
 733         ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
 734         r300->hw.zs.cmd[R300_ZS_CMD_0] =
 735             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
 736         if (is_r500) {
 737                 if (r300->radeon.radeonScreen->kernel_mm)
 738                         ALLOC_STATE(zsb, always, R300_ZSB_CMDSIZE, 0);
 739                 else
 740                         ALLOC_STATE(zsb, never, R300_ZSB_CMDSIZE, 0);
 741                 r300->hw.zsb.cmd[R300_ZSB_CMD_0] =
 742                         cmdpacket0(r300->radeon.radeonScreen, R500_ZB_STENCILREFMASK_BF, 1);
 743         }
 744
 745         ALLOC_STATE(zstencil_format, always, 5, 0);
 746         r300->hw.zstencil_format.cmd[0] =
 747             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
 748         r300->hw.zstencil_format.emit = emit_zstencil_format;
 749
 750         ALLOC_STATE(zb, zb_offset, R300_ZB_CMDSIZE, 0);
 751         r300->hw.zb.emit = emit_zb_offset;
 752         ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
 753         r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
 754         ALLOC_STATE(zb_zmask, always, 3, 0);
 755         r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
 756         ALLOC_STATE(zb_hiz_offset, always, 2, 0);
 757         r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
 758         ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
 759         r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
 760
 761         /* VPU only on TCL */
 762         if (has_tcl) {
 763                 int i;
 764                 if (r300->radeon.radeonScreen->kernel_mm) {
 765                         ALLOC_STATE(vap_flush, always, 10, 0);
 766                         /* flush processing vertices */
 767                         r300->hw.vap_flush.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 768                         r300->hw.vap_flush.cmd[1] = 0;
 769                         r300->hw.vap_flush.cmd[2] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DSTCACHE_CTLSTAT, 1);
 770                         r300->hw.vap_flush.cmd[3] = R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D;
 771                         r300->hw.vap_flush.cmd[4] = cmdpacket0(r300->radeon.radeonScreen, RADEON_WAIT_UNTIL, 1);
 772                         r300->hw.vap_flush.cmd[5] = RADEON_WAIT_3D_IDLECLEAN;
 773                         r300->hw.vap_flush.cmd[6] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 774                         r300->hw.vap_flush.cmd[7] = 0xffffff;
 775                         r300->hw.vap_flush.cmd[8] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 776                         r300->hw.vap_flush.cmd[9] = 0;
 777                 } else {
 778                         ALLOC_STATE(vap_flush, never, 10, 0);
 779                 }
 780
 781
 782                 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 783                 r300->hw.vpi.cmd[0] =
 784                         cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
 785                 if (r300->radeon.radeonScreen->kernel_mm)
 786                         r300->hw.vpi.emit = emit_vpu;
 787
 788                 if (is_r500) {
 789                         ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 790                         r300->hw.vpp.cmd[0] =
 791                                 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
 792                         if (r300->radeon.radeonScreen->kernel_mm)
 793                                 r300->hw.vpp.emit = emit_vpu;
 794
 795                         ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 796                         r300->hw.vps.cmd[0] =
 797                                 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
 798                         if (r300->radeon.radeonScreen->kernel_mm)
 799                                 r300->hw.vps.emit = emit_vpu;
 800
 801                         for (i = 0; i < 6; i++) {
 802                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 803                                 r300->hw.vpucp[i].cmd[0] =
 804                                         cmdvpu(r300->radeon.radeonScreen,
 805                                                         R500_PVS_UCP_START + i, 1);
 806                                 if (r300->radeon.radeonScreen->kernel_mm)
 807                                         r300->hw.vpucp[i].emit = emit_vpu;
 808                         }
 809                 } else {
 810                         ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 811                         r300->hw.vpp.cmd[0] =
 812                                 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
 813                         if (r300->radeon.radeonScreen->kernel_mm)
 814                                 r300->hw.vpp.emit = emit_vpu;
 815
 816                         ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 817                         r300->hw.vps.cmd[0] =
 818                                 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
 819                         if (r300->radeon.radeonScreen->kernel_mm)
 820                                 r300->hw.vps.emit = emit_vpu;
 821
 822                         for (i = 0; i < 6; i++) {
 823                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 824                                 r300->hw.vpucp[i].cmd[0] =
 825                                         cmdvpu(r300->radeon.radeonScreen,
 826                                                         R300_PVS_UCP_START + i, 1);
 827                                 if (r300->radeon.radeonScreen->kernel_mm)
 828                                         r300->hw.vpucp[i].emit = emit_vpu;
 829                         }
 830                 }
 831         }
 832
 833         /* Textures */
 834         ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
 835         r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
 836             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
 837
 838         ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
 839         r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
 840             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
 841
 842         ALLOC_STATE(tex.size, variable, mtu + 1, 0);
 843         r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
 844
 845         ALLOC_STATE(tex.format, variable, mtu + 1, 0);
 846         r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
 847             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
 848
 849         ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
 850         r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
 851
 852         ALLOC_STATE(tex.offset, tex_offsets, 1, 0);
 853         r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
 854             cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
 855         r300->hw.tex.offset.emit = &emit_tex_offsets;
 856
 857         ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
 858         r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
 859             cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
 860
 861         ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
 862         r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
 863             cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
 864
 865         radeon_init_query_stateobj(&r300->radeon, R300_QUERYOBJ_CMDSIZE);
 866         if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 867                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RV530_FG_ZBREG_DEST, 1);
 868                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL;
 869         } else {
 870                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_REG_DEST, 1);
 871                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = R300_RASTER_PIPE_SELECT_ALL;
 872         }
 873         r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZPASS_DATA, 1);
 874         r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_1] = 0;
 875
 876         r300->radeon.hw.is_dirty = GL_TRUE;
 877         r300->radeon.hw.all_dirty = GL_TRUE;
 878
 879         rcommonInitCmdBuf(&r300->radeon);
 880 }