2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Nicolai Haehnle <prefect_@gmx.net>
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
44 #include "radeon_drm.h"
46 #include "r300_context.h"
48 #include "r300_cmdbuf.h"
49 #include "r300_emit.h"
50 #include "radeon_bocs_wrapper.h"
51 #include "radeon_mipmap_tree.h"
52 #include "radeon_queryobj.h"
54 /** # of dwords reserved for additional instructions that may need to be written
57 #define SPACE_FOR_FLUSHING 4
59 static unsigned packet0_count(r300ContextPtr r300
, uint32_t *pkt
)
61 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
62 return ((((*pkt
) >> 16) & 0x3FFF) + 1);
64 drm_r300_cmd_header_t
*t
= (drm_r300_cmd_header_t
*)pkt
;
65 return t
->packet0
.count
;
69 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
70 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
72 static int check_vpu(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
74 r300ContextPtr r300
= R300_CONTEXT(ctx
);
77 cnt
= vpu_count(atom
->cmd
);
79 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
83 return cnt
? (cnt
* 4) + extra
: 0;
86 void r300_emit_vpu(struct r300_context
*r300
,
91 BATCH_LOCALS(&r300
->radeon
);
93 BEGIN_BATCH_NO_AUTOSTATE(3 + len
);
94 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG
, addr
);
95 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA
, len
-1) | RADEON_ONE_REG_WR
);
96 OUT_BATCH_TABLE(data
, len
);
100 static void emit_vpu_state(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
102 r300ContextPtr r300
= R300_CONTEXT(ctx
);
103 drm_r300_cmd_header_t cmd
;
106 cmd
.u
= atom
->cmd
[0];
107 addr
= (cmd
.vpu
.adrhi
<< 8) | cmd
.vpu
.adrlo
;
108 ndw
= atom
->check(ctx
, atom
);
110 r300_emit_vpu(r300
, &atom
->cmd
[1], vpu_count(atom
->cmd
) * 4, addr
);
113 void r500_emit_fp(struct r300_context
*r300
,
120 BATCH_LOCALS(&r300
->radeon
);
122 addr
|= (type
<< 16);
123 addr
|= (clamp
<< 17);
125 BEGIN_BATCH_NO_AUTOSTATE(len
+ 3);
126 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX
, 0));
128 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA
, len
-1) | RADEON_ONE_REG_WR
);
129 OUT_BATCH_TABLE(data
, len
);
133 static void emit_r500fp_atom(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
135 r300ContextPtr r300
= R300_CONTEXT(ctx
);
136 drm_r300_cmd_header_t cmd
;
137 uint32_t addr
, count
;
140 cmd
.u
= atom
->cmd
[0];
141 addr
= ((cmd
.r500fp
.adrhi_flags
& 1) << 8) | cmd
.r500fp
.adrlo
;
142 type
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_TYPE
);
143 clamp
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_CLAMP
);
146 count
= r500fp_count(atom
->cmd
) * 4;
148 count
= r500fp_count(atom
->cmd
) * 6;
151 r500_emit_fp(r300
, &atom
->cmd
[1], count
, addr
, type
, clamp
);
154 static int check_tex_offsets(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
156 r300ContextPtr r300
= R300_CONTEXT(ctx
);
157 int numtmus
= packet0_count(r300
, r300
->hw
.tex
.offset
.cmd
);
159 if (atom
->cmd
[0] == CP_PACKET2
) {
162 for(i
= 0; i
< numtmus
; ++i
) {
163 radeonTexObj
*t
= r300
->hw
.textures
[i
];
164 if (!t
&& !r300
->radeon
.radeonScreen
->kernel_mm
) {
166 } else if (t
&& t
->image_override
&& !t
->bo
) {
167 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
175 static void emit_tex_offsets(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
177 r300ContextPtr r300
= R300_CONTEXT(ctx
);
178 BATCH_LOCALS(&r300
->radeon
);
179 int numtmus
= packet0_count(r300
, r300
->hw
.tex
.offset
.cmd
);
182 for(i
= 0; i
< numtmus
; ++i
) {
183 radeonTexObj
*t
= r300
->hw
.textures
[i
];
184 if (t
&& !t
->image_override
) {
185 BEGIN_BATCH_NO_AUTOSTATE(4);
186 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
187 OUT_BATCH_RELOC(t
->tile_bits
, t
->mt
->bo
, get_base_teximage_offset(t
),
188 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
191 /* Texture unit hasn't a texture bound.
192 * We assign the current color buffer as a fakery to make
193 * KIL work on KMS (without it, the CS checker will complain).
195 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
196 struct radeon_renderbuffer
*rrb
= radeon_get_colorbuffer(&r300
->radeon
);
197 if (rrb
&& rrb
->bo
) {
198 BEGIN_BATCH_NO_AUTOSTATE(4);
199 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
200 OUT_BATCH_RELOC(0, rrb
->bo
, 0,
201 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
205 } else { /* override cases */
207 BEGIN_BATCH_NO_AUTOSTATE(4);
208 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
209 OUT_BATCH_RELOC(t
->tile_bits
, t
->bo
, 0,
210 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
212 } else if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
213 BEGIN_BATCH_NO_AUTOSTATE(2);
214 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
215 OUT_BATCH(t
->override_offset
);
218 /* Texture unit hasn't a texture bound nothings to do */
224 void r300_emit_scissor(GLcontext
*ctx
)
226 r300ContextPtr r300
= R300_CONTEXT(ctx
);
227 BATCH_LOCALS(&r300
->radeon
);
228 unsigned x1
, y1
, x2
, y2
;
229 struct radeon_renderbuffer
*rrb
;
231 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
234 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
235 if (!rrb
|| !rrb
->bo
) {
236 fprintf(stderr
, "no rrb\n");
239 if (r300
->radeon
.state
.scissor
.enabled
) {
240 x1
= r300
->radeon
.state
.scissor
.rect
.x1
;
241 y1
= r300
->radeon
.state
.scissor
.rect
.y1
;
242 x2
= r300
->radeon
.state
.scissor
.rect
.x2
;
243 y2
= r300
->radeon
.state
.scissor
.rect
.y2
;
247 x2
= rrb
->base
.Width
- 1;
248 y2
= rrb
->base
.Height
- 1;
250 if (r300
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV515
) {
251 x1
+= R300_SCISSORS_OFFSET
;
252 y1
+= R300_SCISSORS_OFFSET
;
253 x2
+= R300_SCISSORS_OFFSET
;
254 y2
+= R300_SCISSORS_OFFSET
;
256 BEGIN_BATCH_NO_AUTOSTATE(3);
257 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
258 OUT_BATCH((x1
<< R300_SCISSORS_X_SHIFT
)|(y1
<< R300_SCISSORS_Y_SHIFT
));
259 OUT_BATCH((x2
<< R300_SCISSORS_X_SHIFT
)|(y2
<< R300_SCISSORS_Y_SHIFT
));
262 static int check_cb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
264 r300ContextPtr r300
= R300_CONTEXT(ctx
);
265 uint32_t dw
= 6 + 3 + 16;
266 if (r300
->radeon
.radeonScreen
->kernel_mm
)
268 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
274 static void emit_scissor(struct r300_context
*r300
,
279 BATCH_LOCALS(&r300
->radeon
);
280 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
) {
281 BEGIN_BATCH_NO_AUTOSTATE(3);
282 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
284 OUT_BATCH(((width
- 1) << R300_SCISSORS_X_SHIFT
) |
285 ((height
- 1) << R300_SCISSORS_Y_SHIFT
));
287 BEGIN_BATCH_NO_AUTOSTATE(16);
288 for (i
= 0; i
< 4; i
++) {
289 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0
+ (i
* 8), 2);
290 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT
) | (0 << R300_CLIPRECT_Y_SHIFT
));
291 OUT_BATCH(((width
- 1) << R300_CLIPRECT_X_SHIFT
) | ((height
- 1) << R300_CLIPRECT_Y_SHIFT
));
293 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE
, 1);
295 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR
, 1);
299 BEGIN_BATCH_NO_AUTOSTATE(3);
300 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
301 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_SCISSORS_X_SHIFT
) |
302 (R300_SCISSORS_OFFSET
<< R300_SCISSORS_Y_SHIFT
));
303 OUT_BATCH(((width
+ R300_SCISSORS_OFFSET
- 1) << R300_SCISSORS_X_SHIFT
) |
304 ((height
+ R300_SCISSORS_OFFSET
- 1) << R300_SCISSORS_Y_SHIFT
));
306 BEGIN_BATCH_NO_AUTOSTATE(16);
307 for (i
= 0; i
< 4; i
++) {
308 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0
+ (i
* 8), 2);
309 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_CLIPRECT_X_SHIFT
) | (R300_SCISSORS_OFFSET
<< R300_CLIPRECT_Y_SHIFT
));
310 OUT_BATCH(((R300_SCISSORS_OFFSET
+ width
- 1) << R300_CLIPRECT_X_SHIFT
) |
311 ((R300_SCISSORS_OFFSET
+ height
- 1) << R300_CLIPRECT_Y_SHIFT
));
313 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE
, 1);
315 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR
, 1);
321 void r300_emit_cb_setup(struct r300_context
*r300
,
322 struct radeon_bo
*bo
,
328 BATCH_LOCALS(&r300
->radeon
);
329 uint32_t cbpitch
= pitch
/ cpp
;
332 assert(offset
% 32 == 0);
335 case MESA_FORMAT_RGB565
:
336 assert(_mesa_little_endian());
337 cbpitch
|= R300_COLOR_FORMAT_RGB565
;
339 case MESA_FORMAT_RGB565_REV
:
340 assert(!_mesa_little_endian());
341 cbpitch
|= R300_COLOR_FORMAT_RGB565
;
343 case MESA_FORMAT_ARGB4444
:
344 assert(_mesa_little_endian());
345 cbpitch
|= R300_COLOR_FORMAT_ARGB4444
;
347 case MESA_FORMAT_ARGB4444_REV
:
348 assert(!_mesa_little_endian());
349 cbpitch
|= R300_COLOR_FORMAT_ARGB4444
;
351 case MESA_FORMAT_ARGB1555
:
352 assert(_mesa_little_endian());
353 cbpitch
|= R300_COLOR_FORMAT_ARGB1555
;
355 case MESA_FORMAT_ARGB1555_REV
:
356 assert(!_mesa_little_endian());
357 cbpitch
|= R300_COLOR_FORMAT_ARGB1555
;
361 cbpitch
|= R300_COLOR_FORMAT_ARGB8888
;
363 _mesa_problem(r300
->radeon
.glCtx
, "unexpected format in emit_cb_offset()");;
368 if (bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
369 cbpitch
|= R300_COLOR_TILE_ENABLE
;
371 if (r300
->radeon
.radeonScreen
->kernel_mm
)
374 BEGIN_BATCH_NO_AUTOSTATE(dw
);
375 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0
, 1);
376 OUT_BATCH_RELOC(offset
, bo
, offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
377 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0
, 1);
378 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
381 OUT_BATCH_RELOC(cbpitch
, bo
, cbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
385 static void emit_cb_offset_atom(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
387 r300ContextPtr r300
= R300_CONTEXT(ctx
);
388 struct radeon_renderbuffer
*rrb
;
389 uint32_t offset
= r300
->radeon
.state
.color
.draw_offset
;
391 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
392 if (!rrb
|| !rrb
->bo
) {
393 fprintf(stderr
, "no rrb\n");
397 if (RADEON_DEBUG
& RADEON_STATE
)
398 fprintf(stderr
,"rrb is %p %d %dx%d\n", rrb
, offset
, rrb
->base
.Width
, rrb
->base
.Height
);
400 r300_emit_cb_setup(r300
, rrb
->bo
, offset
, rrb
->base
.Format
, rrb
->cpp
, rrb
->pitch
);
402 if (r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
403 emit_scissor(r300
, rrb
->base
.Width
, rrb
->base
.Height
);
407 static int check_zb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
409 r300ContextPtr r300
= R300_CONTEXT(ctx
);
412 if (r300
->radeon
.radeonScreen
->kernel_mm
)
417 static void emit_zb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
419 r300ContextPtr r300
= R300_CONTEXT(ctx
);
420 BATCH_LOCALS(&r300
->radeon
);
421 struct radeon_renderbuffer
*rrb
;
423 uint32_t dw
= atom
->check(ctx
, atom
);
425 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
429 zbpitch
= (rrb
->pitch
/ rrb
->cpp
);
430 if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
431 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
432 zbpitch
|= R300_DEPTHMACROTILE_ENABLE
;
434 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
){
435 zbpitch
|= R300_DEPTHMICROTILE_TILED
;
439 BEGIN_BATCH_NO_AUTOSTATE(dw
);
440 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET
, 1);
441 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
442 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH
, 1);
443 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
446 OUT_BATCH_RELOC(cbpitch
, rrb
->bo
, zbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
450 static void emit_zstencil_format(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
452 r300ContextPtr r300
= R300_CONTEXT(ctx
);
453 BATCH_LOCALS(&r300
->radeon
);
454 struct radeon_renderbuffer
*rrb
;
457 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
462 format
= R300_DEPTHFORMAT_16BIT_INT_Z
;
463 else if (rrb
->cpp
== 4)
464 format
= R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL
;
467 BEGIN_BATCH_NO_AUTOSTATE(atom
->cmd_size
);
468 OUT_BATCH(atom
->cmd
[0]);
469 atom
->cmd
[1] &= ~0xf;
470 atom
->cmd
[1] |= format
;
471 OUT_BATCH(atom
->cmd
[1]);
472 OUT_BATCH(atom
->cmd
[2]);
473 OUT_BATCH(atom
->cmd
[3]);
474 OUT_BATCH(atom
->cmd
[4]);
478 static int check_never(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
483 static int check_always(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
485 return atom
->cmd_size
;
488 static int check_variable(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
490 r300ContextPtr r300
= R300_CONTEXT(ctx
);
492 if (atom
->cmd
[0] == CP_PACKET2
) {
495 cnt
= packet0_count(r300
, atom
->cmd
);
496 return cnt
? cnt
+ 1 : 0;
499 static int check_r500fp(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
502 r300ContextPtr r300
= R300_CONTEXT(ctx
);
504 cnt
= r500fp_count(atom
->cmd
);
505 if (r300
->radeon
.radeonScreen
->kernel_mm
)
508 return cnt
? (cnt
* 6) + extra
: 0;
511 static int check_r500fp_const(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
514 r300ContextPtr r300
= R300_CONTEXT(ctx
);
516 cnt
= r500fp_count(atom
->cmd
);
517 if (r300
->radeon
.radeonScreen
->kernel_mm
)
520 cnt
= r500fp_count(atom
->cmd
);
521 return cnt
? (cnt
* 4) + extra
: 0;
524 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
526 r300->hw.ATOM.cmd_size = (SZ); \
527 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
528 r300->hw.ATOM.name = #ATOM; \
529 r300->hw.ATOM.idx = (IDX); \
530 r300->hw.ATOM.check = check_##CHK; \
531 r300->hw.ATOM.dirty = GL_FALSE; \
532 r300->radeon.hw.max_state_size += (SZ); \
533 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
536 * Allocate memory for the command buffer and initialize the state atom
537 * list. Note that the initial hardware state is set by r300InitState().
539 void r300InitCmdBuf(r300ContextPtr r300
)
545 has_tcl
= r300
->options
.hw_tcl_enabled
;
547 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
550 r300
->radeon
.hw
.max_state_size
= 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
552 mtu
= r300
->radeon
.glCtx
->Const
.MaxTextureUnits
;
553 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
554 fprintf(stderr
, "Using %d maximum texture units..\n", mtu
);
557 /* Setup the atom linked list */
558 make_empty_list(&r300
->radeon
.hw
.atomlist
);
559 r300
->radeon
.hw
.atomlist
.name
= "atom-list";
561 /* Initialize state atoms */
562 ALLOC_STATE(vpt
, always
, R300_VPT_CMDSIZE
, 0);
563 r300
->hw
.vpt
.cmd
[R300_VPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VPORT_XSCALE
, 6);
564 ALLOC_STATE(vap_cntl
, always
, R300_VAP_CNTL_SIZE
, 0);
565 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_STATE_FLUSH_REG
, 1);
566 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH_1
] = 0;
567 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_CMD
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL
, 1);
568 if (is_r500
&& !r300
->radeon
.radeonScreen
->kernel_mm
) {
569 ALLOC_STATE(vap_index_offset
, always
, 2, 0);
570 r300
->hw
.vap_index_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_VAP_INDEX_OFFSET
, 1);
571 r300
->hw
.vap_index_offset
.cmd
[1] = 0;
573 ALLOC_STATE(vte
, always
, 3, 0);
574 r300
->hw
.vte
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VTE_CNTL
, 2);
575 ALLOC_STATE(vap_vf_max_vtx_indx
, always
, 3, 0);
576 r300
->hw
.vap_vf_max_vtx_indx
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VF_MAX_VTX_INDX
, 2);
577 ALLOC_STATE(vap_cntl_status
, always
, 2, 0);
578 r300
->hw
.vap_cntl_status
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL_STATUS
, 1);
579 ALLOC_STATE(vir
[0], variable
, R300_VIR_CMDSIZE
, 0);
580 r300
->hw
.vir
[0].cmd
[R300_VIR_CMD_0
] =
581 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_0
, 1);
582 ALLOC_STATE(vir
[1], variable
, R300_VIR_CMDSIZE
, 1);
583 r300
->hw
.vir
[1].cmd
[R300_VIR_CMD_0
] =
584 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_EXT_0
, 1);
585 ALLOC_STATE(vic
, always
, R300_VIC_CMDSIZE
, 0);
586 r300
->hw
.vic
.cmd
[R300_VIC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VTX_STATE_CNTL
, 2);
587 ALLOC_STATE(vap_psc_sgn_norm_cntl
, always
, 2, 0);
588 r300
->hw
.vap_psc_sgn_norm_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PSC_SGN_NORM_CNTL
, SGN_NORM_ZERO_CLAMP_MINUS_ONE
);
591 ALLOC_STATE(vap_clip_cntl
, always
, 2, 0);
592 r300
->hw
.vap_clip_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CLIP_CNTL
, 1);
593 ALLOC_STATE(vap_clip
, always
, 5, 0);
594 r300
->hw
.vap_clip
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_GB_VERT_CLIP_ADJ
, 4);
595 ALLOC_STATE(vap_pvs_vtx_timeout_reg
, always
, 2, 0);
596 r300
->hw
.vap_pvs_vtx_timeout_reg
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, VAP_PVS_VTX_TIMEOUT_REG
, 1);
599 ALLOC_STATE(vof
, always
, R300_VOF_CMDSIZE
, 0);
600 r300
->hw
.vof
.cmd
[R300_VOF_CMD_0
] =
601 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_OUTPUT_VTX_FMT_0
, 2);
604 ALLOC_STATE(pvs
, always
, R300_PVS_CMDSIZE
, 0);
605 r300
->hw
.pvs
.cmd
[R300_PVS_CMD_0
] =
606 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_CODE_CNTL_0
, 3);
609 ALLOC_STATE(gb_enable
, always
, 2, 0);
610 r300
->hw
.gb_enable
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_ENABLE
, 1);
611 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
612 ALLOC_STATE(gb_misc
, always
, R300_GB_MISC_CMDSIZE
, 0);
614 ALLOC_STATE(gb_misc
, never
, R300_GB_MISC_CMDSIZE
, 0);
616 r300
->hw
.gb_misc
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_MSPOS0
, 3);
617 ALLOC_STATE(gb_misc2
, always
, R300_GB_MISC2_CMDSIZE
, 0);
618 r300
->hw
.gb_misc2
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x401C, 2);
619 ALLOC_STATE(txe
, always
, R300_TXE_CMDSIZE
, 0);
620 r300
->hw
.txe
.cmd
[R300_TXE_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_ENABLE
, 1);
621 ALLOC_STATE(ga_point_s0
, always
, 5, 0);
622 r300
->hw
.ga_point_s0
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_S0
, 4);
623 ALLOC_STATE(ga_triangle_stipple
, always
, 2, 0);
624 r300
->hw
.ga_triangle_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_TRIANGLE_STIPPLE
, 1);
625 ALLOC_STATE(ps
, always
, R300_PS_CMDSIZE
, 0);
626 r300
->hw
.ps
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_SIZE
, 1);
627 ALLOC_STATE(ga_point_minmax
, always
, 4, 0);
628 r300
->hw
.ga_point_minmax
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_MINMAX
, 3);
629 ALLOC_STATE(lcntl
, always
, 2, 0);
630 r300
->hw
.lcntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_CNTL
, 1);
631 ALLOC_STATE(ga_line_stipple
, always
, 4, 0);
632 r300
->hw
.ga_line_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_STIPPLE_VALUE
, 3);
633 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
634 ALLOC_STATE(shade
, always
, 2, 0);
636 ALLOC_STATE(shade
, never
, 2, 0);
638 r300
->hw
.shade
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_ENHANCE
, 1);
639 ALLOC_STATE(shade2
, always
, 4, 0);
640 r300
->hw
.shade2
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x4278, 3);
641 ALLOC_STATE(polygon_mode
, always
, 4, 0);
642 r300
->hw
.polygon_mode
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POLY_MODE
, 3);
643 ALLOC_STATE(fogp
, always
, 3, 0);
644 r300
->hw
.fogp
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_FOG_SCALE
, 2);
645 ALLOC_STATE(zbias_cntl
, always
, 2, 0);
646 r300
->hw
.zbias_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_TEX_WRAP
, 1);
647 ALLOC_STATE(zbs
, always
, R300_ZBS_CMDSIZE
, 0);
648 r300
->hw
.zbs
.cmd
[R300_ZBS_CMD_0
] =
649 cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
650 ALLOC_STATE(occlusion_cntl
, always
, 2, 0);
651 r300
->hw
.occlusion_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_ENABLE
, 1);
652 ALLOC_STATE(cul
, always
, R300_CUL_CMDSIZE
, 0);
653 r300
->hw
.cul
.cmd
[R300_CUL_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_CULL_MODE
, 1);
654 ALLOC_STATE(su_depth_scale
, always
, 3, 0);
655 r300
->hw
.su_depth_scale
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_DEPTH_SCALE
, 2);
656 ALLOC_STATE(rc
, always
, R300_RC_CMDSIZE
, 0);
657 r300
->hw
.rc
.cmd
[R300_RC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_COUNT
, 2);
659 ALLOC_STATE(ri
, variable
, R500_RI_CMDSIZE
, 0);
660 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_IP_0
, 16);
661 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
662 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_INST_0
, 1);
664 ALLOC_STATE(ri
, variable
, R300_RI_CMDSIZE
, 0);
665 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_IP_0
, 8);
666 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
667 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_INST_0
, 1);
669 ALLOC_STATE(sc_hyperz
, always
, 3, 0);
670 r300
->hw
.sc_hyperz
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_HYPERZ
, 2);
671 ALLOC_STATE(sc_screendoor
, always
, 2, 0);
672 r300
->hw
.sc_screendoor
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
673 ALLOC_STATE(us_out_fmt
, always
, 6, 0);
674 r300
->hw
.us_out_fmt
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_OUT_FMT
, 5);
677 ALLOC_STATE(fp
, always
, R500_FP_CMDSIZE
, 0);
678 r300
->hw
.fp
.cmd
[R500_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CONFIG
, 2);
679 r300
->hw
.fp
.cmd
[R500_FP_CNTL
] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
;
680 r300
->hw
.fp
.cmd
[R500_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CODE_ADDR
, 3);
681 r300
->hw
.fp
.cmd
[R500_FP_CMD_2
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_FC_CTRL
, 1);
682 r300
->hw
.fp
.cmd
[R500_FP_FC_CNTL
] = 0; /* FIXME when we add flow control */
684 ALLOC_STATE(r500fp
, r500fp
, R500_FPI_CMDSIZE
, 0);
685 r300
->hw
.r500fp
.cmd
[R300_FPI_CMD_0
] =
686 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 0, 0);
687 if (r300
->radeon
.radeonScreen
->kernel_mm
)
688 r300
->hw
.r500fp
.emit
= emit_r500fp_atom
;
690 ALLOC_STATE(r500fp_const
, r500fp_const
, R500_FPP_CMDSIZE
, 0);
691 r300
->hw
.r500fp_const
.cmd
[R300_FPI_CMD_0
] =
692 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 1, 0);
693 if (r300
->radeon
.radeonScreen
->kernel_mm
)
694 r300
->hw
.r500fp_const
.emit
= emit_r500fp_atom
;
696 ALLOC_STATE(fp
, always
, R300_FP_CMDSIZE
, 0);
697 r300
->hw
.fp
.cmd
[R300_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CONFIG
, 3);
698 r300
->hw
.fp
.cmd
[R300_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CODE_ADDR_0
, 4);
700 ALLOC_STATE(fpt
, variable
, R300_FPT_CMDSIZE
, 0);
701 r300
->hw
.fpt
.cmd
[R300_FPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_TEX_INST_0
, 0);
703 ALLOC_STATE(fpi
[0], variable
, R300_FPI_CMDSIZE
, 0);
704 r300
->hw
.fpi
[0].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_INST_0
, 1);
705 ALLOC_STATE(fpi
[1], variable
, R300_FPI_CMDSIZE
, 1);
706 r300
->hw
.fpi
[1].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_ADDR_0
, 1);
707 ALLOC_STATE(fpi
[2], variable
, R300_FPI_CMDSIZE
, 2);
708 r300
->hw
.fpi
[2].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_INST_0
, 1);
709 ALLOC_STATE(fpi
[3], variable
, R300_FPI_CMDSIZE
, 3);
710 r300
->hw
.fpi
[3].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_ADDR_0
, 1);
711 ALLOC_STATE(fpp
, variable
, R300_FPP_CMDSIZE
, 0);
712 r300
->hw
.fpp
.cmd
[R300_FPP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_PFS_PARAM_0_X
, 0);
714 ALLOC_STATE(fogs
, always
, R300_FOGS_CMDSIZE
, 0);
715 r300
->hw
.fogs
.cmd
[R300_FOGS_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_BLEND
, 1);
716 ALLOC_STATE(fogc
, always
, R300_FOGC_CMDSIZE
, 0);
717 r300
->hw
.fogc
.cmd
[R300_FOGC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_COLOR_R
, 3);
718 ALLOC_STATE(at
, always
, R300_AT_CMDSIZE
, 0);
719 r300
->hw
.at
.cmd
[R300_AT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_ALPHA_FUNC
, 2);
720 ALLOC_STATE(fg_depth_src
, always
, 2, 0);
721 r300
->hw
.fg_depth_src
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_DEPTH_SRC
, 1);
722 ALLOC_STATE(rb3d_cctl
, always
, 2, 0);
723 r300
->hw
.rb3d_cctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CCTL
, 1);
724 ALLOC_STATE(bld
, always
, R300_BLD_CMDSIZE
, 0);
725 r300
->hw
.bld
.cmd
[R300_BLD_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CBLEND
, 2);
726 ALLOC_STATE(cmk
, always
, R300_CMK_CMDSIZE
, 0);
727 r300
->hw
.cmk
.cmd
[R300_CMK_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, RB3D_COLOR_CHANNEL_MASK
, 1);
729 ALLOC_STATE(blend_color
, always
, 3, 0);
730 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_CONSTANT_COLOR_AR
, 2);
732 ALLOC_STATE(blend_color
, always
, 2, 0);
733 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_BLEND_COLOR
, 1);
735 ALLOC_STATE(rop
, always
, 2, 0);
736 r300
->hw
.rop
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_ROPCNTL
, 1);
737 ALLOC_STATE(cb
, cb_offset
, R300_CB_CMDSIZE
, 0);
738 r300
->hw
.cb
.emit
= &emit_cb_offset_atom
;
739 ALLOC_STATE(rb3d_dither_ctl
, always
, 10, 0);
740 r300
->hw
.rb3d_dither_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_DITHER_CTL
, 9);
741 ALLOC_STATE(rb3d_aaresolve_ctl
, always
, 2, 0);
742 r300
->hw
.rb3d_aaresolve_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_AARESOLVE_CTL
, 1);
743 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV350
) {
744 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold
, always
, 3, 0);
746 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold
, never
, 3, 0);
748 r300
->hw
.rb3d_discard_src_pixel_lte_threshold
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
, 2);
749 ALLOC_STATE(zs
, always
, R300_ZS_CMDSIZE
, 0);
750 r300
->hw
.zs
.cmd
[R300_ZS_CMD_0
] =
751 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_CNTL
, 3);
753 if (r300
->radeon
.radeonScreen
->kernel_mm
)
754 ALLOC_STATE(zsb
, always
, R300_ZSB_CMDSIZE
, 0);
756 ALLOC_STATE(zsb
, never
, R300_ZSB_CMDSIZE
, 0);
757 r300
->hw
.zsb
.cmd
[R300_ZSB_CMD_0
] =
758 cmdpacket0(r300
->radeon
.radeonScreen
, R500_ZB_STENCILREFMASK_BF
, 1);
761 ALLOC_STATE(zstencil_format
, always
, 5, 0);
762 r300
->hw
.zstencil_format
.cmd
[0] =
763 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_FORMAT
, 4);
764 r300
->hw
.zstencil_format
.emit
= emit_zstencil_format
;
766 ALLOC_STATE(zb
, zb_offset
, R300_ZB_CMDSIZE
, 0);
767 r300
->hw
.zb
.emit
= emit_zb_offset
;
768 ALLOC_STATE(zb_depthclearvalue
, always
, 2, 0);
769 r300
->hw
.zb_depthclearvalue
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_DEPTHCLEARVALUE
, 1);
770 ALLOC_STATE(zb_zmask
, always
, 3, 0);
771 r300
->hw
.zb_zmask
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_ZMASK_OFFSET
, 2);
772 ALLOC_STATE(zb_hiz_offset
, always
, 2, 0);
773 r300
->hw
.zb_hiz_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_OFFSET
, 1);
774 ALLOC_STATE(zb_hiz_pitch
, always
, 2, 0);
775 r300
->hw
.zb_hiz_pitch
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_PITCH
, 1);
777 /* VPU only on TCL */
780 ALLOC_STATE(vpi
, vpu
, R300_VPI_CMDSIZE
, 0);
781 r300
->hw
.vpi
.cmd
[0] =
782 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CODE_START
, 0);
783 if (r300
->radeon
.radeonScreen
->kernel_mm
)
784 r300
->hw
.vpi
.emit
= emit_vpu_state
;
787 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
788 r300
->hw
.vpp
.cmd
[0] =
789 cmdvpu(r300
->radeon
.radeonScreen
, R500_PVS_CONST_START
, 0);
790 if (r300
->radeon
.radeonScreen
->kernel_mm
)
791 r300
->hw
.vpp
.emit
= emit_vpu_state
;
793 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
794 r300
->hw
.vps
.cmd
[0] =
795 cmdvpu(r300
->radeon
.radeonScreen
, R500_POINT_VPORT_SCALE_OFFSET
, 1);
796 if (r300
->radeon
.radeonScreen
->kernel_mm
)
797 r300
->hw
.vps
.emit
= emit_vpu_state
;
799 for (i
= 0; i
< 6; i
++) {
800 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
801 r300
->hw
.vpucp
[i
].cmd
[0] =
802 cmdvpu(r300
->radeon
.radeonScreen
,
803 R500_PVS_UCP_START
+ i
, 1);
804 if (r300
->radeon
.radeonScreen
->kernel_mm
)
805 r300
->hw
.vpucp
[i
].emit
= emit_vpu_state
;
808 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
809 r300
->hw
.vpp
.cmd
[0] =
810 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CONST_START
, 0);
811 if (r300
->radeon
.radeonScreen
->kernel_mm
)
812 r300
->hw
.vpp
.emit
= emit_vpu_state
;
814 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
815 r300
->hw
.vps
.cmd
[0] =
816 cmdvpu(r300
->radeon
.radeonScreen
, R300_POINT_VPORT_SCALE_OFFSET
, 1);
817 if (r300
->radeon
.radeonScreen
->kernel_mm
)
818 r300
->hw
.vps
.emit
= emit_vpu_state
;
820 for (i
= 0; i
< 6; i
++) {
821 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
822 r300
->hw
.vpucp
[i
].cmd
[0] =
823 cmdvpu(r300
->radeon
.radeonScreen
,
824 R300_PVS_UCP_START
+ i
, 1);
825 if (r300
->radeon
.radeonScreen
->kernel_mm
)
826 r300
->hw
.vpucp
[i
].emit
= emit_vpu_state
;
832 ALLOC_STATE(tex
.filter
, variable
, mtu
+ 1, 0);
833 r300
->hw
.tex
.filter
.cmd
[R300_TEX_CMD_0
] =
834 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER0_0
, 0);
836 ALLOC_STATE(tex
.filter_1
, variable
, mtu
+ 1, 0);
837 r300
->hw
.tex
.filter_1
.cmd
[R300_TEX_CMD_0
] =
838 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER1_0
, 0);
840 ALLOC_STATE(tex
.size
, variable
, mtu
+ 1, 0);
841 r300
->hw
.tex
.size
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_SIZE_0
, 0);
843 ALLOC_STATE(tex
.format
, variable
, mtu
+ 1, 0);
844 r300
->hw
.tex
.format
.cmd
[R300_TEX_CMD_0
] =
845 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT_0
, 0);
847 ALLOC_STATE(tex
.pitch
, variable
, mtu
+ 1, 0);
848 r300
->hw
.tex
.pitch
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT2_0
, 0);
850 ALLOC_STATE(tex
.offset
, tex_offsets
, 1, 0);
851 r300
->hw
.tex
.offset
.cmd
[R300_TEX_CMD_0
] =
852 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_OFFSET_0
, 0);
853 r300
->hw
.tex
.offset
.emit
= &emit_tex_offsets
;
855 ALLOC_STATE(tex
.chroma_key
, variable
, mtu
+ 1, 0);
856 r300
->hw
.tex
.chroma_key
.cmd
[R300_TEX_CMD_0
] =
857 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_CHROMA_KEY_0
, 0);
859 ALLOC_STATE(tex
.border_color
, variable
, mtu
+ 1, 0);
860 r300
->hw
.tex
.border_color
.cmd
[R300_TEX_CMD_0
] =
861 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_BORDER_COLOR_0
, 0);
863 radeon_init_query_stateobj(&r300
->radeon
, R300_QUERYOBJ_CMDSIZE
);
864 if (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV530
) {
865 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, RV530_FG_ZBREG_DEST
, 1);
866 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_0
] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
;
868 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_REG_DEST
, 1);
869 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_0
] = R300_RASTER_PIPE_SELECT_ALL
;
871 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_ZPASS_DATA
, 1);
872 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_1
] = 0;
874 r300
->radeon
.hw
.is_dirty
= GL_TRUE
;
875 r300
->radeon
.hw
.all_dirty
= GL_TRUE
;
877 rcommonInitCmdBuf(&r300
->radeon
);