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r300: fix missing BEGIN/END batches
[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Nicolai Haehnle <prefect_@gmx.net>
34 */
35
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
43
44 #include "drm.h"
45 #include "radeon_drm.h"
46
47 #include "r300_context.h"
48 #include "r300_ioctl.h"
49 #include "radeon_reg.h"
50 #include "r300_reg.h"
51 #include "r300_cmdbuf.h"
52 #include "r300_emit.h"
53 #include "radeon_bocs_wrapper.h"
54 #include "radeon_mipmap_tree.h"
55 #include "r300_state.h"
56 #include "radeon_reg.h"
57
58 /** # of dwords reserved for additional instructions that may need to be written
59 * during flushing.
60 */
61 #define SPACE_FOR_FLUSHING 4
62
63 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
64 {
65 if (r300->radeon.radeonScreen->kernel_mm) {
66 return ((((*pkt) >> 16) & 0x3FFF) + 1);
67 } else {
68 drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
69 return t->packet0.count;
70 }
71 }
72
73 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
74 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
75
76 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
77 {
78 r300ContextPtr r300 = R300_CONTEXT(ctx);
79 BATCH_LOCALS(&r300->radeon);
80 drm_r300_cmd_header_t cmd;
81 uint32_t addr, ndw, i;
82
83 if (!r300->radeon.radeonScreen->kernel_mm) {
84 uint32_t dwords;
85 dwords = (*atom->check) (ctx, atom);
86 BEGIN_BATCH_NO_AUTOSTATE(dwords);
87 OUT_BATCH_TABLE(atom->cmd, dwords);
88 END_BATCH();
89 return;
90 }
91
92 cmd.u = atom->cmd[0];
93 addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
94 ndw = cmd.vpu.count * 4;
95 if (ndw) {
96
97 if (r300->vap_flush_needed) {
98 BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
99
100 /* flush processing vertices */
101 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
102 OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
103 OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
104 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
105 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
106 r300->vap_flush_needed = GL_FALSE;
107 } else {
108 BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
109 }
110 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
111 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
112 for (i = 0; i < ndw; i++) {
113 OUT_BATCH(atom->cmd[i+1]);
114 }
115 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
116 END_BATCH();
117 }
118 }
119
120 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
121 {
122 r300ContextPtr r300 = R300_CONTEXT(ctx);
123 BATCH_LOCALS(&r300->radeon);
124 drm_r300_cmd_header_t cmd;
125 uint32_t addr, ndw, i, sz;
126 int type, clamp, stride;
127
128 if (!r300->radeon.radeonScreen->kernel_mm) {
129 uint32_t dwords;
130 dwords = (*atom->check) (ctx, atom);
131 BEGIN_BATCH_NO_AUTOSTATE(dwords);
132 OUT_BATCH_TABLE(atom->cmd, dwords);
133 END_BATCH();
134 return;
135 }
136
137 cmd.u = atom->cmd[0];
138 sz = cmd.r500fp.count;
139 addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
140 type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
141 clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
142
143 addr |= (type << 16);
144 addr |= (clamp << 17);
145
146 stride = type ? 4 : 6;
147
148 ndw = sz * stride;
149 if (ndw) {
150
151 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
152 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
153 OUT_BATCH(addr);
154 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
155 for (i = 0; i < ndw; i++) {
156 OUT_BATCH(atom->cmd[i+1]);
157 }
158 END_BATCH();
159 }
160 }
161
162 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
163 {
164 r300ContextPtr r300 = R300_CONTEXT(ctx);
165 BATCH_LOCALS(&r300->radeon);
166 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
167 int i;
168
169 for(i = 0; i < numtmus; ++i) {
170 radeonTexObj *t = r300->hw.textures[i];
171 if (t && !t->image_override) {
172 BEGIN_BATCH_NO_AUTOSTATE(4);
173 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
174 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
175 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
176 END_BATCH();
177 } else if (!t) {
178 /* Texture unit hasn't a texture bound.
179 * We assign the current color buffer as a fakery to make
180 * KIL work on KMS (without it, the CS checker will complain).
181 */
182 if (r300->radeon.radeonScreen->kernel_mm) {
183 struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
184 if (rrb && rrb->bo) {
185 BEGIN_BATCH_NO_AUTOSTATE(4);
186 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
187 OUT_BATCH_RELOC(0, rrb->bo, 0,
188 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
189 END_BATCH();
190 }
191 }
192 } else { /* override cases */
193 if (t->bo) {
194 BEGIN_BATCH_NO_AUTOSTATE(4);
195 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
196 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
197 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
198 END_BATCH();
199 } else if (!r300->radeon.radeonScreen->kernel_mm) {
200 BEGIN_BATCH_NO_AUTOSTATE(2);
201 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
202 OUT_BATCH(t->override_offset);
203 END_BATCH();
204 } else {
205 /* Texture unit hasn't a texture bound nothings to do */
206 }
207 }
208 }
209 }
210
211 void r300_emit_scissor(GLcontext *ctx)
212 {
213 r300ContextPtr r300 = R300_CONTEXT(ctx);
214 BATCH_LOCALS(&r300->radeon);
215 unsigned x1, y1, x2, y2;
216 struct radeon_renderbuffer *rrb;
217
218 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
219 return;
220 }
221 rrb = radeon_get_colorbuffer(&r300->radeon);
222 if (!rrb || !rrb->bo) {
223 fprintf(stderr, "no rrb\n");
224 return;
225 }
226 if (r300->radeon.state.scissor.enabled) {
227 x1 = r300->radeon.state.scissor.rect.x1;
228 y1 = r300->radeon.state.scissor.rect.y1;
229 x2 = r300->radeon.state.scissor.rect.x2 - 1;
230 y2 = r300->radeon.state.scissor.rect.y2 - 1;
231 } else {
232 x1 = 0;
233 y1 = 0;
234 x2 = rrb->base.Width - 1;
235 y2 = rrb->base.Height - 1;
236 }
237 if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
238 x1 += R300_SCISSORS_OFFSET;
239 y1 += R300_SCISSORS_OFFSET;
240 x2 += R300_SCISSORS_OFFSET;
241 y2 += R300_SCISSORS_OFFSET;
242 }
243 BEGIN_BATCH_NO_AUTOSTATE(3);
244 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
245 OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
246 OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
247 END_BATCH();
248 }
249
250 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
251 {
252 r300ContextPtr r300 = R300_CONTEXT(ctx);
253 BATCH_LOCALS(&r300->radeon);
254 struct radeon_renderbuffer *rrb;
255 uint32_t cbpitch;
256 uint32_t offset = r300->radeon.state.color.draw_offset;
257 uint32_t dw = 6;
258 int i;
259
260 rrb = radeon_get_colorbuffer(&r300->radeon);
261 if (!rrb || !rrb->bo) {
262 fprintf(stderr, "no rrb\n");
263 return;
264 }
265
266 if (RADEON_DEBUG & DEBUG_STATE)
267 fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
268 cbpitch = (rrb->pitch / rrb->cpp);
269 if (rrb->cpp == 4)
270 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
271 else switch (rrb->base._ActualFormat) {
272 case GL_RGB5:
273 cbpitch |= R300_COLOR_FORMAT_RGB565;
274 break;
275 case GL_RGBA4:
276 cbpitch |= R300_COLOR_FORMAT_ARGB4444;
277 break;
278 case GL_RGB5_A1:
279 cbpitch |= R300_COLOR_FORMAT_ARGB1555;
280 break;
281 }
282
283 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
284 cbpitch |= R300_COLOR_TILE_ENABLE;
285
286 if (r300->radeon.radeonScreen->kernel_mm)
287 dw += 2;
288 BEGIN_BATCH_NO_AUTOSTATE(dw);
289 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
290 OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
291 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
292 if (!r300->radeon.radeonScreen->kernel_mm)
293 OUT_BATCH(cbpitch);
294 else
295 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
296 END_BATCH();
297 if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
298 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
299 BEGIN_BATCH_NO_AUTOSTATE(3);
300 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
301 OUT_BATCH(0);
302 OUT_BATCH(((rrb->base.Width - 1) << R300_SCISSORS_X_SHIFT) |
303 ((rrb->base.Height - 1) << R300_SCISSORS_Y_SHIFT));
304 END_BATCH();
305 BEGIN_BATCH_NO_AUTOSTATE(16);
306 for (i = 0; i < 4; i++) {
307 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
308 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
309 OUT_BATCH(((rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT));
310 }
311 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
312 OUT_BATCH(0xAAAA);
313 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
314 OUT_BATCH(0xffffff);
315 END_BATCH();
316 } else {
317 BEGIN_BATCH_NO_AUTOSTATE(3);
318 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
319 OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
320 (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
321 OUT_BATCH(((rrb->base.Width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
322 ((rrb->base.Height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
323 END_BATCH();
324 BEGIN_BATCH_NO_AUTOSTATE(16);
325 for (i = 0; i < 4; i++) {
326 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
327 OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
328 OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) |
329 ((R300_SCISSORS_OFFSET + rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT));
330 }
331 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
332 OUT_BATCH(0xAAAA);
333 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
334 OUT_BATCH(0xffffff);
335 END_BATCH();
336 }
337 }
338 }
339
340 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
341 {
342 r300ContextPtr r300 = R300_CONTEXT(ctx);
343 BATCH_LOCALS(&r300->radeon);
344 struct radeon_renderbuffer *rrb;
345 uint32_t zbpitch;
346 uint32_t dw;
347
348 rrb = radeon_get_depthbuffer(&r300->radeon);
349 if (!rrb)
350 return;
351
352 zbpitch = (rrb->pitch / rrb->cpp);
353 if (!r300->radeon.radeonScreen->kernel_mm) {
354 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
355 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
356 }
357 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
358 zbpitch |= R300_DEPTHMICROTILE_TILED;
359 }
360 }
361
362 dw = 6;
363 if (r300->radeon.radeonScreen->kernel_mm)
364 dw += 2;
365 BEGIN_BATCH_NO_AUTOSTATE(dw);
366 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
367 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
368 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
369 if (!r300->radeon.radeonScreen->kernel_mm)
370 OUT_BATCH(zbpitch);
371 else
372 OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
373 END_BATCH();
374 }
375
376 static void emit_gb_misc(GLcontext *ctx, struct radeon_state_atom * atom)
377 {
378 r300ContextPtr r300 = R300_CONTEXT(ctx);
379 BATCH_LOCALS(&r300->radeon);
380 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
381 BEGIN_BATCH_NO_AUTOSTATE(4);
382 OUT_BATCH(atom->cmd[0]);
383 OUT_BATCH(atom->cmd[1]);
384 OUT_BATCH(atom->cmd[2]);
385 OUT_BATCH(atom->cmd[3]);
386 END_BATCH();
387 }
388 }
389
390 static void emit_threshold_misc(GLcontext *ctx, struct radeon_state_atom * atom)
391 {
392 r300ContextPtr r300 = R300_CONTEXT(ctx);
393 BATCH_LOCALS(&r300->radeon);
394 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
395 BEGIN_BATCH_NO_AUTOSTATE(3);
396 OUT_BATCH(atom->cmd[0]);
397 OUT_BATCH(atom->cmd[1]);
398 OUT_BATCH(atom->cmd[2]);
399 END_BATCH();
400 }
401 }
402
403 static void emit_shade_misc(GLcontext *ctx, struct radeon_state_atom * atom)
404 {
405 r300ContextPtr r300 = R300_CONTEXT(ctx);
406 BATCH_LOCALS(&r300->radeon);
407
408 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
409 BEGIN_BATCH_NO_AUTOSTATE(2);
410 OUT_BATCH(atom->cmd[0]);
411 OUT_BATCH(atom->cmd[1]);
412 END_BATCH();
413 }
414 }
415
416 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
417 {
418 r300ContextPtr r300 = R300_CONTEXT(ctx);
419 BATCH_LOCALS(&r300->radeon);
420 struct radeon_renderbuffer *rrb;
421 uint32_t format = 0;
422
423 rrb = radeon_get_depthbuffer(&r300->radeon);
424 if (!rrb)
425 format = 0;
426 else {
427 if (rrb->cpp == 2)
428 format = R300_DEPTHFORMAT_16BIT_INT_Z;
429 else if (rrb->cpp == 4)
430 format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
431 }
432
433 BEGIN_BATCH_NO_AUTOSTATE(5);
434 OUT_BATCH(atom->cmd[0]);
435 atom->cmd[1] &= ~0xf;
436 atom->cmd[1] |= format;
437 OUT_BATCH(atom->cmd[1]);
438 OUT_BATCH(atom->cmd[2]);
439 OUT_BATCH(atom->cmd[3]);
440 OUT_BATCH(atom->cmd[4]);
441 END_BATCH();
442 }
443
444 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
445 {
446 return atom->cmd_size;
447 }
448
449 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
450 {
451 r300ContextPtr r300 = R300_CONTEXT(ctx);
452 int cnt;
453 if (atom->cmd[0] == CP_PACKET2) {
454 return 0;
455 }
456 cnt = packet0_count(r300, atom->cmd);
457 return cnt ? cnt + 1 : 0;
458 }
459
460 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
461 {
462 int cnt;
463
464 cnt = vpu_count(atom->cmd);
465 return cnt ? (cnt * 4) + 1 : 0;
466 }
467
468 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
469 {
470 int cnt;
471
472 cnt = r500fp_count(atom->cmd);
473 return cnt ? (cnt * 6) + 1 : 0;
474 }
475
476 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
477 {
478 int cnt;
479
480 cnt = r500fp_count(atom->cmd);
481 return cnt ? (cnt * 4) + 1 : 0;
482 }
483
484 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
485 do { \
486 r300->hw.ATOM.cmd_size = (SZ); \
487 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
488 r300->hw.ATOM.name = #ATOM; \
489 r300->hw.ATOM.idx = (IDX); \
490 r300->hw.ATOM.check = check_##CHK; \
491 r300->hw.ATOM.dirty = GL_FALSE; \
492 r300->radeon.hw.max_state_size += (SZ); \
493 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
494 } while (0)
495 /**
496 * Allocate memory for the command buffer and initialize the state atom
497 * list. Note that the initial hardware state is set by r300InitState().
498 */
499 void r300InitCmdBuf(r300ContextPtr r300)
500 {
501 int mtu;
502 int has_tcl;
503 int is_r500 = 0;
504
505 has_tcl = r300->options.hw_tcl_enabled;
506
507 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
508 is_r500 = 1;
509
510 r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
511
512 mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
513 if (RADEON_DEBUG & DEBUG_TEXTURE) {
514 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
515 }
516
517 /* Setup the atom linked list */
518 make_empty_list(&r300->radeon.hw.atomlist);
519 r300->radeon.hw.atomlist.name = "atom-list";
520
521 /* Initialize state atoms */
522 ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
523 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
524 ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
525 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
526 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
527 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
528 if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
529 ALLOC_STATE(vap_index_offset, always, 2, 0);
530 r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
531 r300->hw.vap_index_offset.cmd[1] = 0;
532 }
533 ALLOC_STATE(vte, always, 3, 0);
534 r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
535 ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
536 r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
537 ALLOC_STATE(vap_cntl_status, always, 2, 0);
538 r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
539 ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
540 r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
541 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
542 ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
543 r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
544 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
545 ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
546 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
547 ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
548 r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
549
550 if (has_tcl) {
551 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
552 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
553 ALLOC_STATE(vap_clip, always, 5, 0);
554 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
555 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
556 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
557 }
558
559 ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
560 r300->hw.vof.cmd[R300_VOF_CMD_0] =
561 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
562
563 if (has_tcl) {
564 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
565 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
566 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
567 }
568
569 ALLOC_STATE(gb_enable, always, 2, 0);
570 r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
571 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
572 r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
573 r300->hw.gb_misc.emit = emit_gb_misc;
574 ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
575 r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
576 ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
577 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
578 ALLOC_STATE(ga_point_s0, always, 5, 0);
579 r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
580 ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
581 r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
582 ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
583 r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
584 ALLOC_STATE(ga_point_minmax, always, 4, 0);
585 r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
586 ALLOC_STATE(lcntl, always, 2, 0);
587 r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
588 ALLOC_STATE(ga_line_stipple, always, 4, 0);
589 r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
590 ALLOC_STATE(shade, always, 2, 0);
591 r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
592 r300->hw.shade.emit = emit_shade_misc;
593 ALLOC_STATE(shade2, always, 4, 0);
594 r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
595 ALLOC_STATE(polygon_mode, always, 4, 0);
596 r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
597 ALLOC_STATE(fogp, always, 3, 0);
598 r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
599 ALLOC_STATE(zbias_cntl, always, 2, 0);
600 r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
601 ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
602 r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
603 cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
604 ALLOC_STATE(occlusion_cntl, always, 2, 0);
605 r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
606 ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
607 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
608 ALLOC_STATE(su_depth_scale, always, 3, 0);
609 r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
610 ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
611 r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
612 if (is_r500) {
613 ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0);
614 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
615 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
616 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
617 } else {
618 ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0);
619 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
620 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
621 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
622 }
623 ALLOC_STATE(sc_hyperz, always, 3, 0);
624 r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
625 ALLOC_STATE(sc_screendoor, always, 2, 0);
626 r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
627 ALLOC_STATE(us_out_fmt, always, 6, 0);
628 r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
629
630 if (is_r500) {
631 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
632 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
633 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
634 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
635 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
636 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
637
638 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
639 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
640 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
641 r300->hw.r500fp.emit = emit_r500fp;
642 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
643 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
644 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
645 r300->hw.r500fp_const.emit = emit_r500fp;
646 } else {
647 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
648 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
649 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
650
651 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
652 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
653
654 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
655 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
656 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
657 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
658 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
659 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
660 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
661 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
662 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
663 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
664 }
665 ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
666 r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
667 ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
668 r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
669 ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
670 r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
671 ALLOC_STATE(fg_depth_src, always, 2, 0);
672 r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
673 ALLOC_STATE(rb3d_cctl, always, 2, 0);
674 r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
675 ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
676 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
677 ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
678 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
679 if (is_r500) {
680 ALLOC_STATE(blend_color, always, 3, 0);
681 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
682 } else {
683 ALLOC_STATE(blend_color, always, 2, 0);
684 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
685 }
686 ALLOC_STATE(rop, always, 2, 0);
687 r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
688 ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
689 r300->hw.cb.emit = &emit_cb_offset;
690 ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
691 r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
692 ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
693 r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
694 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
695 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
696 r300->hw.rb3d_discard_src_pixel_lte_threshold.emit = emit_threshold_misc;
697 ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
698 r300->hw.zs.cmd[R300_ZS_CMD_0] =
699 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
700
701 ALLOC_STATE(zstencil_format, always, 5, 0);
702 r300->hw.zstencil_format.cmd[0] =
703 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
704 r300->hw.zstencil_format.emit = emit_zstencil_format;
705
706 ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
707 r300->hw.zb.emit = emit_zb_offset;
708 ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
709 r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
710 ALLOC_STATE(zb_zmask, always, 3, 0);
711 r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
712 ALLOC_STATE(zb_hiz_offset, always, 2, 0);
713 r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
714 ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
715 r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
716
717 /* VPU only on TCL */
718 if (has_tcl) {
719 int i;
720 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
721 r300->hw.vpi.cmd[0] =
722 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
723 r300->hw.vpi.emit = emit_vpu;
724
725 if (is_r500) {
726 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
727 r300->hw.vpp.cmd[0] =
728 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
729 r300->hw.vpp.emit = emit_vpu;
730
731 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
732 r300->hw.vps.cmd[0] =
733 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
734 r300->hw.vps.emit = emit_vpu;
735
736 for (i = 0; i < 6; i++) {
737 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
738 r300->hw.vpucp[i].cmd[0] =
739 cmdvpu(r300->radeon.radeonScreen,
740 R500_PVS_UCP_START + i, 1);
741 r300->hw.vpucp[i].emit = emit_vpu;
742 }
743 } else {
744 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
745 r300->hw.vpp.cmd[0] =
746 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
747 r300->hw.vpp.emit = emit_vpu;
748
749 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
750 r300->hw.vps.cmd[0] =
751 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
752 r300->hw.vps.emit = emit_vpu;
753
754 for (i = 0; i < 6; i++) {
755 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
756 r300->hw.vpucp[i].cmd[0] =
757 cmdvpu(r300->radeon.radeonScreen,
758 R300_PVS_UCP_START + i, 1);
759 r300->hw.vpucp[i].emit = emit_vpu;
760 }
761 }
762 }
763
764 /* Textures */
765 ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
766 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
767 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
768
769 ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
770 r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
771 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
772
773 ALLOC_STATE(tex.size, variable, mtu + 1, 0);
774 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
775
776 ALLOC_STATE(tex.format, variable, mtu + 1, 0);
777 r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
778 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
779
780 ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
781 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
782
783 ALLOC_STATE(tex.offset, variable, 1, 0);
784 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
785 cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
786 r300->hw.tex.offset.emit = &emit_tex_offsets;
787
788 ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
789 r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
790 cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
791
792 ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
793 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
794 cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
795
796 r300->radeon.hw.is_dirty = GL_TRUE;
797 r300->radeon.hw.all_dirty = GL_TRUE;
798
799 rcommonInitCmdBuf(&r300->radeon);
800 }