2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Nicolai Haehnle <prefect_@gmx.net>
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
45 #include "radeon_drm.h"
47 #include "r300_context.h"
48 #include "r300_ioctl.h"
49 #include "radeon_reg.h"
51 #include "r300_cmdbuf.h"
52 #include "r300_emit.h"
53 #include "radeon_bocs_wrapper.h"
54 #include "radeon_mipmap_tree.h"
55 #include "r300_state.h"
56 #include "radeon_reg.h"
57 #include "radeon_queryobj.h"
59 /** # of dwords reserved for additional instructions that may need to be written
62 #define SPACE_FOR_FLUSHING 4
64 static unsigned packet0_count(r300ContextPtr r300
, uint32_t *pkt
)
66 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
67 return ((((*pkt
) >> 16) & 0x3FFF) + 1);
69 drm_r300_cmd_header_t
*t
= (drm_r300_cmd_header_t
*)pkt
;
70 return t
->packet0
.count
;
74 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
75 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
77 int check_vpu(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
79 r300ContextPtr r300
= R300_CONTEXT(ctx
);
82 cnt
= vpu_count(atom
->cmd
);
84 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
88 return cnt
? (cnt
* 4) + extra
: 0;
92 void emit_vpu(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
94 r300ContextPtr r300
= R300_CONTEXT(ctx
);
95 BATCH_LOCALS(&r300
->radeon
);
96 drm_r300_cmd_header_t cmd
;
100 addr
= (cmd
.vpu
.adrhi
<< 8) | cmd
.vpu
.adrlo
;
101 ndw
= atom
->check(ctx
, atom
);
103 BEGIN_BATCH_NO_AUTOSTATE(ndw
);
106 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG
, addr
);
107 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA
, ndw
-1) | RADEON_ONE_REG_WR
);
108 OUT_BATCH_TABLE(&atom
->cmd
[1], ndw
);
109 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
113 void emit_r500fp(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
115 r300ContextPtr r300
= R300_CONTEXT(ctx
);
116 BATCH_LOCALS(&r300
->radeon
);
117 drm_r300_cmd_header_t cmd
;
118 uint32_t addr
, ndw
, sz
;
121 ndw
= atom
->check(ctx
, atom
);
123 cmd
.u
= atom
->cmd
[0];
124 sz
= cmd
.r500fp
.count
;
125 addr
= ((cmd
.r500fp
.adrhi_flags
& 1) << 8) | cmd
.r500fp
.adrlo
;
126 type
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_TYPE
);
127 clamp
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_CLAMP
);
129 addr
|= (type
<< 16);
130 addr
|= (clamp
<< 17);
132 BEGIN_BATCH_NO_AUTOSTATE(ndw
);
133 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX
, 0));
136 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA
, ndw
-1) | RADEON_ONE_REG_WR
);
137 OUT_BATCH_TABLE(&atom
->cmd
[1], ndw
);
141 static int check_tex_offsets(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
143 r300ContextPtr r300
= R300_CONTEXT(ctx
);
144 int numtmus
= packet0_count(r300
, r300
->hw
.tex
.offset
.cmd
);
146 if (atom
->cmd
[0] == CP_PACKET2
) {
149 for(i
= 0; i
< numtmus
; ++i
) {
150 radeonTexObj
*t
= r300
->hw
.textures
[i
];
151 if (!t
&& !r300
->radeon
.radeonScreen
->kernel_mm
) {
153 } else if (t
&& t
->image_override
&& !t
->bo
) {
154 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
162 static void emit_tex_offsets(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
164 r300ContextPtr r300
= R300_CONTEXT(ctx
);
165 BATCH_LOCALS(&r300
->radeon
);
166 int numtmus
= packet0_count(r300
, r300
->hw
.tex
.offset
.cmd
);
169 for(i
= 0; i
< numtmus
; ++i
) {
170 radeonTexObj
*t
= r300
->hw
.textures
[i
];
171 if (t
&& !t
->image_override
) {
172 BEGIN_BATCH_NO_AUTOSTATE(4);
173 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
174 OUT_BATCH_RELOC(t
->tile_bits
, t
->mt
->bo
, 0,
175 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
178 /* Texture unit hasn't a texture bound.
179 * We assign the current color buffer as a fakery to make
180 * KIL work on KMS (without it, the CS checker will complain).
182 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
183 struct radeon_renderbuffer
*rrb
= radeon_get_colorbuffer(&r300
->radeon
);
184 if (rrb
&& rrb
->bo
) {
185 BEGIN_BATCH_NO_AUTOSTATE(4);
186 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
187 OUT_BATCH_RELOC(0, rrb
->bo
, 0,
188 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
192 } else { /* override cases */
194 BEGIN_BATCH_NO_AUTOSTATE(4);
195 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
196 OUT_BATCH_RELOC(t
->tile_bits
, t
->bo
, 0,
197 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
199 } else if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
200 BEGIN_BATCH_NO_AUTOSTATE(2);
201 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
202 OUT_BATCH(t
->override_offset
);
205 /* Texture unit hasn't a texture bound nothings to do */
211 void r300_emit_scissor(GLcontext
*ctx
)
213 r300ContextPtr r300
= R300_CONTEXT(ctx
);
214 BATCH_LOCALS(&r300
->radeon
);
215 unsigned x1
, y1
, x2
, y2
;
216 struct radeon_renderbuffer
*rrb
;
218 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
221 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
222 if (!rrb
|| !rrb
->bo
) {
223 fprintf(stderr
, "no rrb\n");
226 if (r300
->radeon
.state
.scissor
.enabled
) {
227 x1
= r300
->radeon
.state
.scissor
.rect
.x1
;
228 y1
= r300
->radeon
.state
.scissor
.rect
.y1
;
229 x2
= r300
->radeon
.state
.scissor
.rect
.x2
;
230 y2
= r300
->radeon
.state
.scissor
.rect
.y2
;
234 x2
= rrb
->base
.Width
- 1;
235 y2
= rrb
->base
.Height
- 1;
237 if (r300
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV515
) {
238 x1
+= R300_SCISSORS_OFFSET
;
239 y1
+= R300_SCISSORS_OFFSET
;
240 x2
+= R300_SCISSORS_OFFSET
;
241 y2
+= R300_SCISSORS_OFFSET
;
243 BEGIN_BATCH_NO_AUTOSTATE(3);
244 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
245 OUT_BATCH((x1
<< R300_SCISSORS_X_SHIFT
)|(y1
<< R300_SCISSORS_Y_SHIFT
));
246 OUT_BATCH((x2
<< R300_SCISSORS_X_SHIFT
)|(y2
<< R300_SCISSORS_Y_SHIFT
));
249 static int check_cb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
251 r300ContextPtr r300
= R300_CONTEXT(ctx
);
252 uint32_t dw
= 6 + 3 + 16;
253 if (r300
->radeon
.radeonScreen
->kernel_mm
)
255 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
261 static void emit_cb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
263 r300ContextPtr r300
= R300_CONTEXT(ctx
);
264 BATCH_LOCALS(&r300
->radeon
);
265 struct radeon_renderbuffer
*rrb
;
267 uint32_t offset
= r300
->radeon
.state
.color
.draw_offset
;
271 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
272 if (!rrb
|| !rrb
->bo
) {
273 fprintf(stderr
, "no rrb\n");
277 if (RADEON_DEBUG
& RADEON_STATE
)
278 fprintf(stderr
,"rrb is %p %d %dx%d\n", rrb
, offset
, rrb
->base
.Width
, rrb
->base
.Height
);
279 cbpitch
= (rrb
->pitch
/ rrb
->cpp
);
281 cbpitch
|= R300_COLOR_FORMAT_ARGB8888
;
282 else switch (rrb
->base
.Format
) {
283 case MESA_FORMAT_RGB565
:
284 cbpitch
|= R300_COLOR_FORMAT_RGB565
;
286 case MESA_FORMAT_ARGB4444
:
287 cbpitch
|= R300_COLOR_FORMAT_ARGB4444
;
289 case MESA_FORMAT_ARGB1555
:
290 cbpitch
|= R300_COLOR_FORMAT_ARGB1555
;
293 _mesa_problem(ctx
, "unexpected format in emit_cb_offset()");
296 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
297 cbpitch
|= R300_COLOR_TILE_ENABLE
;
299 if (r300
->radeon
.radeonScreen
->kernel_mm
)
301 BEGIN_BATCH_NO_AUTOSTATE(dw
);
302 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0
, 1);
303 OUT_BATCH_RELOC(offset
, rrb
->bo
, offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
304 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0
, 1);
305 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
308 OUT_BATCH_RELOC(cbpitch
, rrb
->bo
, cbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
310 if (r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
311 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
) {
312 BEGIN_BATCH_NO_AUTOSTATE(3);
313 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
315 OUT_BATCH(((rrb
->base
.Width
- 1) << R300_SCISSORS_X_SHIFT
) |
316 ((rrb
->base
.Height
- 1) << R300_SCISSORS_Y_SHIFT
));
318 BEGIN_BATCH_NO_AUTOSTATE(16);
319 for (i
= 0; i
< 4; i
++) {
320 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0
+ (i
* 8), 2);
321 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT
) | (0 << R300_CLIPRECT_Y_SHIFT
));
322 OUT_BATCH(((rrb
->base
.Width
- 1) << R300_CLIPRECT_X_SHIFT
) | ((rrb
->base
.Height
- 1) << R300_CLIPRECT_Y_SHIFT
));
324 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE
, 1);
326 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR
, 1);
330 BEGIN_BATCH_NO_AUTOSTATE(3);
331 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
332 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_SCISSORS_X_SHIFT
) |
333 (R300_SCISSORS_OFFSET
<< R300_SCISSORS_Y_SHIFT
));
334 OUT_BATCH(((rrb
->base
.Width
+ R300_SCISSORS_OFFSET
- 1) << R300_SCISSORS_X_SHIFT
) |
335 ((rrb
->base
.Height
+ R300_SCISSORS_OFFSET
- 1) << R300_SCISSORS_Y_SHIFT
));
337 BEGIN_BATCH_NO_AUTOSTATE(16);
338 for (i
= 0; i
< 4; i
++) {
339 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0
+ (i
* 8), 2);
340 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_CLIPRECT_X_SHIFT
) | (R300_SCISSORS_OFFSET
<< R300_CLIPRECT_Y_SHIFT
));
341 OUT_BATCH(((R300_SCISSORS_OFFSET
+ rrb
->base
.Width
- 1) << R300_CLIPRECT_X_SHIFT
) |
342 ((R300_SCISSORS_OFFSET
+ rrb
->base
.Height
- 1) << R300_CLIPRECT_Y_SHIFT
));
344 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE
, 1);
346 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR
, 1);
353 static int check_zb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
355 r300ContextPtr r300
= R300_CONTEXT(ctx
);
358 if (r300
->radeon
.radeonScreen
->kernel_mm
)
363 static void emit_zb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
365 r300ContextPtr r300
= R300_CONTEXT(ctx
);
366 BATCH_LOCALS(&r300
->radeon
);
367 struct radeon_renderbuffer
*rrb
;
369 uint32_t dw
= atom
->check(ctx
, atom
);
371 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
375 zbpitch
= (rrb
->pitch
/ rrb
->cpp
);
376 if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
377 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
378 zbpitch
|= R300_DEPTHMACROTILE_ENABLE
;
380 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
){
381 zbpitch
|= R300_DEPTHMICROTILE_TILED
;
385 BEGIN_BATCH_NO_AUTOSTATE(dw
);
386 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET
, 1);
387 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
388 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH
, 1);
389 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
392 OUT_BATCH_RELOC(cbpitch
, rrb
->bo
, zbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
396 static void emit_zstencil_format(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
398 r300ContextPtr r300
= R300_CONTEXT(ctx
);
399 BATCH_LOCALS(&r300
->radeon
);
400 struct radeon_renderbuffer
*rrb
;
403 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
408 format
= R300_DEPTHFORMAT_16BIT_INT_Z
;
409 else if (rrb
->cpp
== 4)
410 format
= R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL
;
413 BEGIN_BATCH_NO_AUTOSTATE(atom
->cmd_size
);
414 OUT_BATCH(atom
->cmd
[0]);
415 atom
->cmd
[1] &= ~0xf;
416 atom
->cmd
[1] |= format
;
417 OUT_BATCH(atom
->cmd
[1]);
418 OUT_BATCH(atom
->cmd
[2]);
419 OUT_BATCH(atom
->cmd
[3]);
420 OUT_BATCH(atom
->cmd
[4]);
424 static int check_never(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
429 static int check_always(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
431 return atom
->cmd_size
;
434 static int check_variable(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
436 r300ContextPtr r300
= R300_CONTEXT(ctx
);
438 if (atom
->cmd
[0] == CP_PACKET2
) {
441 cnt
= packet0_count(r300
, atom
->cmd
);
442 return cnt
? cnt
+ 1 : 0;
445 int check_r500fp(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
448 r300ContextPtr r300
= R300_CONTEXT(ctx
);
450 cnt
= r500fp_count(atom
->cmd
);
451 if (r300
->radeon
.radeonScreen
->kernel_mm
)
454 return cnt
? (cnt
* 6) + extra
: 0;
457 int check_r500fp_const(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
460 r300ContextPtr r300
= R300_CONTEXT(ctx
);
462 cnt
= r500fp_count(atom
->cmd
);
463 if (r300
->radeon
.radeonScreen
->kernel_mm
)
466 cnt
= r500fp_count(atom
->cmd
);
467 return cnt
? (cnt
* 4) + extra
: 0;
470 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
472 r300->hw.ATOM.cmd_size = (SZ); \
473 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
474 r300->hw.ATOM.name = #ATOM; \
475 r300->hw.ATOM.idx = (IDX); \
476 r300->hw.ATOM.check = check_##CHK; \
477 r300->hw.ATOM.dirty = GL_FALSE; \
478 r300->radeon.hw.max_state_size += (SZ); \
479 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
482 * Allocate memory for the command buffer and initialize the state atom
483 * list. Note that the initial hardware state is set by r300InitState().
485 void r300InitCmdBuf(r300ContextPtr r300
)
491 has_tcl
= r300
->options
.hw_tcl_enabled
;
493 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
496 r300
->radeon
.hw
.max_state_size
= 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
498 mtu
= r300
->radeon
.glCtx
->Const
.MaxTextureUnits
;
499 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
500 fprintf(stderr
, "Using %d maximum texture units..\n", mtu
);
503 /* Setup the atom linked list */
504 make_empty_list(&r300
->radeon
.hw
.atomlist
);
505 r300
->radeon
.hw
.atomlist
.name
= "atom-list";
507 /* Initialize state atoms */
508 ALLOC_STATE(vpt
, always
, R300_VPT_CMDSIZE
, 0);
509 r300
->hw
.vpt
.cmd
[R300_VPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VPORT_XSCALE
, 6);
510 ALLOC_STATE(vap_cntl
, always
, R300_VAP_CNTL_SIZE
, 0);
511 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_STATE_FLUSH_REG
, 1);
512 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH_1
] = 0;
513 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_CMD
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL
, 1);
514 if (is_r500
&& !r300
->radeon
.radeonScreen
->kernel_mm
) {
515 ALLOC_STATE(vap_index_offset
, always
, 2, 0);
516 r300
->hw
.vap_index_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_VAP_INDEX_OFFSET
, 1);
517 r300
->hw
.vap_index_offset
.cmd
[1] = 0;
519 ALLOC_STATE(vte
, always
, 3, 0);
520 r300
->hw
.vte
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VTE_CNTL
, 2);
521 ALLOC_STATE(vap_vf_max_vtx_indx
, always
, 3, 0);
522 r300
->hw
.vap_vf_max_vtx_indx
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VF_MAX_VTX_INDX
, 2);
523 ALLOC_STATE(vap_cntl_status
, always
, 2, 0);
524 r300
->hw
.vap_cntl_status
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL_STATUS
, 1);
525 ALLOC_STATE(vir
[0], variable
, R300_VIR_CMDSIZE
, 0);
526 r300
->hw
.vir
[0].cmd
[R300_VIR_CMD_0
] =
527 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_0
, 1);
528 ALLOC_STATE(vir
[1], variable
, R300_VIR_CMDSIZE
, 1);
529 r300
->hw
.vir
[1].cmd
[R300_VIR_CMD_0
] =
530 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_EXT_0
, 1);
531 ALLOC_STATE(vic
, always
, R300_VIC_CMDSIZE
, 0);
532 r300
->hw
.vic
.cmd
[R300_VIC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VTX_STATE_CNTL
, 2);
533 ALLOC_STATE(vap_psc_sgn_norm_cntl
, always
, 2, 0);
534 r300
->hw
.vap_psc_sgn_norm_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PSC_SGN_NORM_CNTL
, SGN_NORM_ZERO_CLAMP_MINUS_ONE
);
537 ALLOC_STATE(vap_clip_cntl
, always
, 2, 0);
538 r300
->hw
.vap_clip_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CLIP_CNTL
, 1);
539 ALLOC_STATE(vap_clip
, always
, 5, 0);
540 r300
->hw
.vap_clip
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_GB_VERT_CLIP_ADJ
, 4);
541 ALLOC_STATE(vap_pvs_vtx_timeout_reg
, always
, 2, 0);
542 r300
->hw
.vap_pvs_vtx_timeout_reg
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, VAP_PVS_VTX_TIMEOUT_REG
, 1);
545 ALLOC_STATE(vof
, always
, R300_VOF_CMDSIZE
, 0);
546 r300
->hw
.vof
.cmd
[R300_VOF_CMD_0
] =
547 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_OUTPUT_VTX_FMT_0
, 2);
550 ALLOC_STATE(pvs
, always
, R300_PVS_CMDSIZE
, 0);
551 r300
->hw
.pvs
.cmd
[R300_PVS_CMD_0
] =
552 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_CODE_CNTL_0
, 3);
555 ALLOC_STATE(gb_enable
, always
, 2, 0);
556 r300
->hw
.gb_enable
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_ENABLE
, 1);
557 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
558 ALLOC_STATE(gb_misc
, always
, R300_GB_MISC_CMDSIZE
, 0);
560 ALLOC_STATE(gb_misc
, never
, R300_GB_MISC_CMDSIZE
, 0);
562 r300
->hw
.gb_misc
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_MSPOS0
, 3);
563 ALLOC_STATE(gb_misc2
, always
, R300_GB_MISC2_CMDSIZE
, 0);
564 r300
->hw
.gb_misc2
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x401C, 2);
565 ALLOC_STATE(txe
, always
, R300_TXE_CMDSIZE
, 0);
566 r300
->hw
.txe
.cmd
[R300_TXE_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_ENABLE
, 1);
567 ALLOC_STATE(ga_point_s0
, always
, 5, 0);
568 r300
->hw
.ga_point_s0
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_S0
, 4);
569 ALLOC_STATE(ga_triangle_stipple
, always
, 2, 0);
570 r300
->hw
.ga_triangle_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_TRIANGLE_STIPPLE
, 1);
571 ALLOC_STATE(ps
, always
, R300_PS_CMDSIZE
, 0);
572 r300
->hw
.ps
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_SIZE
, 1);
573 ALLOC_STATE(ga_point_minmax
, always
, 4, 0);
574 r300
->hw
.ga_point_minmax
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_MINMAX
, 3);
575 ALLOC_STATE(lcntl
, always
, 2, 0);
576 r300
->hw
.lcntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_CNTL
, 1);
577 ALLOC_STATE(ga_line_stipple
, always
, 4, 0);
578 r300
->hw
.ga_line_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_STIPPLE_VALUE
, 3);
579 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
580 ALLOC_STATE(shade
, always
, 2, 0);
582 ALLOC_STATE(shade
, never
, 2, 0);
584 r300
->hw
.shade
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_ENHANCE
, 1);
585 ALLOC_STATE(shade2
, always
, 4, 0);
586 r300
->hw
.shade2
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x4278, 3);
587 ALLOC_STATE(polygon_mode
, always
, 4, 0);
588 r300
->hw
.polygon_mode
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POLY_MODE
, 3);
589 ALLOC_STATE(fogp
, always
, 3, 0);
590 r300
->hw
.fogp
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_FOG_SCALE
, 2);
591 ALLOC_STATE(zbias_cntl
, always
, 2, 0);
592 r300
->hw
.zbias_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_TEX_WRAP
, 1);
593 ALLOC_STATE(zbs
, always
, R300_ZBS_CMDSIZE
, 0);
594 r300
->hw
.zbs
.cmd
[R300_ZBS_CMD_0
] =
595 cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
596 ALLOC_STATE(occlusion_cntl
, always
, 2, 0);
597 r300
->hw
.occlusion_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_ENABLE
, 1);
598 ALLOC_STATE(cul
, always
, R300_CUL_CMDSIZE
, 0);
599 r300
->hw
.cul
.cmd
[R300_CUL_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_CULL_MODE
, 1);
600 ALLOC_STATE(su_depth_scale
, always
, 3, 0);
601 r300
->hw
.su_depth_scale
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_DEPTH_SCALE
, 2);
602 ALLOC_STATE(rc
, always
, R300_RC_CMDSIZE
, 0);
603 r300
->hw
.rc
.cmd
[R300_RC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_COUNT
, 2);
605 ALLOC_STATE(ri
, variable
, R500_RI_CMDSIZE
, 0);
606 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_IP_0
, 16);
607 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
608 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_INST_0
, 1);
610 ALLOC_STATE(ri
, variable
, R300_RI_CMDSIZE
, 0);
611 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_IP_0
, 8);
612 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
613 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_INST_0
, 1);
615 ALLOC_STATE(sc_hyperz
, always
, 3, 0);
616 r300
->hw
.sc_hyperz
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_HYPERZ
, 2);
617 ALLOC_STATE(sc_screendoor
, always
, 2, 0);
618 r300
->hw
.sc_screendoor
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
619 ALLOC_STATE(us_out_fmt
, always
, 6, 0);
620 r300
->hw
.us_out_fmt
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_OUT_FMT
, 5);
623 ALLOC_STATE(fp
, always
, R500_FP_CMDSIZE
, 0);
624 r300
->hw
.fp
.cmd
[R500_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CONFIG
, 2);
625 r300
->hw
.fp
.cmd
[R500_FP_CNTL
] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
;
626 r300
->hw
.fp
.cmd
[R500_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CODE_ADDR
, 3);
627 r300
->hw
.fp
.cmd
[R500_FP_CMD_2
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_FC_CTRL
, 1);
628 r300
->hw
.fp
.cmd
[R500_FP_FC_CNTL
] = 0; /* FIXME when we add flow control */
630 ALLOC_STATE(r500fp
, r500fp
, R500_FPI_CMDSIZE
, 0);
631 r300
->hw
.r500fp
.cmd
[R300_FPI_CMD_0
] =
632 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 0, 0);
633 if (r300
->radeon
.radeonScreen
->kernel_mm
)
634 r300
->hw
.r500fp
.emit
= emit_r500fp
;
636 ALLOC_STATE(r500fp_const
, r500fp_const
, R500_FPP_CMDSIZE
, 0);
637 r300
->hw
.r500fp_const
.cmd
[R300_FPI_CMD_0
] =
638 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 1, 0);
639 if (r300
->radeon
.radeonScreen
->kernel_mm
)
640 r300
->hw
.r500fp_const
.emit
= emit_r500fp
;
642 ALLOC_STATE(fp
, always
, R300_FP_CMDSIZE
, 0);
643 r300
->hw
.fp
.cmd
[R300_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CONFIG
, 3);
644 r300
->hw
.fp
.cmd
[R300_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CODE_ADDR_0
, 4);
646 ALLOC_STATE(fpt
, variable
, R300_FPT_CMDSIZE
, 0);
647 r300
->hw
.fpt
.cmd
[R300_FPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_TEX_INST_0
, 0);
649 ALLOC_STATE(fpi
[0], variable
, R300_FPI_CMDSIZE
, 0);
650 r300
->hw
.fpi
[0].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_INST_0
, 1);
651 ALLOC_STATE(fpi
[1], variable
, R300_FPI_CMDSIZE
, 1);
652 r300
->hw
.fpi
[1].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_ADDR_0
, 1);
653 ALLOC_STATE(fpi
[2], variable
, R300_FPI_CMDSIZE
, 2);
654 r300
->hw
.fpi
[2].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_INST_0
, 1);
655 ALLOC_STATE(fpi
[3], variable
, R300_FPI_CMDSIZE
, 3);
656 r300
->hw
.fpi
[3].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_ADDR_0
, 1);
657 ALLOC_STATE(fpp
, variable
, R300_FPP_CMDSIZE
, 0);
658 r300
->hw
.fpp
.cmd
[R300_FPP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_PFS_PARAM_0_X
, 0);
660 ALLOC_STATE(fogs
, always
, R300_FOGS_CMDSIZE
, 0);
661 r300
->hw
.fogs
.cmd
[R300_FOGS_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_BLEND
, 1);
662 ALLOC_STATE(fogc
, always
, R300_FOGC_CMDSIZE
, 0);
663 r300
->hw
.fogc
.cmd
[R300_FOGC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_COLOR_R
, 3);
664 ALLOC_STATE(at
, always
, R300_AT_CMDSIZE
, 0);
665 r300
->hw
.at
.cmd
[R300_AT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_ALPHA_FUNC
, 2);
666 ALLOC_STATE(fg_depth_src
, always
, 2, 0);
667 r300
->hw
.fg_depth_src
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_DEPTH_SRC
, 1);
668 ALLOC_STATE(rb3d_cctl
, always
, 2, 0);
669 r300
->hw
.rb3d_cctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CCTL
, 1);
670 ALLOC_STATE(bld
, always
, R300_BLD_CMDSIZE
, 0);
671 r300
->hw
.bld
.cmd
[R300_BLD_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CBLEND
, 2);
672 ALLOC_STATE(cmk
, always
, R300_CMK_CMDSIZE
, 0);
673 r300
->hw
.cmk
.cmd
[R300_CMK_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, RB3D_COLOR_CHANNEL_MASK
, 1);
675 ALLOC_STATE(blend_color
, always
, 3, 0);
676 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_CONSTANT_COLOR_AR
, 2);
678 ALLOC_STATE(blend_color
, always
, 2, 0);
679 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_BLEND_COLOR
, 1);
681 ALLOC_STATE(rop
, always
, 2, 0);
682 r300
->hw
.rop
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_ROPCNTL
, 1);
683 ALLOC_STATE(cb
, cb_offset
, R300_CB_CMDSIZE
, 0);
684 r300
->hw
.cb
.emit
= &emit_cb_offset
;
685 ALLOC_STATE(rb3d_dither_ctl
, always
, 10, 0);
686 r300
->hw
.rb3d_dither_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_DITHER_CTL
, 9);
687 ALLOC_STATE(rb3d_aaresolve_ctl
, always
, 2, 0);
688 r300
->hw
.rb3d_aaresolve_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_AARESOLVE_CTL
, 1);
689 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV350
) {
690 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold
, always
, 3, 0);
692 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold
, never
, 3, 0);
694 r300
->hw
.rb3d_discard_src_pixel_lte_threshold
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
, 2);
695 ALLOC_STATE(zs
, always
, R300_ZS_CMDSIZE
, 0);
696 r300
->hw
.zs
.cmd
[R300_ZS_CMD_0
] =
697 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_CNTL
, 3);
699 if (r300
->radeon
.radeonScreen
->kernel_mm
)
700 ALLOC_STATE(zsb
, always
, R300_ZSB_CMDSIZE
, 0);
702 ALLOC_STATE(zsb
, never
, R300_ZSB_CMDSIZE
, 0);
703 r300
->hw
.zsb
.cmd
[R300_ZSB_CMD_0
] =
704 cmdpacket0(r300
->radeon
.radeonScreen
, R500_ZB_STENCILREFMASK_BF
, 1);
707 ALLOC_STATE(zstencil_format
, always
, 5, 0);
708 r300
->hw
.zstencil_format
.cmd
[0] =
709 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_FORMAT
, 4);
710 r300
->hw
.zstencil_format
.emit
= emit_zstencil_format
;
712 ALLOC_STATE(zb
, zb_offset
, R300_ZB_CMDSIZE
, 0);
713 r300
->hw
.zb
.emit
= emit_zb_offset
;
714 ALLOC_STATE(zb_depthclearvalue
, always
, 2, 0);
715 r300
->hw
.zb_depthclearvalue
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_DEPTHCLEARVALUE
, 1);
716 ALLOC_STATE(zb_zmask
, always
, 3, 0);
717 r300
->hw
.zb_zmask
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_ZMASK_OFFSET
, 2);
718 ALLOC_STATE(zb_hiz_offset
, always
, 2, 0);
719 r300
->hw
.zb_hiz_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_OFFSET
, 1);
720 ALLOC_STATE(zb_hiz_pitch
, always
, 2, 0);
721 r300
->hw
.zb_hiz_pitch
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_PITCH
, 1);
723 /* VPU only on TCL */
726 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
727 ALLOC_STATE(vap_flush
, always
, 10, 0);
728 /* flush processing vertices */
729 r300
->hw
.vap_flush
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
730 r300
->hw
.vap_flush
.cmd
[1] = 0;
731 r300
->hw
.vap_flush
.cmd
[2] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_DSTCACHE_CTLSTAT
, 1);
732 r300
->hw
.vap_flush
.cmd
[3] = R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
;
733 r300
->hw
.vap_flush
.cmd
[4] = cmdpacket0(r300
->radeon
.radeonScreen
, RADEON_WAIT_UNTIL
, 1);
734 r300
->hw
.vap_flush
.cmd
[5] = RADEON_WAIT_3D_IDLECLEAN
;
735 r300
->hw
.vap_flush
.cmd
[6] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
736 r300
->hw
.vap_flush
.cmd
[7] = 0xffffff;
737 r300
->hw
.vap_flush
.cmd
[8] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_STATE_FLUSH_REG
, 1);
738 r300
->hw
.vap_flush
.cmd
[9] = 0;
740 ALLOC_STATE(vap_flush
, never
, 10, 0);
744 ALLOC_STATE(vpi
, vpu
, R300_VPI_CMDSIZE
, 0);
745 r300
->hw
.vpi
.cmd
[0] =
746 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CODE_START
, 0);
747 if (r300
->radeon
.radeonScreen
->kernel_mm
)
748 r300
->hw
.vpi
.emit
= emit_vpu
;
751 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
752 r300
->hw
.vpp
.cmd
[0] =
753 cmdvpu(r300
->radeon
.radeonScreen
, R500_PVS_CONST_START
, 0);
754 if (r300
->radeon
.radeonScreen
->kernel_mm
)
755 r300
->hw
.vpp
.emit
= emit_vpu
;
757 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
758 r300
->hw
.vps
.cmd
[0] =
759 cmdvpu(r300
->radeon
.radeonScreen
, R500_POINT_VPORT_SCALE_OFFSET
, 1);
760 if (r300
->radeon
.radeonScreen
->kernel_mm
)
761 r300
->hw
.vps
.emit
= emit_vpu
;
763 for (i
= 0; i
< 6; i
++) {
764 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
765 r300
->hw
.vpucp
[i
].cmd
[0] =
766 cmdvpu(r300
->radeon
.radeonScreen
,
767 R500_PVS_UCP_START
+ i
, 1);
768 if (r300
->radeon
.radeonScreen
->kernel_mm
)
769 r300
->hw
.vpucp
[i
].emit
= emit_vpu
;
772 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
773 r300
->hw
.vpp
.cmd
[0] =
774 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CONST_START
, 0);
775 if (r300
->radeon
.radeonScreen
->kernel_mm
)
776 r300
->hw
.vpp
.emit
= emit_vpu
;
778 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
779 r300
->hw
.vps
.cmd
[0] =
780 cmdvpu(r300
->radeon
.radeonScreen
, R300_POINT_VPORT_SCALE_OFFSET
, 1);
781 if (r300
->radeon
.radeonScreen
->kernel_mm
)
782 r300
->hw
.vps
.emit
= emit_vpu
;
784 for (i
= 0; i
< 6; i
++) {
785 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
786 r300
->hw
.vpucp
[i
].cmd
[0] =
787 cmdvpu(r300
->radeon
.radeonScreen
,
788 R300_PVS_UCP_START
+ i
, 1);
789 if (r300
->radeon
.radeonScreen
->kernel_mm
)
790 r300
->hw
.vpucp
[i
].emit
= emit_vpu
;
796 ALLOC_STATE(tex
.filter
, variable
, mtu
+ 1, 0);
797 r300
->hw
.tex
.filter
.cmd
[R300_TEX_CMD_0
] =
798 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER0_0
, 0);
800 ALLOC_STATE(tex
.filter_1
, variable
, mtu
+ 1, 0);
801 r300
->hw
.tex
.filter_1
.cmd
[R300_TEX_CMD_0
] =
802 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER1_0
, 0);
804 ALLOC_STATE(tex
.size
, variable
, mtu
+ 1, 0);
805 r300
->hw
.tex
.size
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_SIZE_0
, 0);
807 ALLOC_STATE(tex
.format
, variable
, mtu
+ 1, 0);
808 r300
->hw
.tex
.format
.cmd
[R300_TEX_CMD_0
] =
809 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT_0
, 0);
811 ALLOC_STATE(tex
.pitch
, variable
, mtu
+ 1, 0);
812 r300
->hw
.tex
.pitch
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT2_0
, 0);
814 ALLOC_STATE(tex
.offset
, tex_offsets
, 1, 0);
815 r300
->hw
.tex
.offset
.cmd
[R300_TEX_CMD_0
] =
816 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_OFFSET_0
, 0);
817 r300
->hw
.tex
.offset
.emit
= &emit_tex_offsets
;
819 ALLOC_STATE(tex
.chroma_key
, variable
, mtu
+ 1, 0);
820 r300
->hw
.tex
.chroma_key
.cmd
[R300_TEX_CMD_0
] =
821 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_CHROMA_KEY_0
, 0);
823 ALLOC_STATE(tex
.border_color
, variable
, mtu
+ 1, 0);
824 r300
->hw
.tex
.border_color
.cmd
[R300_TEX_CMD_0
] =
825 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_BORDER_COLOR_0
, 0);
827 radeon_init_query_stateobj(&r300
->radeon
, R300_QUERYOBJ_CMDSIZE
);
828 if (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV530
) {
829 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, RV530_FG_ZBREG_DEST
, 1);
830 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_0
] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
;
832 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_REG_DEST
, 1);
833 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_0
] = R300_RASTER_PIPE_SELECT_ALL
;
835 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_ZPASS_DATA
, 1);
836 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_1
] = 0;
838 r300
->radeon
.hw
.is_dirty
= GL_TRUE
;
839 r300
->radeon
.hw
.all_dirty
= GL_TRUE
;
841 rcommonInitCmdBuf(&r300
->radeon
);