2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Nicolai Haehnle <prefect_@gmx.net>
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
45 #include "radeon_drm.h"
47 #include "r300_context.h"
48 #include "r300_ioctl.h"
49 #include "radeon_reg.h"
51 #include "r300_cmdbuf.h"
52 #include "r300_emit.h"
53 #include "radeon_bocs_wrapper.h"
54 #include "radeon_mipmap_tree.h"
55 #include "r300_state.h"
56 #include "radeon_reg.h"
57 #include "radeon_queryobj.h"
59 /** # of dwords reserved for additional instructions that may need to be written
62 #define SPACE_FOR_FLUSHING 4
64 static unsigned packet0_count(r300ContextPtr r300
, uint32_t *pkt
)
66 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
67 return ((((*pkt
) >> 16) & 0x3FFF) + 1);
69 drm_r300_cmd_header_t
*t
= (drm_r300_cmd_header_t
*)pkt
;
70 return t
->packet0
.count
;
74 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
75 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
77 void emit_vpu(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
79 r300ContextPtr r300
= R300_CONTEXT(ctx
);
80 BATCH_LOCALS(&r300
->radeon
);
81 drm_r300_cmd_header_t cmd
;
82 uint32_t addr
, ndw
, i
;
84 if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
86 dwords
= (*atom
->check
) (ctx
, atom
);
87 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
88 OUT_BATCH_TABLE(atom
->cmd
, dwords
);
94 addr
= (cmd
.vpu
.adrhi
<< 8) | cmd
.vpu
.adrlo
;
95 ndw
= cmd
.vpu
.count
* 4;
98 if (r300
->vap_flush_needed
) {
99 BEGIN_BATCH_NO_AUTOSTATE(15 + ndw
);
101 /* flush processing vertices */
102 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR
, 0);
103 OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT
, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
104 OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL
, RADEON_WAIT_3D_IDLECLEAN
);
105 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR
, 0xffffff);
106 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
107 r300
->vap_flush_needed
= GL_FALSE
;
109 BEGIN_BATCH_NO_AUTOSTATE(5 + ndw
);
111 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG
, addr
);
112 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA
, ndw
-1) | RADEON_ONE_REG_WR
);
113 for (i
= 0; i
< ndw
; i
++) {
114 OUT_BATCH(atom
->cmd
[i
+1]);
116 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
121 void emit_r500fp(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
123 r300ContextPtr r300
= R300_CONTEXT(ctx
);
124 BATCH_LOCALS(&r300
->radeon
);
125 drm_r300_cmd_header_t cmd
;
126 uint32_t addr
, ndw
, i
, sz
;
127 int type
, clamp
, stride
;
129 if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
131 dwords
= (*atom
->check
) (ctx
, atom
);
132 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
133 OUT_BATCH_TABLE(atom
->cmd
, dwords
);
138 cmd
.u
= atom
->cmd
[0];
139 sz
= cmd
.r500fp
.count
;
140 addr
= ((cmd
.r500fp
.adrhi_flags
& 1) << 8) | cmd
.r500fp
.adrlo
;
141 type
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_TYPE
);
142 clamp
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_CLAMP
);
144 addr
|= (type
<< 16);
145 addr
|= (clamp
<< 17);
147 stride
= type
? 4 : 6;
152 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw
);
153 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX
, 0));
155 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA
, ndw
-1) | RADEON_ONE_REG_WR
);
156 for (i
= 0; i
< ndw
; i
++) {
157 OUT_BATCH(atom
->cmd
[i
+1]);
163 static void emit_tex_offsets(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
165 r300ContextPtr r300
= R300_CONTEXT(ctx
);
166 BATCH_LOCALS(&r300
->radeon
);
167 int numtmus
= packet0_count(r300
, r300
->hw
.tex
.offset
.cmd
);
170 for(i
= 0; i
< numtmus
; ++i
) {
171 radeonTexObj
*t
= r300
->hw
.textures
[i
];
172 if (t
&& !t
->image_override
) {
173 BEGIN_BATCH_NO_AUTOSTATE(4);
174 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
175 OUT_BATCH_RELOC(t
->tile_bits
, t
->mt
->bo
, 0,
176 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
179 /* Texture unit hasn't a texture bound.
180 * We assign the current color buffer as a fakery to make
181 * KIL work on KMS (without it, the CS checker will complain).
183 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
184 struct radeon_renderbuffer
*rrb
= radeon_get_colorbuffer(&r300
->radeon
);
185 if (rrb
&& rrb
->bo
) {
186 BEGIN_BATCH_NO_AUTOSTATE(4);
187 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
188 OUT_BATCH_RELOC(0, rrb
->bo
, 0,
189 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
193 } else { /* override cases */
195 BEGIN_BATCH_NO_AUTOSTATE(4);
196 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
197 OUT_BATCH_RELOC(t
->tile_bits
, t
->bo
, 0,
198 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
200 } else if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
201 BEGIN_BATCH_NO_AUTOSTATE(2);
202 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
203 OUT_BATCH(t
->override_offset
);
206 /* Texture unit hasn't a texture bound nothings to do */
212 void r300_emit_scissor(GLcontext
*ctx
)
214 r300ContextPtr r300
= R300_CONTEXT(ctx
);
215 BATCH_LOCALS(&r300
->radeon
);
216 unsigned x1
, y1
, x2
, y2
;
217 struct radeon_renderbuffer
*rrb
;
219 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
222 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
223 if (!rrb
|| !rrb
->bo
) {
224 fprintf(stderr
, "no rrb\n");
227 if (r300
->radeon
.state
.scissor
.enabled
) {
228 x1
= r300
->radeon
.state
.scissor
.rect
.x1
;
229 y1
= r300
->radeon
.state
.scissor
.rect
.y1
;
230 x2
= r300
->radeon
.state
.scissor
.rect
.x2
- 1;
231 y2
= r300
->radeon
.state
.scissor
.rect
.y2
- 1;
235 x2
= rrb
->base
.Width
- 1;
236 y2
= rrb
->base
.Height
- 1;
238 if (r300
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV515
) {
239 x1
+= R300_SCISSORS_OFFSET
;
240 y1
+= R300_SCISSORS_OFFSET
;
241 x2
+= R300_SCISSORS_OFFSET
;
242 y2
+= R300_SCISSORS_OFFSET
;
244 BEGIN_BATCH_NO_AUTOSTATE(3);
245 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
246 OUT_BATCH((x1
<< R300_SCISSORS_X_SHIFT
)|(y1
<< R300_SCISSORS_Y_SHIFT
));
247 OUT_BATCH((x2
<< R300_SCISSORS_X_SHIFT
)|(y2
<< R300_SCISSORS_Y_SHIFT
));
251 static void emit_cb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
253 r300ContextPtr r300
= R300_CONTEXT(ctx
);
254 BATCH_LOCALS(&r300
->radeon
);
255 struct radeon_renderbuffer
*rrb
;
257 uint32_t offset
= r300
->radeon
.state
.color
.draw_offset
;
261 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
262 if (!rrb
|| !rrb
->bo
) {
263 fprintf(stderr
, "no rrb\n");
267 if (RADEON_DEBUG
& DEBUG_STATE
)
268 fprintf(stderr
,"rrb is %p %d %dx%d\n", rrb
, offset
, rrb
->base
.Width
, rrb
->base
.Height
);
269 cbpitch
= (rrb
->pitch
/ rrb
->cpp
);
271 cbpitch
|= R300_COLOR_FORMAT_ARGB8888
;
272 else switch (rrb
->base
._ActualFormat
) {
274 cbpitch
|= R300_COLOR_FORMAT_RGB565
;
277 cbpitch
|= R300_COLOR_FORMAT_ARGB4444
;
280 cbpitch
|= R300_COLOR_FORMAT_ARGB1555
;
284 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
285 cbpitch
|= R300_COLOR_TILE_ENABLE
;
287 if (r300
->radeon
.radeonScreen
->kernel_mm
)
289 BEGIN_BATCH_NO_AUTOSTATE(dw
);
290 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0
, 1);
291 OUT_BATCH_RELOC(offset
, rrb
->bo
, offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
292 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0
, 1);
293 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
296 OUT_BATCH_RELOC(cbpitch
, rrb
->bo
, cbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
298 if (r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
299 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
) {
300 BEGIN_BATCH_NO_AUTOSTATE(3);
301 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
303 OUT_BATCH(((rrb
->base
.Width
- 1) << R300_SCISSORS_X_SHIFT
) |
304 ((rrb
->base
.Height
- 1) << R300_SCISSORS_Y_SHIFT
));
306 BEGIN_BATCH_NO_AUTOSTATE(16);
307 for (i
= 0; i
< 4; i
++) {
308 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0
+ (i
* 8), 2);
309 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT
) | (0 << R300_CLIPRECT_Y_SHIFT
));
310 OUT_BATCH(((rrb
->base
.Width
- 1) << R300_CLIPRECT_X_SHIFT
) | ((rrb
->base
.Height
- 1) << R300_CLIPRECT_Y_SHIFT
));
312 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE
, 1);
314 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR
, 1);
318 BEGIN_BATCH_NO_AUTOSTATE(3);
319 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
320 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_SCISSORS_X_SHIFT
) |
321 (R300_SCISSORS_OFFSET
<< R300_SCISSORS_Y_SHIFT
));
322 OUT_BATCH(((rrb
->base
.Width
+ R300_SCISSORS_OFFSET
- 1) << R300_SCISSORS_X_SHIFT
) |
323 ((rrb
->base
.Height
+ R300_SCISSORS_OFFSET
- 1) << R300_SCISSORS_Y_SHIFT
));
325 BEGIN_BATCH_NO_AUTOSTATE(16);
326 for (i
= 0; i
< 4; i
++) {
327 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0
+ (i
* 8), 2);
328 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_CLIPRECT_X_SHIFT
) | (R300_SCISSORS_OFFSET
<< R300_CLIPRECT_Y_SHIFT
));
329 OUT_BATCH(((R300_SCISSORS_OFFSET
+ rrb
->base
.Width
- 1) << R300_CLIPRECT_X_SHIFT
) |
330 ((R300_SCISSORS_OFFSET
+ rrb
->base
.Height
- 1) << R300_CLIPRECT_Y_SHIFT
));
332 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE
, 1);
334 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR
, 1);
341 static void emit_zb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
343 r300ContextPtr r300
= R300_CONTEXT(ctx
);
344 BATCH_LOCALS(&r300
->radeon
);
345 struct radeon_renderbuffer
*rrb
;
349 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
353 zbpitch
= (rrb
->pitch
/ rrb
->cpp
);
354 if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
355 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
356 zbpitch
|= R300_DEPTHMACROTILE_ENABLE
;
358 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
){
359 zbpitch
|= R300_DEPTHMICROTILE_TILED
;
364 if (r300
->radeon
.radeonScreen
->kernel_mm
)
366 BEGIN_BATCH_NO_AUTOSTATE(dw
);
367 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET
, 1);
368 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
369 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH
, 1);
370 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
373 OUT_BATCH_RELOC(cbpitch
, rrb
->bo
, zbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
377 static void emit_gb_misc(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
379 r300ContextPtr r300
= R300_CONTEXT(ctx
);
380 BATCH_LOCALS(&r300
->radeon
);
381 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
382 BEGIN_BATCH_NO_AUTOSTATE(4);
383 OUT_BATCH(atom
->cmd
[0]);
384 OUT_BATCH(atom
->cmd
[1]);
385 OUT_BATCH(atom
->cmd
[2]);
386 OUT_BATCH(atom
->cmd
[3]);
391 static void emit_threshold_misc(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
393 r300ContextPtr r300
= R300_CONTEXT(ctx
);
394 BATCH_LOCALS(&r300
->radeon
);
395 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
) {
396 BEGIN_BATCH_NO_AUTOSTATE(3);
397 OUT_BATCH(atom
->cmd
[0]);
398 OUT_BATCH(atom
->cmd
[1]);
399 OUT_BATCH(atom
->cmd
[2]);
404 static void emit_shade_misc(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
406 r300ContextPtr r300
= R300_CONTEXT(ctx
);
407 BATCH_LOCALS(&r300
->radeon
);
409 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
410 BEGIN_BATCH_NO_AUTOSTATE(2);
411 OUT_BATCH(atom
->cmd
[0]);
412 OUT_BATCH(atom
->cmd
[1]);
417 static void emit_zstencil_format(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
419 r300ContextPtr r300
= R300_CONTEXT(ctx
);
420 BATCH_LOCALS(&r300
->radeon
);
421 struct radeon_renderbuffer
*rrb
;
424 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
429 format
= R300_DEPTHFORMAT_16BIT_INT_Z
;
430 else if (rrb
->cpp
== 4)
431 format
= R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL
;
434 BEGIN_BATCH_NO_AUTOSTATE(5);
435 OUT_BATCH(atom
->cmd
[0]);
436 atom
->cmd
[1] &= ~0xf;
437 atom
->cmd
[1] |= format
;
438 OUT_BATCH(atom
->cmd
[1]);
439 OUT_BATCH(atom
->cmd
[2]);
440 OUT_BATCH(atom
->cmd
[3]);
441 OUT_BATCH(atom
->cmd
[4]);
445 static int check_always(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
447 return atom
->cmd_size
;
450 static int check_variable(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
452 r300ContextPtr r300
= R300_CONTEXT(ctx
);
454 if (atom
->cmd
[0] == CP_PACKET2
) {
457 cnt
= packet0_count(r300
, atom
->cmd
);
458 return cnt
? cnt
+ 1 : 0;
461 int check_vpu(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
465 cnt
= vpu_count(atom
->cmd
);
466 return cnt
? (cnt
* 4) + 1 : 0;
469 int check_r500fp(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
473 cnt
= r500fp_count(atom
->cmd
);
474 return cnt
? (cnt
* 6) + 1 : 0;
477 int check_r500fp_const(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
481 cnt
= r500fp_count(atom
->cmd
);
482 return cnt
? (cnt
* 4) + 1 : 0;
485 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
487 r300->hw.ATOM.cmd_size = (SZ); \
488 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
489 r300->hw.ATOM.name = #ATOM; \
490 r300->hw.ATOM.idx = (IDX); \
491 r300->hw.ATOM.check = check_##CHK; \
492 r300->hw.ATOM.dirty = GL_FALSE; \
493 r300->radeon.hw.max_state_size += (SZ); \
494 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
497 * Allocate memory for the command buffer and initialize the state atom
498 * list. Note that the initial hardware state is set by r300InitState().
500 void r300InitCmdBuf(r300ContextPtr r300
)
506 has_tcl
= r300
->options
.hw_tcl_enabled
;
508 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
511 r300
->radeon
.hw
.max_state_size
= 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
513 mtu
= r300
->radeon
.glCtx
->Const
.MaxTextureUnits
;
514 if (RADEON_DEBUG
& DEBUG_TEXTURE
) {
515 fprintf(stderr
, "Using %d maximum texture units..\n", mtu
);
518 /* Setup the atom linked list */
519 make_empty_list(&r300
->radeon
.hw
.atomlist
);
520 r300
->radeon
.hw
.atomlist
.name
= "atom-list";
522 /* Initialize state atoms */
523 ALLOC_STATE(vpt
, always
, R300_VPT_CMDSIZE
, 0);
524 r300
->hw
.vpt
.cmd
[R300_VPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VPORT_XSCALE
, 6);
525 ALLOC_STATE(vap_cntl
, always
, R300_VAP_CNTL_SIZE
, 0);
526 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_STATE_FLUSH_REG
, 1);
527 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH_1
] = 0;
528 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_CMD
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL
, 1);
529 if (is_r500
&& !r300
->radeon
.radeonScreen
->kernel_mm
) {
530 ALLOC_STATE(vap_index_offset
, always
, 2, 0);
531 r300
->hw
.vap_index_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_VAP_INDEX_OFFSET
, 1);
532 r300
->hw
.vap_index_offset
.cmd
[1] = 0;
534 ALLOC_STATE(vte
, always
, 3, 0);
535 r300
->hw
.vte
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VTE_CNTL
, 2);
536 ALLOC_STATE(vap_vf_max_vtx_indx
, always
, 3, 0);
537 r300
->hw
.vap_vf_max_vtx_indx
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VF_MAX_VTX_INDX
, 2);
538 ALLOC_STATE(vap_cntl_status
, always
, 2, 0);
539 r300
->hw
.vap_cntl_status
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL_STATUS
, 1);
540 ALLOC_STATE(vir
[0], variable
, R300_VIR_CMDSIZE
, 0);
541 r300
->hw
.vir
[0].cmd
[R300_VIR_CMD_0
] =
542 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_0
, 1);
543 ALLOC_STATE(vir
[1], variable
, R300_VIR_CMDSIZE
, 1);
544 r300
->hw
.vir
[1].cmd
[R300_VIR_CMD_0
] =
545 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_EXT_0
, 1);
546 ALLOC_STATE(vic
, always
, R300_VIC_CMDSIZE
, 0);
547 r300
->hw
.vic
.cmd
[R300_VIC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VTX_STATE_CNTL
, 2);
548 ALLOC_STATE(vap_psc_sgn_norm_cntl
, always
, 2, 0);
549 r300
->hw
.vap_psc_sgn_norm_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PSC_SGN_NORM_CNTL
, SGN_NORM_ZERO_CLAMP_MINUS_ONE
);
552 ALLOC_STATE(vap_clip_cntl
, always
, 2, 0);
553 r300
->hw
.vap_clip_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CLIP_CNTL
, 1);
554 ALLOC_STATE(vap_clip
, always
, 5, 0);
555 r300
->hw
.vap_clip
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_GB_VERT_CLIP_ADJ
, 4);
556 ALLOC_STATE(vap_pvs_vtx_timeout_reg
, always
, 2, 0);
557 r300
->hw
.vap_pvs_vtx_timeout_reg
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, VAP_PVS_VTX_TIMEOUT_REG
, 1);
560 ALLOC_STATE(vof
, always
, R300_VOF_CMDSIZE
, 0);
561 r300
->hw
.vof
.cmd
[R300_VOF_CMD_0
] =
562 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_OUTPUT_VTX_FMT_0
, 2);
565 ALLOC_STATE(pvs
, always
, R300_PVS_CMDSIZE
, 0);
566 r300
->hw
.pvs
.cmd
[R300_PVS_CMD_0
] =
567 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_CODE_CNTL_0
, 3);
570 ALLOC_STATE(gb_enable
, always
, 2, 0);
571 r300
->hw
.gb_enable
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_ENABLE
, 1);
572 ALLOC_STATE(gb_misc
, always
, R300_GB_MISC_CMDSIZE
, 0);
573 r300
->hw
.gb_misc
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_MSPOS0
, 3);
574 r300
->hw
.gb_misc
.emit
= emit_gb_misc
;
575 ALLOC_STATE(gb_misc2
, always
, R300_GB_MISC2_CMDSIZE
, 0);
576 r300
->hw
.gb_misc2
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x401C, 2);
577 ALLOC_STATE(txe
, always
, R300_TXE_CMDSIZE
, 0);
578 r300
->hw
.txe
.cmd
[R300_TXE_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_ENABLE
, 1);
579 ALLOC_STATE(ga_point_s0
, always
, 5, 0);
580 r300
->hw
.ga_point_s0
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_S0
, 4);
581 ALLOC_STATE(ga_triangle_stipple
, always
, 2, 0);
582 r300
->hw
.ga_triangle_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_TRIANGLE_STIPPLE
, 1);
583 ALLOC_STATE(ps
, always
, R300_PS_CMDSIZE
, 0);
584 r300
->hw
.ps
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_SIZE
, 1);
585 ALLOC_STATE(ga_point_minmax
, always
, 4, 0);
586 r300
->hw
.ga_point_minmax
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_MINMAX
, 3);
587 ALLOC_STATE(lcntl
, always
, 2, 0);
588 r300
->hw
.lcntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_CNTL
, 1);
589 ALLOC_STATE(ga_line_stipple
, always
, 4, 0);
590 r300
->hw
.ga_line_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_STIPPLE_VALUE
, 3);
591 ALLOC_STATE(shade
, always
, 2, 0);
592 r300
->hw
.shade
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_ENHANCE
, 1);
593 r300
->hw
.shade
.emit
= emit_shade_misc
;
594 ALLOC_STATE(shade2
, always
, 4, 0);
595 r300
->hw
.shade2
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x4278, 3);
596 ALLOC_STATE(polygon_mode
, always
, 4, 0);
597 r300
->hw
.polygon_mode
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POLY_MODE
, 3);
598 ALLOC_STATE(fogp
, always
, 3, 0);
599 r300
->hw
.fogp
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_FOG_SCALE
, 2);
600 ALLOC_STATE(zbias_cntl
, always
, 2, 0);
601 r300
->hw
.zbias_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_TEX_WRAP
, 1);
602 ALLOC_STATE(zbs
, always
, R300_ZBS_CMDSIZE
, 0);
603 r300
->hw
.zbs
.cmd
[R300_ZBS_CMD_0
] =
604 cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
605 ALLOC_STATE(occlusion_cntl
, always
, 2, 0);
606 r300
->hw
.occlusion_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_ENABLE
, 1);
607 ALLOC_STATE(cul
, always
, R300_CUL_CMDSIZE
, 0);
608 r300
->hw
.cul
.cmd
[R300_CUL_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_CULL_MODE
, 1);
609 ALLOC_STATE(su_depth_scale
, always
, 3, 0);
610 r300
->hw
.su_depth_scale
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_DEPTH_SCALE
, 2);
611 ALLOC_STATE(rc
, always
, R300_RC_CMDSIZE
, 0);
612 r300
->hw
.rc
.cmd
[R300_RC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_COUNT
, 2);
614 ALLOC_STATE(ri
, variable
, R500_RI_CMDSIZE
, 0);
615 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_IP_0
, 16);
616 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
617 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_INST_0
, 1);
619 ALLOC_STATE(ri
, variable
, R300_RI_CMDSIZE
, 0);
620 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_IP_0
, 8);
621 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
622 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_INST_0
, 1);
624 ALLOC_STATE(sc_hyperz
, always
, 3, 0);
625 r300
->hw
.sc_hyperz
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_HYPERZ
, 2);
626 ALLOC_STATE(sc_screendoor
, always
, 2, 0);
627 r300
->hw
.sc_screendoor
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
628 ALLOC_STATE(us_out_fmt
, always
, 6, 0);
629 r300
->hw
.us_out_fmt
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_OUT_FMT
, 5);
632 ALLOC_STATE(fp
, always
, R500_FP_CMDSIZE
, 0);
633 r300
->hw
.fp
.cmd
[R500_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CONFIG
, 2);
634 r300
->hw
.fp
.cmd
[R500_FP_CNTL
] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
;
635 r300
->hw
.fp
.cmd
[R500_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CODE_ADDR
, 3);
636 r300
->hw
.fp
.cmd
[R500_FP_CMD_2
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_FC_CTRL
, 1);
637 r300
->hw
.fp
.cmd
[R500_FP_FC_CNTL
] = 0; /* FIXME when we add flow control */
639 ALLOC_STATE(r500fp
, r500fp
, R500_FPI_CMDSIZE
, 0);
640 r300
->hw
.r500fp
.cmd
[R300_FPI_CMD_0
] =
641 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 0, 0);
642 r300
->hw
.r500fp
.emit
= emit_r500fp
;
643 ALLOC_STATE(r500fp_const
, r500fp_const
, R500_FPP_CMDSIZE
, 0);
644 r300
->hw
.r500fp_const
.cmd
[R300_FPI_CMD_0
] =
645 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 1, 0);
646 r300
->hw
.r500fp_const
.emit
= emit_r500fp
;
648 ALLOC_STATE(fp
, always
, R300_FP_CMDSIZE
, 0);
649 r300
->hw
.fp
.cmd
[R300_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CONFIG
, 3);
650 r300
->hw
.fp
.cmd
[R300_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CODE_ADDR_0
, 4);
652 ALLOC_STATE(fpt
, variable
, R300_FPT_CMDSIZE
, 0);
653 r300
->hw
.fpt
.cmd
[R300_FPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_TEX_INST_0
, 0);
655 ALLOC_STATE(fpi
[0], variable
, R300_FPI_CMDSIZE
, 0);
656 r300
->hw
.fpi
[0].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_INST_0
, 1);
657 ALLOC_STATE(fpi
[1], variable
, R300_FPI_CMDSIZE
, 1);
658 r300
->hw
.fpi
[1].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_ADDR_0
, 1);
659 ALLOC_STATE(fpi
[2], variable
, R300_FPI_CMDSIZE
, 2);
660 r300
->hw
.fpi
[2].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_INST_0
, 1);
661 ALLOC_STATE(fpi
[3], variable
, R300_FPI_CMDSIZE
, 3);
662 r300
->hw
.fpi
[3].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_ADDR_0
, 1);
663 ALLOC_STATE(fpp
, variable
, R300_FPP_CMDSIZE
, 0);
664 r300
->hw
.fpp
.cmd
[R300_FPP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_PFS_PARAM_0_X
, 0);
666 ALLOC_STATE(fogs
, always
, R300_FOGS_CMDSIZE
, 0);
667 r300
->hw
.fogs
.cmd
[R300_FOGS_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_BLEND
, 1);
668 ALLOC_STATE(fogc
, always
, R300_FOGC_CMDSIZE
, 0);
669 r300
->hw
.fogc
.cmd
[R300_FOGC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_COLOR_R
, 3);
670 ALLOC_STATE(at
, always
, R300_AT_CMDSIZE
, 0);
671 r300
->hw
.at
.cmd
[R300_AT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_ALPHA_FUNC
, 2);
672 ALLOC_STATE(fg_depth_src
, always
, 2, 0);
673 r300
->hw
.fg_depth_src
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_DEPTH_SRC
, 1);
674 ALLOC_STATE(rb3d_cctl
, always
, 2, 0);
675 r300
->hw
.rb3d_cctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CCTL
, 1);
676 ALLOC_STATE(bld
, always
, R300_BLD_CMDSIZE
, 0);
677 r300
->hw
.bld
.cmd
[R300_BLD_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CBLEND
, 2);
678 ALLOC_STATE(cmk
, always
, R300_CMK_CMDSIZE
, 0);
679 r300
->hw
.cmk
.cmd
[R300_CMK_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, RB3D_COLOR_CHANNEL_MASK
, 1);
681 ALLOC_STATE(blend_color
, always
, 3, 0);
682 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_CONSTANT_COLOR_AR
, 2);
684 ALLOC_STATE(blend_color
, always
, 2, 0);
685 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_BLEND_COLOR
, 1);
687 ALLOC_STATE(rop
, always
, 2, 0);
688 r300
->hw
.rop
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_ROPCNTL
, 1);
689 ALLOC_STATE(cb
, always
, R300_CB_CMDSIZE
, 0);
690 r300
->hw
.cb
.emit
= &emit_cb_offset
;
691 ALLOC_STATE(rb3d_dither_ctl
, always
, 10, 0);
692 r300
->hw
.rb3d_dither_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_DITHER_CTL
, 9);
693 ALLOC_STATE(rb3d_aaresolve_ctl
, always
, 2, 0);
694 r300
->hw
.rb3d_aaresolve_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_AARESOLVE_CTL
, 1);
695 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold
, always
, 3, 0);
696 r300
->hw
.rb3d_discard_src_pixel_lte_threshold
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
, 2);
697 r300
->hw
.rb3d_discard_src_pixel_lte_threshold
.emit
= emit_threshold_misc
;
698 ALLOC_STATE(zs
, always
, R300_ZS_CMDSIZE
, 0);
699 r300
->hw
.zs
.cmd
[R300_ZS_CMD_0
] =
700 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_CNTL
, 3);
702 ALLOC_STATE(zstencil_format
, always
, 5, 0);
703 r300
->hw
.zstencil_format
.cmd
[0] =
704 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_FORMAT
, 4);
705 r300
->hw
.zstencil_format
.emit
= emit_zstencil_format
;
707 ALLOC_STATE(zb
, always
, R300_ZB_CMDSIZE
, 0);
708 r300
->hw
.zb
.emit
= emit_zb_offset
;
709 ALLOC_STATE(zb_depthclearvalue
, always
, 2, 0);
710 r300
->hw
.zb_depthclearvalue
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_DEPTHCLEARVALUE
, 1);
711 ALLOC_STATE(zb_zmask
, always
, 3, 0);
712 r300
->hw
.zb_zmask
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_ZMASK_OFFSET
, 2);
713 ALLOC_STATE(zb_hiz_offset
, always
, 2, 0);
714 r300
->hw
.zb_hiz_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_OFFSET
, 1);
715 ALLOC_STATE(zb_hiz_pitch
, always
, 2, 0);
716 r300
->hw
.zb_hiz_pitch
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_PITCH
, 1);
718 /* VPU only on TCL */
721 ALLOC_STATE(vpi
, vpu
, R300_VPI_CMDSIZE
, 0);
722 r300
->hw
.vpi
.cmd
[0] =
723 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CODE_START
, 0);
724 r300
->hw
.vpi
.emit
= emit_vpu
;
727 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
728 r300
->hw
.vpp
.cmd
[0] =
729 cmdvpu(r300
->radeon
.radeonScreen
, R500_PVS_CONST_START
, 0);
730 r300
->hw
.vpp
.emit
= emit_vpu
;
732 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
733 r300
->hw
.vps
.cmd
[0] =
734 cmdvpu(r300
->radeon
.radeonScreen
, R500_POINT_VPORT_SCALE_OFFSET
, 1);
735 r300
->hw
.vps
.emit
= emit_vpu
;
737 for (i
= 0; i
< 6; i
++) {
738 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
739 r300
->hw
.vpucp
[i
].cmd
[0] =
740 cmdvpu(r300
->radeon
.radeonScreen
,
741 R500_PVS_UCP_START
+ i
, 1);
742 r300
->hw
.vpucp
[i
].emit
= emit_vpu
;
745 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
746 r300
->hw
.vpp
.cmd
[0] =
747 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CONST_START
, 0);
748 r300
->hw
.vpp
.emit
= emit_vpu
;
750 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
751 r300
->hw
.vps
.cmd
[0] =
752 cmdvpu(r300
->radeon
.radeonScreen
, R300_POINT_VPORT_SCALE_OFFSET
, 1);
753 r300
->hw
.vps
.emit
= emit_vpu
;
755 for (i
= 0; i
< 6; i
++) {
756 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
757 r300
->hw
.vpucp
[i
].cmd
[0] =
758 cmdvpu(r300
->radeon
.radeonScreen
,
759 R300_PVS_UCP_START
+ i
, 1);
760 r300
->hw
.vpucp
[i
].emit
= emit_vpu
;
766 ALLOC_STATE(tex
.filter
, variable
, mtu
+ 1, 0);
767 r300
->hw
.tex
.filter
.cmd
[R300_TEX_CMD_0
] =
768 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER0_0
, 0);
770 ALLOC_STATE(tex
.filter_1
, variable
, mtu
+ 1, 0);
771 r300
->hw
.tex
.filter_1
.cmd
[R300_TEX_CMD_0
] =
772 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER1_0
, 0);
774 ALLOC_STATE(tex
.size
, variable
, mtu
+ 1, 0);
775 r300
->hw
.tex
.size
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_SIZE_0
, 0);
777 ALLOC_STATE(tex
.format
, variable
, mtu
+ 1, 0);
778 r300
->hw
.tex
.format
.cmd
[R300_TEX_CMD_0
] =
779 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT_0
, 0);
781 ALLOC_STATE(tex
.pitch
, variable
, mtu
+ 1, 0);
782 r300
->hw
.tex
.pitch
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT2_0
, 0);
784 ALLOC_STATE(tex
.offset
, variable
, 1, 0);
785 r300
->hw
.tex
.offset
.cmd
[R300_TEX_CMD_0
] =
786 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_OFFSET_0
, 0);
787 r300
->hw
.tex
.offset
.emit
= &emit_tex_offsets
;
789 ALLOC_STATE(tex
.chroma_key
, variable
, mtu
+ 1, 0);
790 r300
->hw
.tex
.chroma_key
.cmd
[R300_TEX_CMD_0
] =
791 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_CHROMA_KEY_0
, 0);
793 ALLOC_STATE(tex
.border_color
, variable
, mtu
+ 1, 0);
794 r300
->hw
.tex
.border_color
.cmd
[R300_TEX_CMD_0
] =
795 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_BORDER_COLOR_0
, 0);
797 radeon_init_query_stateobj(&r300
->radeon
, R300_QUERYOBJ_CMDSIZE
);
798 if (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV530
) {
799 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, RV530_FG_ZBREG_DEST
, 1);
800 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_0
] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
;
802 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_REG_DEST
, 1);
803 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_0
] = R300_RASTER_PIPE_SELECT_ALL
;
805 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_ZPASS_DATA
, 1);
806 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_1
] = 0;
808 r300
->radeon
.hw
.is_dirty
= GL_TRUE
;
809 r300
->radeon
.hw
.all_dirty
= GL_TRUE
;
811 rcommonInitCmdBuf(&r300
->radeon
);