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r300: refactor R500 fragment program emission
[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Nicolai Haehnle <prefect_@gmx.net>
34 */
35
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
43
44 #include "drm.h"
45 #include "radeon_drm.h"
46
47 #include "r300_context.h"
48 #include "r300_reg.h"
49 #include "r300_cmdbuf.h"
50 #include "r300_emit.h"
51 #include "radeon_bocs_wrapper.h"
52 #include "radeon_mipmap_tree.h"
53 #include "r300_state.h"
54 #include "radeon_queryobj.h"
55
56 /** # of dwords reserved for additional instructions that may need to be written
57 * during flushing.
58 */
59 #define SPACE_FOR_FLUSHING 4
60
61 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
62 {
63 if (r300->radeon.radeonScreen->kernel_mm) {
64 return ((((*pkt) >> 16) & 0x3FFF) + 1);
65 } else {
66 drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
67 return t->packet0.count;
68 }
69 }
70
71 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
72 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
73
74 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
75 {
76 r300ContextPtr r300 = R300_CONTEXT(ctx);
77 int cnt;
78 int extra = 1;
79 cnt = vpu_count(atom->cmd);
80
81 if (r300->radeon.radeonScreen->kernel_mm) {
82 extra = 5;
83 }
84
85 return cnt ? (cnt * 4) + extra : 0;
86 }
87
88
89 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
90 {
91 r300ContextPtr r300 = R300_CONTEXT(ctx);
92 BATCH_LOCALS(&r300->radeon);
93 drm_r300_cmd_header_t cmd;
94 uint32_t addr, ndw;
95
96 cmd.u = atom->cmd[0];
97 addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
98 ndw = atom->check(ctx, atom);
99
100 BEGIN_BATCH_NO_AUTOSTATE(ndw);
101
102 ndw -= 5;
103 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
104 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
105 OUT_BATCH_TABLE(&atom->cmd[1], ndw);
106 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
107 END_BATCH();
108 }
109
110 void r500_emit_fp(struct r300_context *r300,
111 uint32_t *data,
112 unsigned len,
113 uint32_t addr,
114 unsigned type,
115 unsigned clamp)
116 {
117 BATCH_LOCALS(&r300->radeon);
118
119 addr |= (type << 16);
120 addr |= (clamp << 17);
121
122 BEGIN_BATCH_NO_AUTOSTATE(len + 3);
123 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
124 OUT_BATCH(addr);
125 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, len-1) | RADEON_ONE_REG_WR);
126 OUT_BATCH_TABLE(data, len);
127 END_BATCH();
128 }
129
130 static void emit_r500fp_atom(GLcontext *ctx, struct radeon_state_atom * atom)
131 {
132 r300ContextPtr r300 = R300_CONTEXT(ctx);
133 drm_r300_cmd_header_t cmd;
134 uint32_t addr, count;
135 int type, clamp;
136
137 cmd.u = atom->cmd[0];
138 addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
139 type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
140 clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
141
142 if (type) {
143 count = r500fp_count(atom->cmd) * 4;
144 } else {
145 count = r500fp_count(atom->cmd) * 6;
146 }
147
148 r500_emit_fp(r300, &atom->cmd[1], count, addr, type, clamp);
149 }
150
151 static int check_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
152 {
153 r300ContextPtr r300 = R300_CONTEXT(ctx);
154 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
155 int dw = 0, i;
156 if (atom->cmd[0] == CP_PACKET2) {
157 return dw;
158 }
159 for(i = 0; i < numtmus; ++i) {
160 radeonTexObj *t = r300->hw.textures[i];
161 if (!t && !r300->radeon.radeonScreen->kernel_mm) {
162 dw += 0;
163 } else if (t && t->image_override && !t->bo) {
164 if (!r300->radeon.radeonScreen->kernel_mm)
165 dw += 2;
166 } else
167 dw += 4;
168 }
169 return dw;
170 }
171
172 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
173 {
174 r300ContextPtr r300 = R300_CONTEXT(ctx);
175 BATCH_LOCALS(&r300->radeon);
176 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
177 int i;
178
179 for(i = 0; i < numtmus; ++i) {
180 radeonTexObj *t = r300->hw.textures[i];
181 if (t && !t->image_override) {
182 BEGIN_BATCH_NO_AUTOSTATE(4);
183 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
184 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
185 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
186 END_BATCH();
187 } else if (!t) {
188 /* Texture unit hasn't a texture bound.
189 * We assign the current color buffer as a fakery to make
190 * KIL work on KMS (without it, the CS checker will complain).
191 */
192 if (r300->radeon.radeonScreen->kernel_mm) {
193 struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
194 if (rrb && rrb->bo) {
195 BEGIN_BATCH_NO_AUTOSTATE(4);
196 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
197 OUT_BATCH_RELOC(0, rrb->bo, 0,
198 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
199 END_BATCH();
200 }
201 }
202 } else { /* override cases */
203 if (t->bo) {
204 BEGIN_BATCH_NO_AUTOSTATE(4);
205 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
206 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
207 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
208 END_BATCH();
209 } else if (!r300->radeon.radeonScreen->kernel_mm) {
210 BEGIN_BATCH_NO_AUTOSTATE(2);
211 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
212 OUT_BATCH(t->override_offset);
213 END_BATCH();
214 } else {
215 /* Texture unit hasn't a texture bound nothings to do */
216 }
217 }
218 }
219 }
220
221 void r300_emit_scissor(GLcontext *ctx)
222 {
223 r300ContextPtr r300 = R300_CONTEXT(ctx);
224 BATCH_LOCALS(&r300->radeon);
225 unsigned x1, y1, x2, y2;
226 struct radeon_renderbuffer *rrb;
227
228 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
229 return;
230 }
231 rrb = radeon_get_colorbuffer(&r300->radeon);
232 if (!rrb || !rrb->bo) {
233 fprintf(stderr, "no rrb\n");
234 return;
235 }
236 if (r300->radeon.state.scissor.enabled) {
237 x1 = r300->radeon.state.scissor.rect.x1;
238 y1 = r300->radeon.state.scissor.rect.y1;
239 x2 = r300->radeon.state.scissor.rect.x2;
240 y2 = r300->radeon.state.scissor.rect.y2;
241 } else {
242 x1 = 0;
243 y1 = 0;
244 x2 = rrb->base.Width - 1;
245 y2 = rrb->base.Height - 1;
246 }
247 if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
248 x1 += R300_SCISSORS_OFFSET;
249 y1 += R300_SCISSORS_OFFSET;
250 x2 += R300_SCISSORS_OFFSET;
251 y2 += R300_SCISSORS_OFFSET;
252 }
253 BEGIN_BATCH_NO_AUTOSTATE(3);
254 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
255 OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
256 OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
257 END_BATCH();
258 }
259 static int check_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
260 {
261 r300ContextPtr r300 = R300_CONTEXT(ctx);
262 uint32_t dw = 6 + 3 + 16;
263 if (r300->radeon.radeonScreen->kernel_mm)
264 dw += 2;
265 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
266 dw -= 3 + 16;
267 }
268 return dw;
269 }
270
271 static void emit_scissor(struct r300_context *r300,
272 unsigned width,
273 unsigned height)
274 {
275 int i;
276 BATCH_LOCALS(&r300->radeon);
277 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
278 BEGIN_BATCH_NO_AUTOSTATE(3);
279 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
280 OUT_BATCH(0);
281 OUT_BATCH(((width - 1) << R300_SCISSORS_X_SHIFT) |
282 ((height - 1) << R300_SCISSORS_Y_SHIFT));
283 END_BATCH();
284 BEGIN_BATCH_NO_AUTOSTATE(16);
285 for (i = 0; i < 4; i++) {
286 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
287 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
288 OUT_BATCH(((width - 1) << R300_CLIPRECT_X_SHIFT) | ((height - 1) << R300_CLIPRECT_Y_SHIFT));
289 }
290 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
291 OUT_BATCH(0xAAAA);
292 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
293 OUT_BATCH(0xffffff);
294 END_BATCH();
295 } else {
296 BEGIN_BATCH_NO_AUTOSTATE(3);
297 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
298 OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
299 (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
300 OUT_BATCH(((width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
301 ((height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
302 END_BATCH();
303 BEGIN_BATCH_NO_AUTOSTATE(16);
304 for (i = 0; i < 4; i++) {
305 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
306 OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
307 OUT_BATCH(((R300_SCISSORS_OFFSET + width - 1) << R300_CLIPRECT_X_SHIFT) |
308 ((R300_SCISSORS_OFFSET + height - 1) << R300_CLIPRECT_Y_SHIFT));
309 }
310 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
311 OUT_BATCH(0xAAAA);
312 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
313 OUT_BATCH(0xffffff);
314 END_BATCH();
315 }
316 }
317
318 void r300_emit_cb_setup(struct r300_context *r300,
319 struct radeon_bo *bo,
320 uint32_t offset,
321 GLuint format,
322 unsigned cpp,
323 unsigned pitch)
324 {
325 BATCH_LOCALS(&r300->radeon);
326 uint32_t cbpitch = pitch / cpp;
327 uint32_t dw = 6;
328
329 assert(offset % 256 == 0);
330
331 switch (format) {
332 case MESA_FORMAT_RGB565:
333 assert(_mesa_little_endian());
334 cbpitch |= R300_COLOR_FORMAT_RGB565;
335 break;
336 case MESA_FORMAT_RGB565_REV:
337 assert(!_mesa_little_endian());
338 cbpitch |= R300_COLOR_FORMAT_RGB565;
339 break;
340 case MESA_FORMAT_ARGB4444:
341 assert(_mesa_little_endian());
342 cbpitch |= R300_COLOR_FORMAT_ARGB4444;
343 break;
344 case MESA_FORMAT_ARGB4444_REV:
345 assert(!_mesa_little_endian());
346 cbpitch |= R300_COLOR_FORMAT_ARGB4444;
347 break;
348 case MESA_FORMAT_ARGB1555:
349 assert(_mesa_little_endian());
350 cbpitch |= R300_COLOR_FORMAT_ARGB1555;
351 break;
352 case MESA_FORMAT_ARGB1555_REV:
353 assert(!_mesa_little_endian());
354 cbpitch |= R300_COLOR_FORMAT_ARGB1555;
355 break;
356 default:
357 if (cpp == 4) {
358 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
359 } else {
360 _mesa_problem(r300->radeon.glCtx, "unexpected format in emit_cb_offset()");;
361 }
362 break;
363 }
364
365 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
366 cbpitch |= R300_COLOR_TILE_ENABLE;
367
368 if (r300->radeon.radeonScreen->kernel_mm)
369 dw += 2;
370
371 BEGIN_BATCH_NO_AUTOSTATE(dw);
372 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
373 OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
374 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
375 if (!r300->radeon.radeonScreen->kernel_mm)
376 OUT_BATCH(cbpitch);
377 else
378 OUT_BATCH_RELOC(cbpitch, bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
379 END_BATCH();
380 }
381
382 static void emit_cb_offset_atom(GLcontext *ctx, struct radeon_state_atom * atom)
383 {
384 r300ContextPtr r300 = R300_CONTEXT(ctx);
385 struct radeon_renderbuffer *rrb;
386 uint32_t offset = r300->radeon.state.color.draw_offset;
387
388 rrb = radeon_get_colorbuffer(&r300->radeon);
389 if (!rrb || !rrb->bo) {
390 fprintf(stderr, "no rrb\n");
391 return;
392 }
393
394 if (RADEON_DEBUG & RADEON_STATE)
395 fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
396
397 r300_emit_cb_setup(r300, rrb->bo, offset, rrb->base.Format, rrb->cpp, rrb->pitch);
398
399 if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
400 emit_scissor(r300, rrb->base.Width, rrb->base.Height);
401 }
402 }
403
404 static int check_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
405 {
406 r300ContextPtr r300 = R300_CONTEXT(ctx);
407 uint32_t dw;
408 dw = 6;
409 if (r300->radeon.radeonScreen->kernel_mm)
410 dw += 2;
411 return dw;
412 }
413
414 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
415 {
416 r300ContextPtr r300 = R300_CONTEXT(ctx);
417 BATCH_LOCALS(&r300->radeon);
418 struct radeon_renderbuffer *rrb;
419 uint32_t zbpitch;
420 uint32_t dw = atom->check(ctx, atom);
421
422 rrb = radeon_get_depthbuffer(&r300->radeon);
423 if (!rrb)
424 return;
425
426 zbpitch = (rrb->pitch / rrb->cpp);
427 if (!r300->radeon.radeonScreen->kernel_mm) {
428 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
429 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
430 }
431 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
432 zbpitch |= R300_DEPTHMICROTILE_TILED;
433 }
434 }
435
436 BEGIN_BATCH_NO_AUTOSTATE(dw);
437 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
438 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
439 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
440 if (!r300->radeon.radeonScreen->kernel_mm)
441 OUT_BATCH(zbpitch);
442 else
443 OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
444 END_BATCH();
445 }
446
447 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
448 {
449 r300ContextPtr r300 = R300_CONTEXT(ctx);
450 BATCH_LOCALS(&r300->radeon);
451 struct radeon_renderbuffer *rrb;
452 uint32_t format = 0;
453
454 rrb = radeon_get_depthbuffer(&r300->radeon);
455 if (!rrb)
456 format = 0;
457 else {
458 if (rrb->cpp == 2)
459 format = R300_DEPTHFORMAT_16BIT_INT_Z;
460 else if (rrb->cpp == 4)
461 format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
462 }
463
464 BEGIN_BATCH_NO_AUTOSTATE(atom->cmd_size);
465 OUT_BATCH(atom->cmd[0]);
466 atom->cmd[1] &= ~0xf;
467 atom->cmd[1] |= format;
468 OUT_BATCH(atom->cmd[1]);
469 OUT_BATCH(atom->cmd[2]);
470 OUT_BATCH(atom->cmd[3]);
471 OUT_BATCH(atom->cmd[4]);
472 END_BATCH();
473 }
474
475 static int check_never(GLcontext *ctx, struct radeon_state_atom *atom)
476 {
477 return 0;
478 }
479
480 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
481 {
482 return atom->cmd_size;
483 }
484
485 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
486 {
487 r300ContextPtr r300 = R300_CONTEXT(ctx);
488 int cnt;
489 if (atom->cmd[0] == CP_PACKET2) {
490 return 0;
491 }
492 cnt = packet0_count(r300, atom->cmd);
493 return cnt ? cnt + 1 : 0;
494 }
495
496 static int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
497 {
498 int cnt;
499 r300ContextPtr r300 = R300_CONTEXT(ctx);
500 int extra = 1;
501 cnt = r500fp_count(atom->cmd);
502 if (r300->radeon.radeonScreen->kernel_mm)
503 extra = 3;
504
505 return cnt ? (cnt * 6) + extra : 0;
506 }
507
508 static int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
509 {
510 int cnt;
511 r300ContextPtr r300 = R300_CONTEXT(ctx);
512 int extra = 1;
513 cnt = r500fp_count(atom->cmd);
514 if (r300->radeon.radeonScreen->kernel_mm)
515 extra = 3;
516
517 cnt = r500fp_count(atom->cmd);
518 return cnt ? (cnt * 4) + extra : 0;
519 }
520
521 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
522 do { \
523 r300->hw.ATOM.cmd_size = (SZ); \
524 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
525 r300->hw.ATOM.name = #ATOM; \
526 r300->hw.ATOM.idx = (IDX); \
527 r300->hw.ATOM.check = check_##CHK; \
528 r300->hw.ATOM.dirty = GL_FALSE; \
529 r300->radeon.hw.max_state_size += (SZ); \
530 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
531 } while (0)
532 /**
533 * Allocate memory for the command buffer and initialize the state atom
534 * list. Note that the initial hardware state is set by r300InitState().
535 */
536 void r300InitCmdBuf(r300ContextPtr r300)
537 {
538 int mtu;
539 int has_tcl;
540 int is_r500 = 0;
541
542 has_tcl = r300->options.hw_tcl_enabled;
543
544 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
545 is_r500 = 1;
546
547 r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
548
549 mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
550 if (RADEON_DEBUG & RADEON_TEXTURE) {
551 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
552 }
553
554 /* Setup the atom linked list */
555 make_empty_list(&r300->radeon.hw.atomlist);
556 r300->radeon.hw.atomlist.name = "atom-list";
557
558 /* Initialize state atoms */
559 ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
560 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
561 ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
562 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
563 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
564 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
565 if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
566 ALLOC_STATE(vap_index_offset, always, 2, 0);
567 r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
568 r300->hw.vap_index_offset.cmd[1] = 0;
569 }
570 ALLOC_STATE(vte, always, 3, 0);
571 r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
572 ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
573 r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
574 ALLOC_STATE(vap_cntl_status, always, 2, 0);
575 r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
576 ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
577 r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
578 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
579 ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
580 r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
581 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
582 ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
583 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
584 ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
585 r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
586
587 if (has_tcl) {
588 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
589 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
590 ALLOC_STATE(vap_clip, always, 5, 0);
591 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
592 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
593 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
594 }
595
596 ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
597 r300->hw.vof.cmd[R300_VOF_CMD_0] =
598 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
599
600 if (has_tcl) {
601 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
602 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
603 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
604 }
605
606 ALLOC_STATE(gb_enable, always, 2, 0);
607 r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
608 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
609 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
610 } else {
611 ALLOC_STATE(gb_misc, never, R300_GB_MISC_CMDSIZE, 0);
612 }
613 r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
614 ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
615 r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
616 ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
617 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
618 ALLOC_STATE(ga_point_s0, always, 5, 0);
619 r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
620 ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
621 r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
622 ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
623 r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
624 ALLOC_STATE(ga_point_minmax, always, 4, 0);
625 r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
626 ALLOC_STATE(lcntl, always, 2, 0);
627 r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
628 ALLOC_STATE(ga_line_stipple, always, 4, 0);
629 r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
630 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
631 ALLOC_STATE(shade, always, 2, 0);
632 } else {
633 ALLOC_STATE(shade, never, 2, 0);
634 }
635 r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
636 ALLOC_STATE(shade2, always, 4, 0);
637 r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
638 ALLOC_STATE(polygon_mode, always, 4, 0);
639 r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
640 ALLOC_STATE(fogp, always, 3, 0);
641 r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
642 ALLOC_STATE(zbias_cntl, always, 2, 0);
643 r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
644 ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
645 r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
646 cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
647 ALLOC_STATE(occlusion_cntl, always, 2, 0);
648 r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
649 ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
650 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
651 ALLOC_STATE(su_depth_scale, always, 3, 0);
652 r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
653 ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
654 r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
655 if (is_r500) {
656 ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0);
657 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
658 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
659 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
660 } else {
661 ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0);
662 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
663 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
664 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
665 }
666 ALLOC_STATE(sc_hyperz, always, 3, 0);
667 r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
668 ALLOC_STATE(sc_screendoor, always, 2, 0);
669 r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
670 ALLOC_STATE(us_out_fmt, always, 6, 0);
671 r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
672
673 if (is_r500) {
674 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
675 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
676 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
677 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
678 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
679 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
680
681 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
682 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
683 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
684 if (r300->radeon.radeonScreen->kernel_mm)
685 r300->hw.r500fp.emit = emit_r500fp_atom;
686
687 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
688 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
689 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
690 if (r300->radeon.radeonScreen->kernel_mm)
691 r300->hw.r500fp_const.emit = emit_r500fp_atom;
692 } else {
693 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
694 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
695 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
696
697 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
698 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
699
700 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
701 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
702 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
703 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
704 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
705 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
706 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
707 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
708 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
709 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
710 }
711 ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
712 r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
713 ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
714 r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
715 ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
716 r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
717 ALLOC_STATE(fg_depth_src, always, 2, 0);
718 r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
719 ALLOC_STATE(rb3d_cctl, always, 2, 0);
720 r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
721 ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
722 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
723 ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
724 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
725 if (is_r500) {
726 ALLOC_STATE(blend_color, always, 3, 0);
727 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
728 } else {
729 ALLOC_STATE(blend_color, always, 2, 0);
730 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
731 }
732 ALLOC_STATE(rop, always, 2, 0);
733 r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
734 ALLOC_STATE(cb, cb_offset, R300_CB_CMDSIZE, 0);
735 r300->hw.cb.emit = &emit_cb_offset_atom;
736 ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
737 r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
738 ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
739 r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
740 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350) {
741 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
742 } else {
743 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);
744 }
745 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
746 ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
747 r300->hw.zs.cmd[R300_ZS_CMD_0] =
748 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
749 if (is_r500) {
750 if (r300->radeon.radeonScreen->kernel_mm)
751 ALLOC_STATE(zsb, always, R300_ZSB_CMDSIZE, 0);
752 else
753 ALLOC_STATE(zsb, never, R300_ZSB_CMDSIZE, 0);
754 r300->hw.zsb.cmd[R300_ZSB_CMD_0] =
755 cmdpacket0(r300->radeon.radeonScreen, R500_ZB_STENCILREFMASK_BF, 1);
756 }
757
758 ALLOC_STATE(zstencil_format, always, 5, 0);
759 r300->hw.zstencil_format.cmd[0] =
760 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
761 r300->hw.zstencil_format.emit = emit_zstencil_format;
762
763 ALLOC_STATE(zb, zb_offset, R300_ZB_CMDSIZE, 0);
764 r300->hw.zb.emit = emit_zb_offset;
765 ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
766 r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
767 ALLOC_STATE(zb_zmask, always, 3, 0);
768 r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
769 ALLOC_STATE(zb_hiz_offset, always, 2, 0);
770 r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
771 ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
772 r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
773
774 /* VPU only on TCL */
775 if (has_tcl) {
776 int i;
777 if (r300->radeon.radeonScreen->kernel_mm) {
778 ALLOC_STATE(vap_flush, always, 10, 0);
779 /* flush processing vertices */
780 r300->hw.vap_flush.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
781 r300->hw.vap_flush.cmd[1] = 0;
782 r300->hw.vap_flush.cmd[2] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DSTCACHE_CTLSTAT, 1);
783 r300->hw.vap_flush.cmd[3] = R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D;
784 r300->hw.vap_flush.cmd[4] = cmdpacket0(r300->radeon.radeonScreen, RADEON_WAIT_UNTIL, 1);
785 r300->hw.vap_flush.cmd[5] = RADEON_WAIT_3D_IDLECLEAN;
786 r300->hw.vap_flush.cmd[6] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
787 r300->hw.vap_flush.cmd[7] = 0xffffff;
788 r300->hw.vap_flush.cmd[8] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
789 r300->hw.vap_flush.cmd[9] = 0;
790 } else {
791 ALLOC_STATE(vap_flush, never, 10, 0);
792 }
793
794
795 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
796 r300->hw.vpi.cmd[0] =
797 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
798 if (r300->radeon.radeonScreen->kernel_mm)
799 r300->hw.vpi.emit = emit_vpu;
800
801 if (is_r500) {
802 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
803 r300->hw.vpp.cmd[0] =
804 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
805 if (r300->radeon.radeonScreen->kernel_mm)
806 r300->hw.vpp.emit = emit_vpu;
807
808 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
809 r300->hw.vps.cmd[0] =
810 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
811 if (r300->radeon.radeonScreen->kernel_mm)
812 r300->hw.vps.emit = emit_vpu;
813
814 for (i = 0; i < 6; i++) {
815 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
816 r300->hw.vpucp[i].cmd[0] =
817 cmdvpu(r300->radeon.radeonScreen,
818 R500_PVS_UCP_START + i, 1);
819 if (r300->radeon.radeonScreen->kernel_mm)
820 r300->hw.vpucp[i].emit = emit_vpu;
821 }
822 } else {
823 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
824 r300->hw.vpp.cmd[0] =
825 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
826 if (r300->radeon.radeonScreen->kernel_mm)
827 r300->hw.vpp.emit = emit_vpu;
828
829 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
830 r300->hw.vps.cmd[0] =
831 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
832 if (r300->radeon.radeonScreen->kernel_mm)
833 r300->hw.vps.emit = emit_vpu;
834
835 for (i = 0; i < 6; i++) {
836 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
837 r300->hw.vpucp[i].cmd[0] =
838 cmdvpu(r300->radeon.radeonScreen,
839 R300_PVS_UCP_START + i, 1);
840 if (r300->radeon.radeonScreen->kernel_mm)
841 r300->hw.vpucp[i].emit = emit_vpu;
842 }
843 }
844 }
845
846 /* Textures */
847 ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
848 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
849 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
850
851 ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
852 r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
853 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
854
855 ALLOC_STATE(tex.size, variable, mtu + 1, 0);
856 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
857
858 ALLOC_STATE(tex.format, variable, mtu + 1, 0);
859 r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
860 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
861
862 ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
863 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
864
865 ALLOC_STATE(tex.offset, tex_offsets, 1, 0);
866 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
867 cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
868 r300->hw.tex.offset.emit = &emit_tex_offsets;
869
870 ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
871 r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
872 cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
873
874 ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
875 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
876 cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
877
878 radeon_init_query_stateobj(&r300->radeon, R300_QUERYOBJ_CMDSIZE);
879 if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) {
880 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RV530_FG_ZBREG_DEST, 1);
881 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL;
882 } else {
883 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_REG_DEST, 1);
884 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = R300_RASTER_PIPE_SELECT_ALL;
885 }
886 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZPASS_DATA, 1);
887 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_1] = 0;
888
889 r300->radeon.hw.is_dirty = GL_TRUE;
890 r300->radeon.hw.all_dirty = GL_TRUE;
891
892 rcommonInitCmdBuf(&r300->radeon);
893 }