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r300: use _mesa_meta_Clear for buffer clears
[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Nicolai Haehnle <prefect_@gmx.net>
34 */
35
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
43
44 #include "drm.h"
45 #include "radeon_drm.h"
46
47 #include "r300_context.h"
48 #include "r300_reg.h"
49 #include "r300_cmdbuf.h"
50 #include "r300_emit.h"
51 #include "radeon_bocs_wrapper.h"
52 #include "radeon_mipmap_tree.h"
53 #include "r300_state.h"
54 #include "radeon_queryobj.h"
55
56 /** # of dwords reserved for additional instructions that may need to be written
57 * during flushing.
58 */
59 #define SPACE_FOR_FLUSHING 4
60
61 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
62 {
63 if (r300->radeon.radeonScreen->kernel_mm) {
64 return ((((*pkt) >> 16) & 0x3FFF) + 1);
65 } else {
66 drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
67 return t->packet0.count;
68 }
69 }
70
71 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
72 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
73
74 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
75 {
76 r300ContextPtr r300 = R300_CONTEXT(ctx);
77 int cnt;
78 int extra = 1;
79 cnt = vpu_count(atom->cmd);
80
81 if (r300->radeon.radeonScreen->kernel_mm) {
82 extra = 5;
83 }
84
85 return cnt ? (cnt * 4) + extra : 0;
86 }
87
88
89 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
90 {
91 r300ContextPtr r300 = R300_CONTEXT(ctx);
92 BATCH_LOCALS(&r300->radeon);
93 drm_r300_cmd_header_t cmd;
94 uint32_t addr, ndw;
95
96 cmd.u = atom->cmd[0];
97 addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
98 ndw = atom->check(ctx, atom);
99
100 BEGIN_BATCH_NO_AUTOSTATE(ndw);
101
102 ndw -= 5;
103 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
104 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
105 OUT_BATCH_TABLE(&atom->cmd[1], ndw);
106 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
107 END_BATCH();
108 }
109
110 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
111 {
112 r300ContextPtr r300 = R300_CONTEXT(ctx);
113 BATCH_LOCALS(&r300->radeon);
114 drm_r300_cmd_header_t cmd;
115 uint32_t addr, ndw, sz;
116 int type, clamp;
117
118 ndw = atom->check(ctx, atom);
119
120 cmd.u = atom->cmd[0];
121 sz = cmd.r500fp.count;
122 addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
123 type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
124 clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
125
126 addr |= (type << 16);
127 addr |= (clamp << 17);
128
129 BEGIN_BATCH_NO_AUTOSTATE(ndw);
130 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
131 OUT_BATCH(addr);
132 ndw-=3;
133 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
134 OUT_BATCH_TABLE(&atom->cmd[1], ndw);
135 END_BATCH();
136 }
137
138 static int check_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
139 {
140 r300ContextPtr r300 = R300_CONTEXT(ctx);
141 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
142 int dw = 0, i;
143 if (atom->cmd[0] == CP_PACKET2) {
144 return dw;
145 }
146 for(i = 0; i < numtmus; ++i) {
147 radeonTexObj *t = r300->hw.textures[i];
148 if (!t && !r300->radeon.radeonScreen->kernel_mm) {
149 dw += 0;
150 } else if (t && t->image_override && !t->bo) {
151 if (!r300->radeon.radeonScreen->kernel_mm)
152 dw += 2;
153 } else
154 dw += 4;
155 }
156 return dw;
157 }
158
159 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
160 {
161 r300ContextPtr r300 = R300_CONTEXT(ctx);
162 BATCH_LOCALS(&r300->radeon);
163 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
164 int i;
165
166 for(i = 0; i < numtmus; ++i) {
167 radeonTexObj *t = r300->hw.textures[i];
168 if (t && !t->image_override) {
169 BEGIN_BATCH_NO_AUTOSTATE(4);
170 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
171 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
172 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
173 END_BATCH();
174 } else if (!t) {
175 /* Texture unit hasn't a texture bound.
176 * We assign the current color buffer as a fakery to make
177 * KIL work on KMS (without it, the CS checker will complain).
178 */
179 if (r300->radeon.radeonScreen->kernel_mm) {
180 struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
181 if (rrb && rrb->bo) {
182 BEGIN_BATCH_NO_AUTOSTATE(4);
183 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
184 OUT_BATCH_RELOC(0, rrb->bo, 0,
185 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
186 END_BATCH();
187 }
188 }
189 } else { /* override cases */
190 if (t->bo) {
191 BEGIN_BATCH_NO_AUTOSTATE(4);
192 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
193 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
194 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
195 END_BATCH();
196 } else if (!r300->radeon.radeonScreen->kernel_mm) {
197 BEGIN_BATCH_NO_AUTOSTATE(2);
198 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
199 OUT_BATCH(t->override_offset);
200 END_BATCH();
201 } else {
202 /* Texture unit hasn't a texture bound nothings to do */
203 }
204 }
205 }
206 }
207
208 void r300_emit_scissor(GLcontext *ctx)
209 {
210 r300ContextPtr r300 = R300_CONTEXT(ctx);
211 BATCH_LOCALS(&r300->radeon);
212 unsigned x1, y1, x2, y2;
213 struct radeon_renderbuffer *rrb;
214
215 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
216 return;
217 }
218 rrb = radeon_get_colorbuffer(&r300->radeon);
219 if (!rrb || !rrb->bo) {
220 fprintf(stderr, "no rrb\n");
221 return;
222 }
223 if (r300->radeon.state.scissor.enabled) {
224 x1 = r300->radeon.state.scissor.rect.x1;
225 y1 = r300->radeon.state.scissor.rect.y1;
226 x2 = r300->radeon.state.scissor.rect.x2;
227 y2 = r300->radeon.state.scissor.rect.y2;
228 } else {
229 x1 = 0;
230 y1 = 0;
231 x2 = rrb->base.Width - 1;
232 y2 = rrb->base.Height - 1;
233 }
234 if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
235 x1 += R300_SCISSORS_OFFSET;
236 y1 += R300_SCISSORS_OFFSET;
237 x2 += R300_SCISSORS_OFFSET;
238 y2 += R300_SCISSORS_OFFSET;
239 }
240 BEGIN_BATCH_NO_AUTOSTATE(3);
241 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
242 OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
243 OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
244 END_BATCH();
245 }
246 static int check_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
247 {
248 r300ContextPtr r300 = R300_CONTEXT(ctx);
249 uint32_t dw = 6 + 3 + 16;
250 if (r300->radeon.radeonScreen->kernel_mm)
251 dw += 2;
252 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
253 dw -= 3 + 16;
254 }
255 return dw;
256 }
257
258 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
259 {
260 r300ContextPtr r300 = R300_CONTEXT(ctx);
261 BATCH_LOCALS(&r300->radeon);
262 struct radeon_renderbuffer *rrb;
263 uint32_t cbpitch;
264 uint32_t offset = r300->radeon.state.color.draw_offset;
265 uint32_t dw = 6;
266 int i;
267
268 rrb = radeon_get_colorbuffer(&r300->radeon);
269 if (!rrb || !rrb->bo) {
270 fprintf(stderr, "no rrb\n");
271 return;
272 }
273
274 if (RADEON_DEBUG & RADEON_STATE)
275 fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
276 cbpitch = (rrb->pitch / rrb->cpp);
277 if (rrb->cpp == 4)
278 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
279 else switch (rrb->base.Format) {
280 case MESA_FORMAT_RGB565:
281 assert(_mesa_little_endian());
282 cbpitch |= R300_COLOR_FORMAT_RGB565;
283 break;
284 case MESA_FORMAT_RGB565_REV:
285 assert(!_mesa_little_endian());
286 cbpitch |= R300_COLOR_FORMAT_RGB565;
287 break;
288 case MESA_FORMAT_ARGB4444:
289 assert(_mesa_little_endian());
290 cbpitch |= R300_COLOR_FORMAT_ARGB4444;
291 break;
292 case MESA_FORMAT_ARGB4444_REV:
293 assert(!_mesa_little_endian());
294 cbpitch |= R300_COLOR_FORMAT_ARGB4444;
295 break;
296 case MESA_FORMAT_ARGB1555:
297 assert(_mesa_little_endian());
298 cbpitch |= R300_COLOR_FORMAT_ARGB1555;
299 break;
300 case MESA_FORMAT_ARGB1555_REV:
301 assert(!_mesa_little_endian());
302 cbpitch |= R300_COLOR_FORMAT_ARGB1555;
303 break;
304 default:
305 _mesa_problem(ctx, "unexpected format in emit_cb_offset()");
306 }
307
308 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
309 cbpitch |= R300_COLOR_TILE_ENABLE;
310
311 if (r300->radeon.radeonScreen->kernel_mm)
312 dw += 2;
313 BEGIN_BATCH_NO_AUTOSTATE(dw);
314 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
315 OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
316 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
317 if (!r300->radeon.radeonScreen->kernel_mm)
318 OUT_BATCH(cbpitch);
319 else
320 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
321 END_BATCH();
322 if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
323 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
324 BEGIN_BATCH_NO_AUTOSTATE(3);
325 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
326 OUT_BATCH(0);
327 OUT_BATCH(((rrb->base.Width - 1) << R300_SCISSORS_X_SHIFT) |
328 ((rrb->base.Height - 1) << R300_SCISSORS_Y_SHIFT));
329 END_BATCH();
330 BEGIN_BATCH_NO_AUTOSTATE(16);
331 for (i = 0; i < 4; i++) {
332 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
333 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
334 OUT_BATCH(((rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT));
335 }
336 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
337 OUT_BATCH(0xAAAA);
338 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
339 OUT_BATCH(0xffffff);
340 END_BATCH();
341 } else {
342 BEGIN_BATCH_NO_AUTOSTATE(3);
343 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
344 OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
345 (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
346 OUT_BATCH(((rrb->base.Width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
347 ((rrb->base.Height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
348 END_BATCH();
349 BEGIN_BATCH_NO_AUTOSTATE(16);
350 for (i = 0; i < 4; i++) {
351 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
352 OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
353 OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) |
354 ((R300_SCISSORS_OFFSET + rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT));
355 }
356 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
357 OUT_BATCH(0xAAAA);
358 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
359 OUT_BATCH(0xffffff);
360 END_BATCH();
361 }
362 }
363 }
364
365 static int check_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
366 {
367 r300ContextPtr r300 = R300_CONTEXT(ctx);
368 uint32_t dw;
369 dw = 6;
370 if (r300->radeon.radeonScreen->kernel_mm)
371 dw += 2;
372 return dw;
373 }
374
375 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
376 {
377 r300ContextPtr r300 = R300_CONTEXT(ctx);
378 BATCH_LOCALS(&r300->radeon);
379 struct radeon_renderbuffer *rrb;
380 uint32_t zbpitch;
381 uint32_t dw = atom->check(ctx, atom);
382
383 rrb = radeon_get_depthbuffer(&r300->radeon);
384 if (!rrb)
385 return;
386
387 zbpitch = (rrb->pitch / rrb->cpp);
388 if (!r300->radeon.radeonScreen->kernel_mm) {
389 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
390 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
391 }
392 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
393 zbpitch |= R300_DEPTHMICROTILE_TILED;
394 }
395 }
396
397 BEGIN_BATCH_NO_AUTOSTATE(dw);
398 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
399 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
400 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
401 if (!r300->radeon.radeonScreen->kernel_mm)
402 OUT_BATCH(zbpitch);
403 else
404 OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
405 END_BATCH();
406 }
407
408 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
409 {
410 r300ContextPtr r300 = R300_CONTEXT(ctx);
411 BATCH_LOCALS(&r300->radeon);
412 struct radeon_renderbuffer *rrb;
413 uint32_t format = 0;
414
415 rrb = radeon_get_depthbuffer(&r300->radeon);
416 if (!rrb)
417 format = 0;
418 else {
419 if (rrb->cpp == 2)
420 format = R300_DEPTHFORMAT_16BIT_INT_Z;
421 else if (rrb->cpp == 4)
422 format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
423 }
424
425 BEGIN_BATCH_NO_AUTOSTATE(atom->cmd_size);
426 OUT_BATCH(atom->cmd[0]);
427 atom->cmd[1] &= ~0xf;
428 atom->cmd[1] |= format;
429 OUT_BATCH(atom->cmd[1]);
430 OUT_BATCH(atom->cmd[2]);
431 OUT_BATCH(atom->cmd[3]);
432 OUT_BATCH(atom->cmd[4]);
433 END_BATCH();
434 }
435
436 static int check_never(GLcontext *ctx, struct radeon_state_atom *atom)
437 {
438 return 0;
439 }
440
441 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
442 {
443 return atom->cmd_size;
444 }
445
446 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
447 {
448 r300ContextPtr r300 = R300_CONTEXT(ctx);
449 int cnt;
450 if (atom->cmd[0] == CP_PACKET2) {
451 return 0;
452 }
453 cnt = packet0_count(r300, atom->cmd);
454 return cnt ? cnt + 1 : 0;
455 }
456
457 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
458 {
459 int cnt;
460 r300ContextPtr r300 = R300_CONTEXT(ctx);
461 int extra = 1;
462 cnt = r500fp_count(atom->cmd);
463 if (r300->radeon.radeonScreen->kernel_mm)
464 extra = 3;
465
466 return cnt ? (cnt * 6) + extra : 0;
467 }
468
469 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
470 {
471 int cnt;
472 r300ContextPtr r300 = R300_CONTEXT(ctx);
473 int extra = 1;
474 cnt = r500fp_count(atom->cmd);
475 if (r300->radeon.radeonScreen->kernel_mm)
476 extra = 3;
477
478 cnt = r500fp_count(atom->cmd);
479 return cnt ? (cnt * 4) + extra : 0;
480 }
481
482 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
483 do { \
484 r300->hw.ATOM.cmd_size = (SZ); \
485 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
486 r300->hw.ATOM.name = #ATOM; \
487 r300->hw.ATOM.idx = (IDX); \
488 r300->hw.ATOM.check = check_##CHK; \
489 r300->hw.ATOM.dirty = GL_FALSE; \
490 r300->radeon.hw.max_state_size += (SZ); \
491 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
492 } while (0)
493 /**
494 * Allocate memory for the command buffer and initialize the state atom
495 * list. Note that the initial hardware state is set by r300InitState().
496 */
497 void r300InitCmdBuf(r300ContextPtr r300)
498 {
499 int mtu;
500 int has_tcl;
501 int is_r500 = 0;
502
503 has_tcl = r300->options.hw_tcl_enabled;
504
505 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
506 is_r500 = 1;
507
508 r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
509
510 mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
511 if (RADEON_DEBUG & RADEON_TEXTURE) {
512 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
513 }
514
515 /* Setup the atom linked list */
516 make_empty_list(&r300->radeon.hw.atomlist);
517 r300->radeon.hw.atomlist.name = "atom-list";
518
519 /* Initialize state atoms */
520 ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
521 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
522 ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
523 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
524 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
525 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
526 if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
527 ALLOC_STATE(vap_index_offset, always, 2, 0);
528 r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
529 r300->hw.vap_index_offset.cmd[1] = 0;
530 }
531 ALLOC_STATE(vte, always, 3, 0);
532 r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
533 ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
534 r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
535 ALLOC_STATE(vap_cntl_status, always, 2, 0);
536 r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
537 ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
538 r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
539 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
540 ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
541 r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
542 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
543 ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
544 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
545 ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
546 r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
547
548 if (has_tcl) {
549 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
550 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
551 ALLOC_STATE(vap_clip, always, 5, 0);
552 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
553 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
554 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
555 }
556
557 ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
558 r300->hw.vof.cmd[R300_VOF_CMD_0] =
559 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
560
561 if (has_tcl) {
562 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
563 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
564 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
565 }
566
567 ALLOC_STATE(gb_enable, always, 2, 0);
568 r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
569 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
570 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
571 } else {
572 ALLOC_STATE(gb_misc, never, R300_GB_MISC_CMDSIZE, 0);
573 }
574 r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
575 ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
576 r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
577 ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
578 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
579 ALLOC_STATE(ga_point_s0, always, 5, 0);
580 r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
581 ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
582 r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
583 ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
584 r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
585 ALLOC_STATE(ga_point_minmax, always, 4, 0);
586 r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
587 ALLOC_STATE(lcntl, always, 2, 0);
588 r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
589 ALLOC_STATE(ga_line_stipple, always, 4, 0);
590 r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
591 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
592 ALLOC_STATE(shade, always, 2, 0);
593 } else {
594 ALLOC_STATE(shade, never, 2, 0);
595 }
596 r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
597 ALLOC_STATE(shade2, always, 4, 0);
598 r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
599 ALLOC_STATE(polygon_mode, always, 4, 0);
600 r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
601 ALLOC_STATE(fogp, always, 3, 0);
602 r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
603 ALLOC_STATE(zbias_cntl, always, 2, 0);
604 r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
605 ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
606 r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
607 cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
608 ALLOC_STATE(occlusion_cntl, always, 2, 0);
609 r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
610 ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
611 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
612 ALLOC_STATE(su_depth_scale, always, 3, 0);
613 r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
614 ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
615 r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
616 if (is_r500) {
617 ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0);
618 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
619 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
620 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
621 } else {
622 ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0);
623 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
624 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
625 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
626 }
627 ALLOC_STATE(sc_hyperz, always, 3, 0);
628 r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
629 ALLOC_STATE(sc_screendoor, always, 2, 0);
630 r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
631 ALLOC_STATE(us_out_fmt, always, 6, 0);
632 r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
633
634 if (is_r500) {
635 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
636 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
637 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
638 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
639 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
640 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
641
642 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
643 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
644 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
645 if (r300->radeon.radeonScreen->kernel_mm)
646 r300->hw.r500fp.emit = emit_r500fp;
647
648 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
649 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
650 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
651 if (r300->radeon.radeonScreen->kernel_mm)
652 r300->hw.r500fp_const.emit = emit_r500fp;
653 } else {
654 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
655 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
656 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
657
658 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
659 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
660
661 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
662 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
663 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
664 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
665 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
666 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
667 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
668 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
669 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
670 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
671 }
672 ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
673 r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
674 ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
675 r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
676 ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
677 r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
678 ALLOC_STATE(fg_depth_src, always, 2, 0);
679 r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
680 ALLOC_STATE(rb3d_cctl, always, 2, 0);
681 r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
682 ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
683 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
684 ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
685 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
686 if (is_r500) {
687 ALLOC_STATE(blend_color, always, 3, 0);
688 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
689 } else {
690 ALLOC_STATE(blend_color, always, 2, 0);
691 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
692 }
693 ALLOC_STATE(rop, always, 2, 0);
694 r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
695 ALLOC_STATE(cb, cb_offset, R300_CB_CMDSIZE, 0);
696 r300->hw.cb.emit = &emit_cb_offset;
697 ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
698 r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
699 ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
700 r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
701 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350) {
702 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
703 } else {
704 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);
705 }
706 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
707 ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
708 r300->hw.zs.cmd[R300_ZS_CMD_0] =
709 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
710 if (is_r500) {
711 if (r300->radeon.radeonScreen->kernel_mm)
712 ALLOC_STATE(zsb, always, R300_ZSB_CMDSIZE, 0);
713 else
714 ALLOC_STATE(zsb, never, R300_ZSB_CMDSIZE, 0);
715 r300->hw.zsb.cmd[R300_ZSB_CMD_0] =
716 cmdpacket0(r300->radeon.radeonScreen, R500_ZB_STENCILREFMASK_BF, 1);
717 }
718
719 ALLOC_STATE(zstencil_format, always, 5, 0);
720 r300->hw.zstencil_format.cmd[0] =
721 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
722 r300->hw.zstencil_format.emit = emit_zstencil_format;
723
724 ALLOC_STATE(zb, zb_offset, R300_ZB_CMDSIZE, 0);
725 r300->hw.zb.emit = emit_zb_offset;
726 ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
727 r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
728 ALLOC_STATE(zb_zmask, always, 3, 0);
729 r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
730 ALLOC_STATE(zb_hiz_offset, always, 2, 0);
731 r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
732 ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
733 r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
734
735 /* VPU only on TCL */
736 if (has_tcl) {
737 int i;
738 if (r300->radeon.radeonScreen->kernel_mm) {
739 ALLOC_STATE(vap_flush, always, 10, 0);
740 /* flush processing vertices */
741 r300->hw.vap_flush.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
742 r300->hw.vap_flush.cmd[1] = 0;
743 r300->hw.vap_flush.cmd[2] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DSTCACHE_CTLSTAT, 1);
744 r300->hw.vap_flush.cmd[3] = R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D;
745 r300->hw.vap_flush.cmd[4] = cmdpacket0(r300->radeon.radeonScreen, RADEON_WAIT_UNTIL, 1);
746 r300->hw.vap_flush.cmd[5] = RADEON_WAIT_3D_IDLECLEAN;
747 r300->hw.vap_flush.cmd[6] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
748 r300->hw.vap_flush.cmd[7] = 0xffffff;
749 r300->hw.vap_flush.cmd[8] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
750 r300->hw.vap_flush.cmd[9] = 0;
751 } else {
752 ALLOC_STATE(vap_flush, never, 10, 0);
753 }
754
755
756 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
757 r300->hw.vpi.cmd[0] =
758 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
759 if (r300->radeon.radeonScreen->kernel_mm)
760 r300->hw.vpi.emit = emit_vpu;
761
762 if (is_r500) {
763 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
764 r300->hw.vpp.cmd[0] =
765 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
766 if (r300->radeon.radeonScreen->kernel_mm)
767 r300->hw.vpp.emit = emit_vpu;
768
769 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
770 r300->hw.vps.cmd[0] =
771 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
772 if (r300->radeon.radeonScreen->kernel_mm)
773 r300->hw.vps.emit = emit_vpu;
774
775 for (i = 0; i < 6; i++) {
776 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
777 r300->hw.vpucp[i].cmd[0] =
778 cmdvpu(r300->radeon.radeonScreen,
779 R500_PVS_UCP_START + i, 1);
780 if (r300->radeon.radeonScreen->kernel_mm)
781 r300->hw.vpucp[i].emit = emit_vpu;
782 }
783 } else {
784 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
785 r300->hw.vpp.cmd[0] =
786 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
787 if (r300->radeon.radeonScreen->kernel_mm)
788 r300->hw.vpp.emit = emit_vpu;
789
790 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
791 r300->hw.vps.cmd[0] =
792 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
793 if (r300->radeon.radeonScreen->kernel_mm)
794 r300->hw.vps.emit = emit_vpu;
795
796 for (i = 0; i < 6; i++) {
797 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
798 r300->hw.vpucp[i].cmd[0] =
799 cmdvpu(r300->radeon.radeonScreen,
800 R300_PVS_UCP_START + i, 1);
801 if (r300->radeon.radeonScreen->kernel_mm)
802 r300->hw.vpucp[i].emit = emit_vpu;
803 }
804 }
805 }
806
807 /* Textures */
808 ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
809 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
810 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
811
812 ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
813 r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
814 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
815
816 ALLOC_STATE(tex.size, variable, mtu + 1, 0);
817 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
818
819 ALLOC_STATE(tex.format, variable, mtu + 1, 0);
820 r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
821 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
822
823 ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
824 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
825
826 ALLOC_STATE(tex.offset, tex_offsets, 1, 0);
827 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
828 cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
829 r300->hw.tex.offset.emit = &emit_tex_offsets;
830
831 ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
832 r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
833 cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
834
835 ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
836 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
837 cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
838
839 radeon_init_query_stateobj(&r300->radeon, R300_QUERYOBJ_CMDSIZE);
840 if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) {
841 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RV530_FG_ZBREG_DEST, 1);
842 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL;
843 } else {
844 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_REG_DEST, 1);
845 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = R300_RASTER_PIPE_SELECT_ALL;
846 }
847 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZPASS_DATA, 1);
848 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_1] = 0;
849
850 r300->radeon.hw.is_dirty = GL_TRUE;
851 r300->radeon.hw.all_dirty = GL_TRUE;
852
853 rcommonInitCmdBuf(&r300->radeon);
854 }