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r300: Remove unnecessary headers.
[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Nicolai Haehnle <prefect_@gmx.net>
34 */
35
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42
43 #include "drm.h"
44 #include "radeon_drm.h"
45
46 #include "r300_context.h"
47 #include "r300_reg.h"
48 #include "r300_cmdbuf.h"
49 #include "r300_emit.h"
50 #include "radeon_bocs_wrapper.h"
51 #include "radeon_mipmap_tree.h"
52 #include "radeon_queryobj.h"
53
54 /** # of dwords reserved for additional instructions that may need to be written
55 * during flushing.
56 */
57 #define SPACE_FOR_FLUSHING 4
58
59 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
60 {
61 if (r300->radeon.radeonScreen->kernel_mm) {
62 return ((((*pkt) >> 16) & 0x3FFF) + 1);
63 } else {
64 drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
65 return t->packet0.count;
66 }
67 }
68
69 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
70 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
71
72 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
73 {
74 r300ContextPtr r300 = R300_CONTEXT(ctx);
75 int cnt;
76 int extra = 1;
77 cnt = vpu_count(atom->cmd);
78
79 if (r300->radeon.radeonScreen->kernel_mm) {
80 extra = 5;
81 }
82
83 return cnt ? (cnt * 4) + extra : 0;
84 }
85
86
87 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
88 {
89 r300ContextPtr r300 = R300_CONTEXT(ctx);
90 BATCH_LOCALS(&r300->radeon);
91 drm_r300_cmd_header_t cmd;
92 uint32_t addr, ndw;
93
94 cmd.u = atom->cmd[0];
95 addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
96 ndw = atom->check(ctx, atom);
97
98 BEGIN_BATCH_NO_AUTOSTATE(ndw);
99
100 ndw -= 5;
101 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
102 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
103 OUT_BATCH_TABLE(&atom->cmd[1], ndw);
104 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
105 END_BATCH();
106 }
107
108 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
109 {
110 r300ContextPtr r300 = R300_CONTEXT(ctx);
111 BATCH_LOCALS(&r300->radeon);
112 drm_r300_cmd_header_t cmd;
113 uint32_t addr, ndw, sz;
114 int type, clamp;
115
116 ndw = atom->check(ctx, atom);
117
118 cmd.u = atom->cmd[0];
119 sz = cmd.r500fp.count;
120 addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
121 type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
122 clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
123
124 addr |= (type << 16);
125 addr |= (clamp << 17);
126
127 BEGIN_BATCH_NO_AUTOSTATE(ndw);
128 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
129 OUT_BATCH(addr);
130 ndw-=3;
131 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
132 OUT_BATCH_TABLE(&atom->cmd[1], ndw);
133 END_BATCH();
134 }
135
136 static int check_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
137 {
138 r300ContextPtr r300 = R300_CONTEXT(ctx);
139 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
140 int dw = 0, i;
141 if (atom->cmd[0] == CP_PACKET2) {
142 return dw;
143 }
144 for(i = 0; i < numtmus; ++i) {
145 radeonTexObj *t = r300->hw.textures[i];
146 if (!t && !r300->radeon.radeonScreen->kernel_mm) {
147 dw += 0;
148 } else if (t && t->image_override && !t->bo) {
149 if (!r300->radeon.radeonScreen->kernel_mm)
150 dw += 2;
151 } else
152 dw += 4;
153 }
154 return dw;
155 }
156
157 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
158 {
159 r300ContextPtr r300 = R300_CONTEXT(ctx);
160 BATCH_LOCALS(&r300->radeon);
161 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
162 int i;
163
164 for(i = 0; i < numtmus; ++i) {
165 radeonTexObj *t = r300->hw.textures[i];
166 if (t && !t->image_override) {
167 BEGIN_BATCH_NO_AUTOSTATE(4);
168 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
169 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
170 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
171 END_BATCH();
172 } else if (!t) {
173 /* Texture unit hasn't a texture bound.
174 * We assign the current color buffer as a fakery to make
175 * KIL work on KMS (without it, the CS checker will complain).
176 */
177 if (r300->radeon.radeonScreen->kernel_mm) {
178 struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
179 if (rrb && rrb->bo) {
180 BEGIN_BATCH_NO_AUTOSTATE(4);
181 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
182 OUT_BATCH_RELOC(0, rrb->bo, 0,
183 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
184 END_BATCH();
185 }
186 }
187 } else { /* override cases */
188 if (t->bo) {
189 BEGIN_BATCH_NO_AUTOSTATE(4);
190 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
191 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
192 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
193 END_BATCH();
194 } else if (!r300->radeon.radeonScreen->kernel_mm) {
195 BEGIN_BATCH_NO_AUTOSTATE(2);
196 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
197 OUT_BATCH(t->override_offset);
198 END_BATCH();
199 } else {
200 /* Texture unit hasn't a texture bound nothings to do */
201 }
202 }
203 }
204 }
205
206 void r300_emit_scissor(GLcontext *ctx)
207 {
208 r300ContextPtr r300 = R300_CONTEXT(ctx);
209 BATCH_LOCALS(&r300->radeon);
210 unsigned x1, y1, x2, y2;
211 struct radeon_renderbuffer *rrb;
212
213 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
214 return;
215 }
216 rrb = radeon_get_colorbuffer(&r300->radeon);
217 if (!rrb || !rrb->bo) {
218 fprintf(stderr, "no rrb\n");
219 return;
220 }
221 if (r300->radeon.state.scissor.enabled) {
222 x1 = r300->radeon.state.scissor.rect.x1;
223 y1 = r300->radeon.state.scissor.rect.y1;
224 x2 = r300->radeon.state.scissor.rect.x2;
225 y2 = r300->radeon.state.scissor.rect.y2;
226 } else {
227 x1 = 0;
228 y1 = 0;
229 x2 = rrb->base.Width - 1;
230 y2 = rrb->base.Height - 1;
231 }
232 if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
233 x1 += R300_SCISSORS_OFFSET;
234 y1 += R300_SCISSORS_OFFSET;
235 x2 += R300_SCISSORS_OFFSET;
236 y2 += R300_SCISSORS_OFFSET;
237 }
238 BEGIN_BATCH_NO_AUTOSTATE(3);
239 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
240 OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
241 OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
242 END_BATCH();
243 }
244 static int check_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
245 {
246 r300ContextPtr r300 = R300_CONTEXT(ctx);
247 uint32_t dw = 6 + 3 + 16;
248 if (r300->radeon.radeonScreen->kernel_mm)
249 dw += 2;
250 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
251 dw -= 3 + 16;
252 }
253 return dw;
254 }
255
256 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
257 {
258 r300ContextPtr r300 = R300_CONTEXT(ctx);
259 BATCH_LOCALS(&r300->radeon);
260 struct radeon_renderbuffer *rrb;
261 uint32_t cbpitch;
262 uint32_t offset = r300->radeon.state.color.draw_offset;
263 uint32_t dw = 6;
264 int i;
265
266 rrb = radeon_get_colorbuffer(&r300->radeon);
267 if (!rrb || !rrb->bo) {
268 fprintf(stderr, "no rrb\n");
269 return;
270 }
271
272 if (RADEON_DEBUG & RADEON_STATE)
273 fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
274 cbpitch = (rrb->pitch / rrb->cpp);
275 if (rrb->cpp == 4)
276 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
277 else switch (rrb->base.Format) {
278 case MESA_FORMAT_RGB565:
279 assert(_mesa_little_endian());
280 cbpitch |= R300_COLOR_FORMAT_RGB565;
281 break;
282 case MESA_FORMAT_RGB565_REV:
283 assert(!_mesa_little_endian());
284 cbpitch |= R300_COLOR_FORMAT_RGB565;
285 break;
286 case MESA_FORMAT_ARGB4444:
287 assert(_mesa_little_endian());
288 cbpitch |= R300_COLOR_FORMAT_ARGB4444;
289 break;
290 case MESA_FORMAT_ARGB4444_REV:
291 assert(!_mesa_little_endian());
292 cbpitch |= R300_COLOR_FORMAT_ARGB4444;
293 break;
294 case MESA_FORMAT_ARGB1555:
295 assert(_mesa_little_endian());
296 cbpitch |= R300_COLOR_FORMAT_ARGB1555;
297 break;
298 case MESA_FORMAT_ARGB1555_REV:
299 assert(!_mesa_little_endian());
300 cbpitch |= R300_COLOR_FORMAT_ARGB1555;
301 break;
302 default:
303 _mesa_problem(ctx, "unexpected format in emit_cb_offset()");
304 }
305
306 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
307 cbpitch |= R300_COLOR_TILE_ENABLE;
308
309 if (r300->radeon.radeonScreen->kernel_mm)
310 dw += 2;
311 BEGIN_BATCH_NO_AUTOSTATE(dw);
312 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
313 OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
314 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
315 if (!r300->radeon.radeonScreen->kernel_mm)
316 OUT_BATCH(cbpitch);
317 else
318 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
319 END_BATCH();
320 if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
321 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
322 BEGIN_BATCH_NO_AUTOSTATE(3);
323 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
324 OUT_BATCH(0);
325 OUT_BATCH(((rrb->base.Width - 1) << R300_SCISSORS_X_SHIFT) |
326 ((rrb->base.Height - 1) << R300_SCISSORS_Y_SHIFT));
327 END_BATCH();
328 BEGIN_BATCH_NO_AUTOSTATE(16);
329 for (i = 0; i < 4; i++) {
330 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
331 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
332 OUT_BATCH(((rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT));
333 }
334 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
335 OUT_BATCH(0xAAAA);
336 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
337 OUT_BATCH(0xffffff);
338 END_BATCH();
339 } else {
340 BEGIN_BATCH_NO_AUTOSTATE(3);
341 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
342 OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
343 (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
344 OUT_BATCH(((rrb->base.Width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
345 ((rrb->base.Height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
346 END_BATCH();
347 BEGIN_BATCH_NO_AUTOSTATE(16);
348 for (i = 0; i < 4; i++) {
349 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
350 OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
351 OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) |
352 ((R300_SCISSORS_OFFSET + rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT));
353 }
354 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
355 OUT_BATCH(0xAAAA);
356 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
357 OUT_BATCH(0xffffff);
358 END_BATCH();
359 }
360 }
361 }
362
363 static int check_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
364 {
365 r300ContextPtr r300 = R300_CONTEXT(ctx);
366 uint32_t dw;
367 dw = 6;
368 if (r300->radeon.radeonScreen->kernel_mm)
369 dw += 2;
370 return dw;
371 }
372
373 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
374 {
375 r300ContextPtr r300 = R300_CONTEXT(ctx);
376 BATCH_LOCALS(&r300->radeon);
377 struct radeon_renderbuffer *rrb;
378 uint32_t zbpitch;
379 uint32_t dw = atom->check(ctx, atom);
380
381 rrb = radeon_get_depthbuffer(&r300->radeon);
382 if (!rrb)
383 return;
384
385 zbpitch = (rrb->pitch / rrb->cpp);
386 if (!r300->radeon.radeonScreen->kernel_mm) {
387 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
388 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
389 }
390 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
391 zbpitch |= R300_DEPTHMICROTILE_TILED;
392 }
393 }
394
395 BEGIN_BATCH_NO_AUTOSTATE(dw);
396 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
397 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
398 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
399 if (!r300->radeon.radeonScreen->kernel_mm)
400 OUT_BATCH(zbpitch);
401 else
402 OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
403 END_BATCH();
404 }
405
406 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
407 {
408 r300ContextPtr r300 = R300_CONTEXT(ctx);
409 BATCH_LOCALS(&r300->radeon);
410 struct radeon_renderbuffer *rrb;
411 uint32_t format = 0;
412
413 rrb = radeon_get_depthbuffer(&r300->radeon);
414 if (!rrb)
415 format = 0;
416 else {
417 if (rrb->cpp == 2)
418 format = R300_DEPTHFORMAT_16BIT_INT_Z;
419 else if (rrb->cpp == 4)
420 format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
421 }
422
423 BEGIN_BATCH_NO_AUTOSTATE(atom->cmd_size);
424 OUT_BATCH(atom->cmd[0]);
425 atom->cmd[1] &= ~0xf;
426 atom->cmd[1] |= format;
427 OUT_BATCH(atom->cmd[1]);
428 OUT_BATCH(atom->cmd[2]);
429 OUT_BATCH(atom->cmd[3]);
430 OUT_BATCH(atom->cmd[4]);
431 END_BATCH();
432 }
433
434 static int check_never(GLcontext *ctx, struct radeon_state_atom *atom)
435 {
436 return 0;
437 }
438
439 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
440 {
441 return atom->cmd_size;
442 }
443
444 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
445 {
446 r300ContextPtr r300 = R300_CONTEXT(ctx);
447 int cnt;
448 if (atom->cmd[0] == CP_PACKET2) {
449 return 0;
450 }
451 cnt = packet0_count(r300, atom->cmd);
452 return cnt ? cnt + 1 : 0;
453 }
454
455 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
456 {
457 int cnt;
458 r300ContextPtr r300 = R300_CONTEXT(ctx);
459 int extra = 1;
460 cnt = r500fp_count(atom->cmd);
461 if (r300->radeon.radeonScreen->kernel_mm)
462 extra = 3;
463
464 return cnt ? (cnt * 6) + extra : 0;
465 }
466
467 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
468 {
469 int cnt;
470 r300ContextPtr r300 = R300_CONTEXT(ctx);
471 int extra = 1;
472 cnt = r500fp_count(atom->cmd);
473 if (r300->radeon.radeonScreen->kernel_mm)
474 extra = 3;
475
476 cnt = r500fp_count(atom->cmd);
477 return cnt ? (cnt * 4) + extra : 0;
478 }
479
480 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
481 do { \
482 r300->hw.ATOM.cmd_size = (SZ); \
483 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
484 r300->hw.ATOM.name = #ATOM; \
485 r300->hw.ATOM.idx = (IDX); \
486 r300->hw.ATOM.check = check_##CHK; \
487 r300->hw.ATOM.dirty = GL_FALSE; \
488 r300->radeon.hw.max_state_size += (SZ); \
489 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
490 } while (0)
491 /**
492 * Allocate memory for the command buffer and initialize the state atom
493 * list. Note that the initial hardware state is set by r300InitState().
494 */
495 void r300InitCmdBuf(r300ContextPtr r300)
496 {
497 int mtu;
498 int has_tcl;
499 int is_r500 = 0;
500
501 has_tcl = r300->options.hw_tcl_enabled;
502
503 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
504 is_r500 = 1;
505
506 r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
507
508 mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
509 if (RADEON_DEBUG & RADEON_TEXTURE) {
510 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
511 }
512
513 /* Setup the atom linked list */
514 make_empty_list(&r300->radeon.hw.atomlist);
515 r300->radeon.hw.atomlist.name = "atom-list";
516
517 /* Initialize state atoms */
518 ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
519 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
520 ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
521 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
522 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
523 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
524 if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
525 ALLOC_STATE(vap_index_offset, always, 2, 0);
526 r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
527 r300->hw.vap_index_offset.cmd[1] = 0;
528 }
529 ALLOC_STATE(vte, always, 3, 0);
530 r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
531 ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
532 r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
533 ALLOC_STATE(vap_cntl_status, always, 2, 0);
534 r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
535 ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
536 r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
537 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
538 ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
539 r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
540 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
541 ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
542 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
543 ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
544 r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
545
546 if (has_tcl) {
547 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
548 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
549 ALLOC_STATE(vap_clip, always, 5, 0);
550 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
551 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
552 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
553 }
554
555 ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
556 r300->hw.vof.cmd[R300_VOF_CMD_0] =
557 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
558
559 if (has_tcl) {
560 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
561 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
562 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
563 }
564
565 ALLOC_STATE(gb_enable, always, 2, 0);
566 r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
567 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
568 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
569 } else {
570 ALLOC_STATE(gb_misc, never, R300_GB_MISC_CMDSIZE, 0);
571 }
572 r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
573 ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
574 r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
575 ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
576 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
577 ALLOC_STATE(ga_point_s0, always, 5, 0);
578 r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
579 ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
580 r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
581 ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
582 r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
583 ALLOC_STATE(ga_point_minmax, always, 4, 0);
584 r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
585 ALLOC_STATE(lcntl, always, 2, 0);
586 r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
587 ALLOC_STATE(ga_line_stipple, always, 4, 0);
588 r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
589 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
590 ALLOC_STATE(shade, always, 2, 0);
591 } else {
592 ALLOC_STATE(shade, never, 2, 0);
593 }
594 r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
595 ALLOC_STATE(shade2, always, 4, 0);
596 r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
597 ALLOC_STATE(polygon_mode, always, 4, 0);
598 r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
599 ALLOC_STATE(fogp, always, 3, 0);
600 r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
601 ALLOC_STATE(zbias_cntl, always, 2, 0);
602 r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
603 ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
604 r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
605 cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
606 ALLOC_STATE(occlusion_cntl, always, 2, 0);
607 r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
608 ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
609 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
610 ALLOC_STATE(su_depth_scale, always, 3, 0);
611 r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
612 ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
613 r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
614 if (is_r500) {
615 ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0);
616 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
617 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
618 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
619 } else {
620 ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0);
621 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
622 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
623 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
624 }
625 ALLOC_STATE(sc_hyperz, always, 3, 0);
626 r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
627 ALLOC_STATE(sc_screendoor, always, 2, 0);
628 r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
629 ALLOC_STATE(us_out_fmt, always, 6, 0);
630 r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
631
632 if (is_r500) {
633 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
634 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
635 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
636 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
637 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
638 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
639
640 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
641 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
642 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
643 if (r300->radeon.radeonScreen->kernel_mm)
644 r300->hw.r500fp.emit = emit_r500fp;
645
646 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
647 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
648 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
649 if (r300->radeon.radeonScreen->kernel_mm)
650 r300->hw.r500fp_const.emit = emit_r500fp;
651 } else {
652 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
653 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
654 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
655
656 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
657 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
658
659 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
660 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
661 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
662 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
663 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
664 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
665 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
666 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
667 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
668 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
669 }
670 ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
671 r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
672 ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
673 r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
674 ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
675 r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
676 ALLOC_STATE(fg_depth_src, always, 2, 0);
677 r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
678 ALLOC_STATE(rb3d_cctl, always, 2, 0);
679 r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
680 ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
681 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
682 ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
683 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
684 if (is_r500) {
685 ALLOC_STATE(blend_color, always, 3, 0);
686 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
687 } else {
688 ALLOC_STATE(blend_color, always, 2, 0);
689 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
690 }
691 ALLOC_STATE(rop, always, 2, 0);
692 r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
693 ALLOC_STATE(cb, cb_offset, R300_CB_CMDSIZE, 0);
694 r300->hw.cb.emit = &emit_cb_offset;
695 ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
696 r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
697 ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
698 r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
699 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350) {
700 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
701 } else {
702 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);
703 }
704 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
705 ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
706 r300->hw.zs.cmd[R300_ZS_CMD_0] =
707 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
708 if (is_r500) {
709 if (r300->radeon.radeonScreen->kernel_mm)
710 ALLOC_STATE(zsb, always, R300_ZSB_CMDSIZE, 0);
711 else
712 ALLOC_STATE(zsb, never, R300_ZSB_CMDSIZE, 0);
713 r300->hw.zsb.cmd[R300_ZSB_CMD_0] =
714 cmdpacket0(r300->radeon.radeonScreen, R500_ZB_STENCILREFMASK_BF, 1);
715 }
716
717 ALLOC_STATE(zstencil_format, always, 5, 0);
718 r300->hw.zstencil_format.cmd[0] =
719 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
720 r300->hw.zstencil_format.emit = emit_zstencil_format;
721
722 ALLOC_STATE(zb, zb_offset, R300_ZB_CMDSIZE, 0);
723 r300->hw.zb.emit = emit_zb_offset;
724 ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
725 r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
726 ALLOC_STATE(zb_zmask, always, 3, 0);
727 r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
728 ALLOC_STATE(zb_hiz_offset, always, 2, 0);
729 r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
730 ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
731 r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
732
733 /* VPU only on TCL */
734 if (has_tcl) {
735 int i;
736 if (r300->radeon.radeonScreen->kernel_mm) {
737 ALLOC_STATE(vap_flush, always, 10, 0);
738 /* flush processing vertices */
739 r300->hw.vap_flush.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
740 r300->hw.vap_flush.cmd[1] = 0;
741 r300->hw.vap_flush.cmd[2] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DSTCACHE_CTLSTAT, 1);
742 r300->hw.vap_flush.cmd[3] = R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D;
743 r300->hw.vap_flush.cmd[4] = cmdpacket0(r300->radeon.radeonScreen, RADEON_WAIT_UNTIL, 1);
744 r300->hw.vap_flush.cmd[5] = RADEON_WAIT_3D_IDLECLEAN;
745 r300->hw.vap_flush.cmd[6] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
746 r300->hw.vap_flush.cmd[7] = 0xffffff;
747 r300->hw.vap_flush.cmd[8] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
748 r300->hw.vap_flush.cmd[9] = 0;
749 } else {
750 ALLOC_STATE(vap_flush, never, 10, 0);
751 }
752
753
754 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
755 r300->hw.vpi.cmd[0] =
756 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
757 if (r300->radeon.radeonScreen->kernel_mm)
758 r300->hw.vpi.emit = emit_vpu;
759
760 if (is_r500) {
761 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
762 r300->hw.vpp.cmd[0] =
763 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
764 if (r300->radeon.radeonScreen->kernel_mm)
765 r300->hw.vpp.emit = emit_vpu;
766
767 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
768 r300->hw.vps.cmd[0] =
769 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
770 if (r300->radeon.radeonScreen->kernel_mm)
771 r300->hw.vps.emit = emit_vpu;
772
773 for (i = 0; i < 6; i++) {
774 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
775 r300->hw.vpucp[i].cmd[0] =
776 cmdvpu(r300->radeon.radeonScreen,
777 R500_PVS_UCP_START + i, 1);
778 if (r300->radeon.radeonScreen->kernel_mm)
779 r300->hw.vpucp[i].emit = emit_vpu;
780 }
781 } else {
782 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
783 r300->hw.vpp.cmd[0] =
784 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
785 if (r300->radeon.radeonScreen->kernel_mm)
786 r300->hw.vpp.emit = emit_vpu;
787
788 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
789 r300->hw.vps.cmd[0] =
790 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
791 if (r300->radeon.radeonScreen->kernel_mm)
792 r300->hw.vps.emit = emit_vpu;
793
794 for (i = 0; i < 6; i++) {
795 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
796 r300->hw.vpucp[i].cmd[0] =
797 cmdvpu(r300->radeon.radeonScreen,
798 R300_PVS_UCP_START + i, 1);
799 if (r300->radeon.radeonScreen->kernel_mm)
800 r300->hw.vpucp[i].emit = emit_vpu;
801 }
802 }
803 }
804
805 /* Textures */
806 ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
807 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
808 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
809
810 ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
811 r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
812 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
813
814 ALLOC_STATE(tex.size, variable, mtu + 1, 0);
815 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
816
817 ALLOC_STATE(tex.format, variable, mtu + 1, 0);
818 r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
819 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
820
821 ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
822 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
823
824 ALLOC_STATE(tex.offset, tex_offsets, 1, 0);
825 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
826 cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
827 r300->hw.tex.offset.emit = &emit_tex_offsets;
828
829 ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
830 r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
831 cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
832
833 ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
834 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
835 cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
836
837 radeon_init_query_stateobj(&r300->radeon, R300_QUERYOBJ_CMDSIZE);
838 if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) {
839 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RV530_FG_ZBREG_DEST, 1);
840 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL;
841 } else {
842 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_REG_DEST, 1);
843 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = R300_RASTER_PIPE_SELECT_ALL;
844 }
845 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZPASS_DATA, 1);
846 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_1] = 0;
847
848 r300->radeon.hw.is_dirty = GL_TRUE;
849 r300->radeon.hw.all_dirty = GL_TRUE;
850
851 rcommonInitCmdBuf(&r300->radeon);
852 }