src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #include "main/glheader.h"
  37 #include "main/state.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "swrast/swrast.h"
  43
  44 #include "drm.h"
  45 #include "radeon_drm.h"
  46
  47 #include "r300_context.h"
  48 #include "r300_reg.h"
  49 #include "r300_cmdbuf.h"
  50 #include "r300_emit.h"
  51 #include "radeon_bocs_wrapper.h"
  52 #include "radeon_mipmap_tree.h"
  53 #include "r300_state.h"
  54 #include "radeon_queryobj.h"
  55
  56 /** # of dwords reserved for additional instructions that may need to be written
  57  * during flushing.
  58  */
  59 #define SPACE_FOR_FLUSHING      4
  60
  61 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
  62 {
  63     if (r300->radeon.radeonScreen->kernel_mm) {
  64         return ((((*pkt) >> 16) & 0x3FFF) + 1);
  65     } else {
  66         drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
  67         return t->packet0.count;
  68     }
  69 }
  70
  71 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
  72 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
  73
  74 static int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
  75 {
  76         r300ContextPtr r300 = R300_CONTEXT(ctx);
  77         int cnt;
  78         int extra = 1;
  79         cnt = vpu_count(atom->cmd);
  80
  81         if (r300->radeon.radeonScreen->kernel_mm) {
  82                 extra = 5;
  83         }
  84
  85         return cnt ? (cnt * 4) + extra : 0;
  86 }
  87
  88 void r300_emit_vpu(struct r300_context *r300,
  89                    uint32_t *data,
  90                    unsigned len,
  91                    uint32_t addr)
  92 {
  93     BATCH_LOCALS(&r300->radeon);
  94
  95     BEGIN_BATCH_NO_AUTOSTATE(5 + len);
  96     OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
  97     OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
  98     OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, len-1) | RADEON_ONE_REG_WR);
  99     OUT_BATCH_TABLE(data, len);
 100     END_BATCH();
 101 }
 102
 103 static void emit_vpu_state(GLcontext *ctx, struct radeon_state_atom * atom)
 104 {
 105     r300ContextPtr r300 = R300_CONTEXT(ctx);
 106     drm_r300_cmd_header_t cmd;
 107     uint32_t addr, ndw;
 108
 109     cmd.u = atom->cmd[0];
 110     addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
 111     ndw = atom->check(ctx, atom);
 112
 113     r300_emit_vpu(r300, &atom->cmd[1], vpu_count(atom->cmd) * 4, addr);
 114 }
 115
 116 void r500_emit_fp(struct r300_context *r300,
 117                   uint32_t *data,
 118                   unsigned len,
 119                   uint32_t addr,
 120                   unsigned type,
 121                   unsigned clamp)
 122 {
 123     BATCH_LOCALS(&r300->radeon);
 124
 125     addr |= (type << 16);
 126     addr |= (clamp << 17);
 127
 128     BEGIN_BATCH_NO_AUTOSTATE(len + 3);
 129     OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
 130     OUT_BATCH(addr);
 131     OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, len-1) | RADEON_ONE_REG_WR);
 132     OUT_BATCH_TABLE(data, len);
 133     END_BATCH();
 134 }
 135
 136 static void emit_r500fp_atom(GLcontext *ctx, struct radeon_state_atom * atom)
 137 {
 138     r300ContextPtr r300 = R300_CONTEXT(ctx);
 139     drm_r300_cmd_header_t cmd;
 140     uint32_t addr, count;
 141     int type, clamp;
 142
 143     cmd.u = atom->cmd[0];
 144     addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
 145     type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
 146     clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
 147
 148     if (type) {
 149         count = r500fp_count(atom->cmd) * 4;
 150     } else {
 151         count = r500fp_count(atom->cmd) * 6;
 152     }
 153
 154     r500_emit_fp(r300, &atom->cmd[1], count, addr, type, clamp);
 155 }
 156
 157 static int check_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 158 {
 159         r300ContextPtr r300 = R300_CONTEXT(ctx);
 160         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 161         int dw = 0, i;
 162         if (atom->cmd[0] == CP_PACKET2) {
 163                 return dw;
 164         }
 165         for(i = 0; i < numtmus; ++i) {
 166                 radeonTexObj *t = r300->hw.textures[i];
 167                 if (!t && !r300->radeon.radeonScreen->kernel_mm) {
 168                         dw += 0;
 169                 } else if (t && t->image_override && !t->bo) {
 170                         if (!r300->radeon.radeonScreen->kernel_mm)
 171                                 dw += 2;
 172                 } else
 173                         dw += 4;
 174         }
 175         return dw;
 176 }
 177
 178 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 179 {
 180         r300ContextPtr r300 = R300_CONTEXT(ctx);
 181         BATCH_LOCALS(&r300->radeon);
 182         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 183         int i;
 184
 185         for(i = 0; i < numtmus; ++i) {
 186                 radeonTexObj *t = r300->hw.textures[i];
 187                 if (t && !t->image_override) {
 188                         BEGIN_BATCH_NO_AUTOSTATE(4);
 189                         OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 190                         OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
 191                                         RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 192                         END_BATCH();
 193                 } else if (!t) {
 194                         /* Texture unit hasn't a texture bound.
 195                          * We assign the current color buffer as a fakery to make
 196                          * KIL work on KMS (without it, the CS checker will complain).
 197                          */
 198                         if (r300->radeon.radeonScreen->kernel_mm) {
 199                                 struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
 200                                 if (rrb && rrb->bo) {
 201                                         BEGIN_BATCH_NO_AUTOSTATE(4);
 202                                         OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 203                                         OUT_BATCH_RELOC(0, rrb->bo, 0,
 204                                                         RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 205                                         END_BATCH();
 206                                 }
 207                         }
 208                 } else { /* override cases */
 209                         if (t->bo) {
 210                                 BEGIN_BATCH_NO_AUTOSTATE(4);
 211                                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 212                                 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
 213                                                 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 214                                 END_BATCH();
 215                         } else if (!r300->radeon.radeonScreen->kernel_mm) {
 216                                 BEGIN_BATCH_NO_AUTOSTATE(2);
 217                                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 218                                 OUT_BATCH(t->override_offset);
 219                                 END_BATCH();
 220                         } else {
 221                                 /* Texture unit hasn't a texture bound nothings to do */
 222                         }
 223                 }
 224         }
 225 }
 226
 227 void r300_emit_scissor(GLcontext *ctx)
 228 {
 229         r300ContextPtr r300 = R300_CONTEXT(ctx);
 230         BATCH_LOCALS(&r300->radeon);
 231     unsigned x1, y1, x2, y2;
 232         struct radeon_renderbuffer *rrb;
 233
 234     if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 235         return;
 236     }
 237         rrb = radeon_get_colorbuffer(&r300->radeon);
 238         if (!rrb || !rrb->bo) {
 239                 fprintf(stderr, "no rrb\n");
 240                 return;
 241         }
 242     if (r300->radeon.state.scissor.enabled) {
 243         x1 = r300->radeon.state.scissor.rect.x1;
 244         y1 = r300->radeon.state.scissor.rect.y1;
 245         x2 = r300->radeon.state.scissor.rect.x2;
 246         y2 = r300->radeon.state.scissor.rect.y2;
 247     } else {
 248         x1 = 0;
 249         y1 = 0;
 250         x2 = rrb->base.Width - 1;
 251         y2 = rrb->base.Height - 1;
 252     }
 253     if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
 254         x1 += R300_SCISSORS_OFFSET;
 255         y1 += R300_SCISSORS_OFFSET;
 256         x2 += R300_SCISSORS_OFFSET;
 257         y2 += R300_SCISSORS_OFFSET;
 258     }
 259     BEGIN_BATCH_NO_AUTOSTATE(3);
 260     OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 261     OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
 262     OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
 263     END_BATCH();
 264 }
 265 static int check_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 266 {
 267         r300ContextPtr r300 = R300_CONTEXT(ctx);
 268         uint32_t dw = 6 + 3 + 16;
 269         if (r300->radeon.radeonScreen->kernel_mm)
 270                 dw += 2;
 271         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 272                 dw -= 3 + 16;
 273         }
 274         return dw;
 275 }
 276
 277 static void emit_scissor(struct r300_context *r300,
 278                          unsigned width,
 279                          unsigned height)
 280 {
 281     int i;
 282     BATCH_LOCALS(&r300->radeon);
 283     if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 284         BEGIN_BATCH_NO_AUTOSTATE(3);
 285         OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 286         OUT_BATCH(0);
 287         OUT_BATCH(((width - 1) << R300_SCISSORS_X_SHIFT) |
 288                 ((height - 1) << R300_SCISSORS_Y_SHIFT));
 289         END_BATCH();
 290         BEGIN_BATCH_NO_AUTOSTATE(16);
 291         for (i = 0; i < 4; i++) {
 292             OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 293             OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
 294             OUT_BATCH(((width - 1) << R300_CLIPRECT_X_SHIFT) | ((height - 1) << R300_CLIPRECT_Y_SHIFT));
 295         }
 296         OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 297         OUT_BATCH(0xAAAA);
 298         OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 299         OUT_BATCH(0xffffff);
 300         END_BATCH();
 301     } else {
 302         BEGIN_BATCH_NO_AUTOSTATE(3);
 303         OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 304         OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
 305                 (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
 306         OUT_BATCH(((width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
 307                 ((height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
 308         END_BATCH();
 309         BEGIN_BATCH_NO_AUTOSTATE(16);
 310         for (i = 0; i < 4; i++) {
 311             OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 312             OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
 313             OUT_BATCH(((R300_SCISSORS_OFFSET + width - 1) << R300_CLIPRECT_X_SHIFT) |
 314                         ((R300_SCISSORS_OFFSET + height - 1) << R300_CLIPRECT_Y_SHIFT));
 315         }
 316         OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 317         OUT_BATCH(0xAAAA);
 318         OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 319         OUT_BATCH(0xffffff);
 320         END_BATCH();
 321     }
 322 }
 323
 324 void r300_emit_cb_setup(struct r300_context *r300,
 325                         struct radeon_bo *bo,
 326                         uint32_t offset,
 327                         GLuint format,
 328                         unsigned cpp,
 329                         unsigned pitch)
 330 {
 331     BATCH_LOCALS(&r300->radeon);
 332     uint32_t cbpitch = pitch / cpp;
 333     uint32_t dw = 6;
 334
 335     assert(offset % 32 == 0);
 336
 337     switch (format) {
 338         case MESA_FORMAT_RGB565:
 339             assert(_mesa_little_endian());
 340             cbpitch |= R300_COLOR_FORMAT_RGB565;
 341             break;
 342         case MESA_FORMAT_RGB565_REV:
 343             assert(!_mesa_little_endian());
 344             cbpitch |= R300_COLOR_FORMAT_RGB565;
 345             break;
 346         case MESA_FORMAT_ARGB4444:
 347             assert(_mesa_little_endian());
 348             cbpitch |= R300_COLOR_FORMAT_ARGB4444;
 349             break;
 350         case MESA_FORMAT_ARGB4444_REV:
 351             assert(!_mesa_little_endian());
 352             cbpitch |= R300_COLOR_FORMAT_ARGB4444;
 353             break;
 354         case MESA_FORMAT_ARGB1555:
 355             assert(_mesa_little_endian());
 356             cbpitch |= R300_COLOR_FORMAT_ARGB1555;
 357             break;
 358         case MESA_FORMAT_ARGB1555_REV:
 359             assert(!_mesa_little_endian());
 360             cbpitch |= R300_COLOR_FORMAT_ARGB1555;
 361             break;
 362         default:
 363             if (cpp == 4) {
 364                 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
 365             } else {
 366                 _mesa_problem(r300->radeon.glCtx, "unexpected format in emit_cb_offset()");;
 367             }
 368             break;
 369     }
 370
 371     if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 372         cbpitch |= R300_COLOR_TILE_ENABLE;
 373
 374     if (r300->radeon.radeonScreen->kernel_mm)
 375         dw += 2;
 376
 377     BEGIN_BATCH_NO_AUTOSTATE(dw);
 378     OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
 379     OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 380     OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
 381     if (!r300->radeon.radeonScreen->kernel_mm)
 382         OUT_BATCH(cbpitch);
 383     else
 384         OUT_BATCH_RELOC(cbpitch, bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 385     END_BATCH();
 386 }
 387
 388 static void emit_cb_offset_atom(GLcontext *ctx, struct radeon_state_atom * atom)
 389 {
 390     r300ContextPtr r300 = R300_CONTEXT(ctx);
 391     struct radeon_renderbuffer *rrb;
 392     uint32_t offset = r300->radeon.state.color.draw_offset;
 393
 394     rrb = radeon_get_colorbuffer(&r300->radeon);
 395     if (!rrb || !rrb->bo) {
 396         fprintf(stderr, "no rrb\n");
 397         return;
 398     }
 399
 400     if (RADEON_DEBUG & RADEON_STATE)
 401         fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
 402
 403     r300_emit_cb_setup(r300, rrb->bo, offset, rrb->base.Format, rrb->cpp, rrb->pitch);
 404
 405     if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 406         emit_scissor(r300, rrb->base.Width, rrb->base.Height);
 407     }
 408 }
 409
 410 static int check_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 411 {
 412         r300ContextPtr r300 = R300_CONTEXT(ctx);
 413         uint32_t dw;
 414         dw = 6;
 415         if (r300->radeon.radeonScreen->kernel_mm)
 416                 dw += 2;
 417         return dw;
 418 }
 419
 420 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 421 {
 422         r300ContextPtr r300 = R300_CONTEXT(ctx);
 423         BATCH_LOCALS(&r300->radeon);
 424         struct radeon_renderbuffer *rrb;
 425         uint32_t zbpitch;
 426         uint32_t dw = atom->check(ctx, atom);
 427
 428         rrb = radeon_get_depthbuffer(&r300->radeon);
 429         if (!rrb)
 430                 return;
 431
 432         zbpitch = (rrb->pitch / rrb->cpp);
 433         if (!r300->radeon.radeonScreen->kernel_mm) {
 434             if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
 435                 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
 436            }
 437             if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 438                 zbpitch |= R300_DEPTHMICROTILE_TILED;
 439             }
 440         }
 441
 442         BEGIN_BATCH_NO_AUTOSTATE(dw);
 443         OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 444         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 445         OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
 446         if (!r300->radeon.radeonScreen->kernel_mm)
 447             OUT_BATCH(zbpitch);
 448         else
 449             OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 450         END_BATCH();
 451 }
 452
 453 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
 454 {
 455         r300ContextPtr r300 = R300_CONTEXT(ctx);
 456         BATCH_LOCALS(&r300->radeon);
 457         struct radeon_renderbuffer *rrb;
 458         uint32_t format = 0;
 459
 460         rrb = radeon_get_depthbuffer(&r300->radeon);
 461         if (!rrb)
 462           format = 0;
 463         else {
 464           if (rrb->cpp == 2)
 465             format = R300_DEPTHFORMAT_16BIT_INT_Z;
 466           else if (rrb->cpp == 4)
 467             format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
 468         }
 469
 470         BEGIN_BATCH_NO_AUTOSTATE(atom->cmd_size);
 471         OUT_BATCH(atom->cmd[0]);
 472         atom->cmd[1] &= ~0xf;
 473         atom->cmd[1] |= format;
 474         OUT_BATCH(atom->cmd[1]);
 475         OUT_BATCH(atom->cmd[2]);
 476         OUT_BATCH(atom->cmd[3]);
 477         OUT_BATCH(atom->cmd[4]);
 478         END_BATCH();
 479 }
 480
 481 static int check_never(GLcontext *ctx, struct radeon_state_atom *atom)
 482 {
 483    return 0;
 484 }
 485
 486 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 487 {
 488         return atom->cmd_size;
 489 }
 490
 491 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
 492 {
 493         r300ContextPtr r300 = R300_CONTEXT(ctx);
 494         int cnt;
 495         if (atom->cmd[0] == CP_PACKET2) {
 496                 return 0;
 497         }
 498         cnt = packet0_count(r300, atom->cmd);
 499         return cnt ? cnt + 1 : 0;
 500 }
 501
 502 static int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
 503 {
 504         int cnt;
 505         r300ContextPtr r300 = R300_CONTEXT(ctx);
 506         int extra = 1;
 507         cnt = r500fp_count(atom->cmd);
 508         if (r300->radeon.radeonScreen->kernel_mm)
 509                 extra = 3;
 510
 511         return cnt ? (cnt * 6) + extra : 0;
 512 }
 513
 514 static int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
 515 {
 516         int cnt;
 517         r300ContextPtr r300 = R300_CONTEXT(ctx);
 518         int extra = 1;
 519         cnt = r500fp_count(atom->cmd);
 520         if (r300->radeon.radeonScreen->kernel_mm)
 521                 extra = 3;
 522
 523         cnt = r500fp_count(atom->cmd);
 524         return cnt ? (cnt * 4) + extra : 0;
 525 }
 526
 527 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )                               \
 528    do {                                                                 \
 529       r300->hw.ATOM.cmd_size = (SZ);                                    \
 530       r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 531       r300->hw.ATOM.name = #ATOM;                                       \
 532       r300->hw.ATOM.idx = (IDX);                                        \
 533       r300->hw.ATOM.check = check_##CHK;                                \
 534       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 535       r300->radeon.hw.max_state_size += (SZ);                                   \
 536       insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM);                \
 537    } while (0)
 538 /**
 539  * Allocate memory for the command buffer and initialize the state atom
 540  * list. Note that the initial hardware state is set by r300InitState().
 541  */
 542 void r300InitCmdBuf(r300ContextPtr r300)
 543 {
 544         int mtu;
 545         int has_tcl;
 546         int is_r500 = 0;
 547
 548         has_tcl = r300->options.hw_tcl_enabled;
 549
 550         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 551                 is_r500 = 1;
 552
 553         r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
 554
 555         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 556         if (RADEON_DEBUG & RADEON_TEXTURE) {
 557                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 558         }
 559
 560         /* Setup the atom linked list */
 561         make_empty_list(&r300->radeon.hw.atomlist);
 562         r300->radeon.hw.atomlist.name = "atom-list";
 563
 564         /* Initialize state atoms */
 565         ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
 566         r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
 567         ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
 568         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 569         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
 570         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
 571         if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
 572             ALLOC_STATE(vap_index_offset, always, 2, 0);
 573             r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
 574             r300->hw.vap_index_offset.cmd[1] = 0;
 575         }
 576         ALLOC_STATE(vte, always, 3, 0);
 577         r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
 578         ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
 579         r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
 580         ALLOC_STATE(vap_cntl_status, always, 2, 0);
 581         r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
 582         ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
 583         r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
 584             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
 585         ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
 586         r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
 587             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 588         ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
 589         r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
 590         ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 591         r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 592
 593         if (has_tcl) {
 594                 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 595                 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
 596                 ALLOC_STATE(vap_clip, always, 5, 0);
 597                 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
 598                 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
 599                 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
 600         }
 601
 602         ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
 603         r300->hw.vof.cmd[R300_VOF_CMD_0] =
 604             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
 605
 606         if (has_tcl) {
 607                 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
 608                 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
 609                     cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
 610         }
 611
 612         ALLOC_STATE(gb_enable, always, 2, 0);
 613         r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
 614         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 615                 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
 616         } else {
 617                 ALLOC_STATE(gb_misc, never, R300_GB_MISC_CMDSIZE, 0);
 618         }
 619         r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
 620         ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
 621         r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
 622         ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
 623         r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
 624         ALLOC_STATE(ga_point_s0, always, 5, 0);
 625         r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
 626         ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
 627         r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
 628         ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
 629         r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
 630         ALLOC_STATE(ga_point_minmax, always, 4, 0);
 631         r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
 632         ALLOC_STATE(lcntl, always, 2, 0);
 633         r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
 634         ALLOC_STATE(ga_line_stipple, always, 4, 0);
 635         r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
 636         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 637                 ALLOC_STATE(shade, always, 2, 0);
 638         } else {
 639                 ALLOC_STATE(shade, never, 2, 0);
 640         }
 641         r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
 642         ALLOC_STATE(shade2, always, 4, 0);
 643         r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
 644         ALLOC_STATE(polygon_mode, always, 4, 0);
 645         r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
 646         ALLOC_STATE(fogp, always, 3, 0);
 647         r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
 648         ALLOC_STATE(zbias_cntl, always, 2, 0);
 649         r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
 650         ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
 651         r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
 652             cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 653         ALLOC_STATE(occlusion_cntl, always, 2, 0);
 654         r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
 655         ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
 656         r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
 657         ALLOC_STATE(su_depth_scale, always, 3, 0);
 658         r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
 659         ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
 660         r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
 661         if (is_r500) {
 662                 ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0);
 663                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
 664                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 665                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
 666         } else {
 667                 ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0);
 668                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
 669                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 670                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
 671         }
 672         ALLOC_STATE(sc_hyperz, always, 3, 0);
 673         r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
 674         ALLOC_STATE(sc_screendoor, always, 2, 0);
 675         r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 676         ALLOC_STATE(us_out_fmt, always, 6, 0);
 677         r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
 678
 679         if (is_r500) {
 680                 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
 681                 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
 682                 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
 683                 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
 684                 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
 685                 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
 686
 687                 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
 688                 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
 689                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
 690                 if (r300->radeon.radeonScreen->kernel_mm)
 691                         r300->hw.r500fp.emit = emit_r500fp_atom;
 692
 693                 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
 694                 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
 695                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
 696                 if (r300->radeon.radeonScreen->kernel_mm)
 697                         r300->hw.r500fp_const.emit = emit_r500fp_atom;
 698         } else {
 699                 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 700                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
 701                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
 702
 703                 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
 704                 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
 705
 706                 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
 707                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
 708                 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
 709                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
 710                 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
 711                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
 712                 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
 713                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
 714                 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
 715                 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
 716         }
 717         ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
 718         r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
 719         ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
 720         r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
 721         ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
 722         r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
 723         ALLOC_STATE(fg_depth_src, always, 2, 0);
 724         r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
 725         ALLOC_STATE(rb3d_cctl, always, 2, 0);
 726         r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
 727         ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
 728         r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
 729         ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
 730         r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
 731         if (is_r500) {
 732                 ALLOC_STATE(blend_color, always, 3, 0);
 733                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
 734         } else {
 735                 ALLOC_STATE(blend_color, always, 2, 0);
 736                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
 737         }
 738         ALLOC_STATE(rop, always, 2, 0);
 739         r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
 740         ALLOC_STATE(cb, cb_offset, R300_CB_CMDSIZE, 0);
 741         r300->hw.cb.emit = &emit_cb_offset_atom;
 742         ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
 743         r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
 744         ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 745         r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
 746         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350) {
 747                 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
 748         } else {
 749                 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);
 750         }
 751         r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
 752         ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
 753         r300->hw.zs.cmd[R300_ZS_CMD_0] =
 754             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
 755         if (is_r500) {
 756                 if (r300->radeon.radeonScreen->kernel_mm)
 757                         ALLOC_STATE(zsb, always, R300_ZSB_CMDSIZE, 0);
 758                 else
 759                         ALLOC_STATE(zsb, never, R300_ZSB_CMDSIZE, 0);
 760                 r300->hw.zsb.cmd[R300_ZSB_CMD_0] =
 761                         cmdpacket0(r300->radeon.radeonScreen, R500_ZB_STENCILREFMASK_BF, 1);
 762         }
 763
 764         ALLOC_STATE(zstencil_format, always, 5, 0);
 765         r300->hw.zstencil_format.cmd[0] =
 766             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
 767         r300->hw.zstencil_format.emit = emit_zstencil_format;
 768
 769         ALLOC_STATE(zb, zb_offset, R300_ZB_CMDSIZE, 0);
 770         r300->hw.zb.emit = emit_zb_offset;
 771         ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
 772         r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
 773         ALLOC_STATE(zb_zmask, always, 3, 0);
 774         r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
 775         ALLOC_STATE(zb_hiz_offset, always, 2, 0);
 776         r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
 777         ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
 778         r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
 779
 780         /* VPU only on TCL */
 781         if (has_tcl) {
 782                 int i;
 783                 if (r300->radeon.radeonScreen->kernel_mm) {
 784                         ALLOC_STATE(vap_flush, always, 10, 0);
 785                         /* flush processing vertices */
 786                         r300->hw.vap_flush.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 787                         r300->hw.vap_flush.cmd[1] = 0;
 788                         r300->hw.vap_flush.cmd[2] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DSTCACHE_CTLSTAT, 1);
 789                         r300->hw.vap_flush.cmd[3] = R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D;
 790                         r300->hw.vap_flush.cmd[4] = cmdpacket0(r300->radeon.radeonScreen, RADEON_WAIT_UNTIL, 1);
 791                         r300->hw.vap_flush.cmd[5] = RADEON_WAIT_3D_IDLECLEAN;
 792                         r300->hw.vap_flush.cmd[6] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 793                         r300->hw.vap_flush.cmd[7] = 0xffffff;
 794                         r300->hw.vap_flush.cmd[8] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 795                         r300->hw.vap_flush.cmd[9] = 0;
 796                 } else {
 797                         ALLOC_STATE(vap_flush, never, 10, 0);
 798                 }
 799
 800
 801                 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 802                 r300->hw.vpi.cmd[0] =
 803                         cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
 804                 if (r300->radeon.radeonScreen->kernel_mm)
 805                         r300->hw.vpi.emit = emit_vpu_state;
 806
 807                 if (is_r500) {
 808                         ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 809                         r300->hw.vpp.cmd[0] =
 810                                 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
 811                         if (r300->radeon.radeonScreen->kernel_mm)
 812                                 r300->hw.vpp.emit = emit_vpu_state;
 813
 814                         ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 815                         r300->hw.vps.cmd[0] =
 816                                 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
 817                         if (r300->radeon.radeonScreen->kernel_mm)
 818                                 r300->hw.vps.emit = emit_vpu_state;
 819
 820                         for (i = 0; i < 6; i++) {
 821                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 822                                 r300->hw.vpucp[i].cmd[0] =
 823                                         cmdvpu(r300->radeon.radeonScreen,
 824                                                         R500_PVS_UCP_START + i, 1);
 825                                 if (r300->radeon.radeonScreen->kernel_mm)
 826                                         r300->hw.vpucp[i].emit = emit_vpu_state;
 827                         }
 828                 } else {
 829                         ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 830                         r300->hw.vpp.cmd[0] =
 831                                 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
 832                         if (r300->radeon.radeonScreen->kernel_mm)
 833                                 r300->hw.vpp.emit = emit_vpu_state;
 834
 835                         ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 836                         r300->hw.vps.cmd[0] =
 837                                 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
 838                         if (r300->radeon.radeonScreen->kernel_mm)
 839                                 r300->hw.vps.emit = emit_vpu_state;
 840
 841                         for (i = 0; i < 6; i++) {
 842                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 843                                 r300->hw.vpucp[i].cmd[0] =
 844                                         cmdvpu(r300->radeon.radeonScreen,
 845                                                         R300_PVS_UCP_START + i, 1);
 846                                 if (r300->radeon.radeonScreen->kernel_mm)
 847                                         r300->hw.vpucp[i].emit = emit_vpu_state;
 848                         }
 849                 }
 850         }
 851
 852         /* Textures */
 853         ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
 854         r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
 855             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
 856
 857         ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
 858         r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
 859             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
 860
 861         ALLOC_STATE(tex.size, variable, mtu + 1, 0);
 862         r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
 863
 864         ALLOC_STATE(tex.format, variable, mtu + 1, 0);
 865         r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
 866             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
 867
 868         ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
 869         r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
 870
 871         ALLOC_STATE(tex.offset, tex_offsets, 1, 0);
 872         r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
 873             cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
 874         r300->hw.tex.offset.emit = &emit_tex_offsets;
 875
 876         ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
 877         r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
 878             cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
 879
 880         ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
 881         r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
 882             cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
 883
 884         radeon_init_query_stateobj(&r300->radeon, R300_QUERYOBJ_CMDSIZE);
 885         if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 886                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RV530_FG_ZBREG_DEST, 1);
 887                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL;
 888         } else {
 889                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_REG_DEST, 1);
 890                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = R300_RASTER_PIPE_SELECT_ALL;
 891         }
 892         r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZPASS_DATA, 1);
 893         r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_1] = 0;
 894
 895         r300->radeon.hw.is_dirty = GL_TRUE;
 896         r300->radeon.hw.all_dirty = GL_TRUE;
 897
 898         rcommonInitCmdBuf(&r300->radeon);
 899 }