src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #include "main/glheader.h"
  37 #include "main/state.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "swrast/swrast.h"
  43
  44 #include "drm.h"
  45 #include "radeon_drm.h"
  46
  47 #include "radeon_buffer.h"
  48 #include "radeon_ioctl.h"
  49 #include "r300_context.h"
  50 #include "r300_ioctl.h"
  51 #include "radeon_reg.h"
  52 #include "r300_reg.h"
  53 #include "r300_cmdbuf.h"
  54 #include "r300_emit.h"
  55 #include "r300_mipmap_tree.h"
  56 #include "r300_state.h"
  57 #include "radeon_cs_legacy.h"
  58
  59 // Set this to 1 for extremely verbose debugging of command buffers
  60 #define DEBUG_CMDBUF            0
  61
  62 /** # of dwords reserved for additional instructions that may need to be written
  63  * during flushing.
  64  */
  65 #define SPACE_FOR_FLUSHING      4
  66
  67 /**
  68  * Send the current command buffer via ioctl to the hardware.
  69  */
  70 int r300FlushCmdBufLocked(r300ContextPtr r300, const char *caller)
  71 {
  72         int ret;
  73
  74         if (r300->cmdbuf.flushing) {
  75                 fprintf(stderr, "Recursive call into r300FlushCmdBufLocked!\n");
  76                 exit(-1);
  77         }
  78         r300->cmdbuf.flushing = 1;
  79     ret = radeon_cs_emit(r300->cmdbuf.cs);
  80     radeon_cs_erase(r300->cmdbuf.cs);
  81         r300->cmdbuf.flushing = 0;
  82         return ret;
  83 }
  84
  85 int r300FlushCmdBuf(r300ContextPtr r300, const char *caller)
  86 {
  87         int ret;
  88
  89         LOCK_HARDWARE(&r300->radeon);
  90         ret = r300FlushCmdBufLocked(r300, caller);
  91         UNLOCK_HARDWARE(&r300->radeon);
  92
  93         if (ret) {
  94                 fprintf(stderr, "drmRadeonCmdBuffer: %d\n", ret);
  95                 _mesa_exit(ret);
  96         }
  97
  98         return ret;
  99 }
 100
 101 /**
 102  * Make sure that enough space is available in the command buffer
 103  * by flushing if necessary.
 104  *
 105  * \param dwords The number of dwords we need to be free on the command buffer
 106  */
 107 void r300EnsureCmdBufSpace(r300ContextPtr r300, int dwords, const char *caller)
 108 {
 109         assert(dwords < r300->cmdbuf.size);
 110
 111         if ((r300->cmdbuf.cs->cdw + dwords + 128) > r300->cmdbuf.size ||
 112         radeon_cs_need_flush(r300->cmdbuf.cs)) {
 113                 r300FlushCmdBuf(r300, caller);
 114     }
 115 }
 116
 117 void r300BeginBatch(r300ContextPtr r300, int n,
 118                     int dostate,
 119                     const char *file,
 120                     const char *function,
 121                     int line)
 122 {
 123         r300EnsureCmdBufSpace(r300, n, function);
 124         if (!r300->cmdbuf.cs->cdw && dostate) {
 125                 if (RADEON_DEBUG & DEBUG_IOCTL)
 126                         fprintf(stderr, "Reemit state after flush (from %s)\n", function);
 127                 r300EmitState(r300);
 128         }
 129     radeon_cs_begin(r300->cmdbuf.cs, n, file, function, line);
 130 }
 131
 132 static void r300PrintStateAtom(r300ContextPtr r300,
 133                                struct r300_state_atom *state)
 134 {
 135         int i;
 136         int dwords = (*state->check) (r300, state);
 137
 138         fprintf(stderr, "  emit %s %d/%d\n", state->name, dwords, state->cmd_size);
 139
 140         if (RADEON_DEBUG & DEBUG_VERBOSE) {
 141                 for (i = 0; i < dwords; i++) {
 142                         fprintf(stderr, "      %s[%d]: %08x\n",
 143                                 state->name, i, state->cmd[i]);
 144                 }
 145         }
 146 }
 147
 148 /**
 149  * Emit all atoms with a dirty field equal to dirty.
 150  *
 151  * The caller must have ensured that there is enough space in the command
 152  * buffer.
 153  */
 154 static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty)
 155 {
 156         BATCH_LOCALS(r300);
 157         struct r300_state_atom *atom;
 158         int dwords;
 159
 160         BEGIN_BATCH_NO_AUTOSTATE(4);
 161         OUT_BATCH(cmdwait(R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 162         OUT_BATCH(cmdpacket0(R300_TX_INVALTAGS, 1));
 163         OUT_BATCH(R300_TX_FLUSH);
 164         OUT_BATCH(cmdpacify());
 165         END_BATCH();
 166
 167         /* Emit actual atoms */
 168         foreach(atom, &r300->hw.atomlist) {
 169                 if ((atom->dirty || r300->hw.all_dirty) == dirty) {
 170                         dwords = (*atom->check) (r300, atom);
 171                         if (dwords) {
 172                                 if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
 173                                         r300PrintStateAtom(r300, atom);
 174                                 }
 175                                 if (atom->emit) {
 176                                         (*atom->emit)(r300);
 177                                 } else {
 178                                         BEGIN_BATCH_NO_AUTOSTATE(dwords);
 179                                         OUT_BATCH_TABLE(atom->cmd, dwords);
 180                                         END_BATCH();
 181                                 }
 182                                 atom->dirty = GL_FALSE;
 183                         } else {
 184                                 if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
 185                                         fprintf(stderr, "  skip state %s\n",
 186                                                 atom->name);
 187                                 }
 188                         }
 189                 }
 190         }
 191
 192         COMMIT_BATCH();
 193 }
 194
 195 /**
 196  * Copy dirty hardware state atoms into the command buffer.
 197  *
 198  * We also copy out clean state if we're at the start of a buffer. That makes
 199  * it easy to recover from lost contexts.
 200  */
 201 void r300EmitState(r300ContextPtr r300)
 202 {
 203         if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_PRIMS))
 204                 fprintf(stderr, "%s\n", __FUNCTION__);
 205
 206         if (r300->cmdbuf.cs->cdw && !r300->hw.is_dirty
 207             && !r300->hw.all_dirty)
 208                 return;
 209
 210         /* To avoid going across the entire set of states multiple times, just check
 211          * for enough space for the case of emitting all state.
 212          */
 213         r300EnsureCmdBufSpace(r300, r300->hw.max_state_size, __FUNCTION__);
 214
 215         if (!r300->cmdbuf.cs->cdw) {
 216                 if (RADEON_DEBUG & DEBUG_STATE)
 217                         fprintf(stderr, "Begin reemit state\n");
 218
 219                 r300EmitAtoms(r300, GL_FALSE);
 220         }
 221
 222         if (RADEON_DEBUG & DEBUG_STATE)
 223                 fprintf(stderr, "Begin dirty state\n");
 224
 225         r300EmitAtoms(r300, GL_TRUE);
 226         r300->hw.is_dirty = GL_FALSE;
 227         r300->hw.all_dirty = GL_FALSE;
 228 }
 229
 230 #define packet0_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->packet0.count)
 231 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
 232 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
 233
 234 static void emit_tex_offsets(r300ContextPtr r300)
 235 {
 236         BATCH_LOCALS(r300);
 237         int numtmus = packet0_count(r300->hw.tex.offset.cmd);
 238
 239         if (numtmus) {
 240                 int i;
 241
 242                 for(i = 0; i < numtmus; ++i) {
 243                     BEGIN_BATCH(2);
 244                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 245                         r300TexObj *t = r300->hw.textures[i];
 246                         if (t && !t->image_override) {
 247                                 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, 0);
 248                         } else if (!t) {
 249                                 OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
 250                         } else {
 251                                 OUT_BATCH(t->override_offset);
 252                         }
 253             END_BATCH();
 254                 }
 255         }
 256 }
 257
 258 static void emit_cb_offset(r300ContextPtr r300)
 259 {
 260         BATCH_LOCALS(r300);
 261         struct radeon_renderbuffer *rrb;
 262         uint32_t cbpitch;
 263
 264         rrb = r300->radeon.state.color.rrb;
 265         if (!rrb) {
 266                 fprintf(stderr, "no rrb\n");
 267                 return;
 268         }
 269
 270         cbpitch = rrb->pitch;
 271         if (rrb->cpp == 4)
 272                 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
 273         else
 274                 cbpitch |= R300_COLOR_FORMAT_RGB565;
 275
 276         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 277                 cbpitch |= R300_COLOR_TILE_ENABLE;
 278
 279         BEGIN_BATCH(4);
 280         OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
 281         OUT_BATCH_RELOC(0, rrb->bo, 0, 0);
 282         OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
 283         OUT_BATCH(cbpitch);
 284         END_BATCH();
 285 }
 286
 287 static void emit_zb_offset(r300ContextPtr r300)
 288 {
 289         BATCH_LOCALS(r300);
 290         struct radeon_renderbuffer *rrb;
 291         uint32_t zbpitch;
 292
 293         rrb = r300->radeon.state.depth_buffer;
 294         if (!rrb)
 295                 return;
 296
 297         zbpitch = rrb->pitch;
 298     if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
 299         zbpitch |= R300_DEPTHMACROTILE_ENABLE;
 300     }
 301     if (r300->radeon.glCtx->Visual.depthBits == 24) {
 302         zbpitch |= R300_DEPTHMICROTILE_TILED;
 303     }
 304
 305         BEGIN_BATCH(4);
 306         OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 307         OUT_BATCH_RELOC(0, rrb->bo, 0, 0);
 308         OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
 309         END_BATCH();
 310 }
 311
 312 static int check_always(r300ContextPtr r300, struct r300_state_atom *atom)
 313 {
 314         return atom->cmd_size;
 315 }
 316
 317 static int check_variable(r300ContextPtr r300, struct r300_state_atom *atom)
 318 {
 319         int cnt;
 320         cnt = packet0_count(atom->cmd);
 321         return cnt ? cnt + 1 : 0;
 322 }
 323
 324 static int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom)
 325 {
 326         int cnt;
 327         cnt = vpu_count(atom->cmd);
 328         return cnt ? (cnt * 4) + 1 : 0;
 329 }
 330
 331 static int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom)
 332 {
 333         int cnt;
 334         cnt = r500fp_count(atom->cmd);
 335         return cnt ? (cnt * 6) + 1 : 0;
 336 }
 337
 338 static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom)
 339 {
 340         int cnt;
 341         cnt = r500fp_count(atom->cmd);
 342         return cnt ? (cnt * 4) + 1 : 0;
 343 }
 344
 345 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )                               \
 346    do {                                                                 \
 347       r300->hw.ATOM.cmd_size = (SZ);                                    \
 348       r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 349       r300->hw.ATOM.name = #ATOM;                                       \
 350       r300->hw.ATOM.idx = (IDX);                                        \
 351       r300->hw.ATOM.check = check_##CHK;                                \
 352       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 353       r300->hw.max_state_size += (SZ);                                  \
 354       insert_at_tail(&r300->hw.atomlist, &r300->hw.ATOM);               \
 355    } while (0)
 356 /**
 357  * Allocate memory for the command buffer and initialize the state atom
 358  * list. Note that the initial hardware state is set by r300InitState().
 359  */
 360 void r300InitCmdBuf(r300ContextPtr r300)
 361 {
 362         int size, mtu;
 363         int has_tcl = 1;
 364         int is_r500 = 0;
 365         int i;
 366
 367         if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
 368                 has_tcl = 0;
 369
 370         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 371                 is_r500 = 1;
 372
 373         r300->hw.max_state_size = 2 + 2;        /* reserve extra space for WAIT_IDLE and tex cache flush */
 374
 375         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 376         if (RADEON_DEBUG & DEBUG_TEXTURE) {
 377                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 378         }
 379
 380         /* Setup the atom linked list */
 381         make_empty_list(&r300->hw.atomlist);
 382         r300->hw.atomlist.name = "atom-list";
 383
 384         /* Initialize state atoms */
 385         ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
 386         r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(R300_SE_VPORT_XSCALE, 6);
 387         ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
 388         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(R300_VAP_PVS_STATE_FLUSH_REG, 1);
 389         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
 390         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(R300_VAP_CNTL, 1);
 391         if (is_r500) {
 392             ALLOC_STATE(vap_index_offset, always, 2, 0);
 393             r300->hw.vap_index_offset.cmd[0] = cmdpacket0(R500_VAP_INDEX_OFFSET, 1);
 394             r300->hw.vap_index_offset.cmd[1] = 0;
 395         }
 396         ALLOC_STATE(vte, always, 3, 0);
 397         r300->hw.vte.cmd[0] = cmdpacket0(R300_SE_VTE_CNTL, 2);
 398         ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
 399         r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(R300_VAP_VF_MAX_VTX_INDX, 2);
 400         ALLOC_STATE(vap_cntl_status, always, 2, 0);
 401         r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(R300_VAP_CNTL_STATUS, 1);
 402         ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
 403         r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
 404             cmdpacket0(R300_VAP_PROG_STREAM_CNTL_0, 1);
 405         ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
 406         r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
 407             cmdpacket0(R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 408         ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
 409         r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(R300_VAP_VTX_STATE_CNTL, 2);
 410         ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 411         r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 412
 413         if (has_tcl) {
 414                 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 415                 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(R300_VAP_CLIP_CNTL, 1);
 416                 ALLOC_STATE(vap_clip, always, 5, 0);
 417                 r300->hw.vap_clip.cmd[0] = cmdpacket0(R300_VAP_GB_VERT_CLIP_ADJ, 4);
 418                 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
 419                 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(VAP_PVS_VTX_TIMEOUT_REG, 1);
 420         }
 421
 422         ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
 423         r300->hw.vof.cmd[R300_VOF_CMD_0] =
 424             cmdpacket0(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 425
 426         if (has_tcl) {
 427                 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
 428                 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
 429                     cmdpacket0(R300_VAP_PVS_CODE_CNTL_0, 3);
 430         }
 431
 432         ALLOC_STATE(gb_enable, always, 2, 0);
 433         r300->hw.gb_enable.cmd[0] = cmdpacket0(R300_GB_ENABLE, 1);
 434         ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
 435         r300->hw.gb_misc.cmd[0] = cmdpacket0(R300_GB_MSPOS0, 5);
 436         ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
 437         r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(R300_TX_ENABLE, 1);
 438         ALLOC_STATE(ga_point_s0, always, 5, 0);
 439         r300->hw.ga_point_s0.cmd[0] = cmdpacket0(R300_GA_POINT_S0, 4);
 440         ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
 441         r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(R300_GA_TRIANGLE_STIPPLE, 1);
 442         ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
 443         r300->hw.ps.cmd[0] = cmdpacket0(R300_GA_POINT_SIZE, 1);
 444         ALLOC_STATE(ga_point_minmax, always, 4, 0);
 445         r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(R300_GA_POINT_MINMAX, 3);
 446         ALLOC_STATE(lcntl, always, 2, 0);
 447         r300->hw.lcntl.cmd[0] = cmdpacket0(R300_GA_LINE_CNTL, 1);
 448         ALLOC_STATE(ga_line_stipple, always, 4, 0);
 449         r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(R300_GA_LINE_STIPPLE_VALUE, 3);
 450         ALLOC_STATE(shade, always, 5, 0);
 451         r300->hw.shade.cmd[0] = cmdpacket0(R300_GA_ENHANCE, 4);
 452         ALLOC_STATE(polygon_mode, always, 4, 0);
 453         r300->hw.polygon_mode.cmd[0] = cmdpacket0(R300_GA_POLY_MODE, 3);
 454         ALLOC_STATE(fogp, always, 3, 0);
 455         r300->hw.fogp.cmd[0] = cmdpacket0(R300_GA_FOG_SCALE, 2);
 456         ALLOC_STATE(zbias_cntl, always, 2, 0);
 457         r300->hw.zbias_cntl.cmd[0] = cmdpacket0(R300_SU_TEX_WRAP, 1);
 458         ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
 459         r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
 460             cmdpacket0(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 461         ALLOC_STATE(occlusion_cntl, always, 2, 0);
 462         r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(R300_SU_POLY_OFFSET_ENABLE, 1);
 463         ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
 464         r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(R300_SU_CULL_MODE, 1);
 465         ALLOC_STATE(su_depth_scale, always, 3, 0);
 466         r300->hw.su_depth_scale.cmd[0] = cmdpacket0(R300_SU_DEPTH_SCALE, 2);
 467         ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
 468         r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(R300_RS_COUNT, 2);
 469         if (is_r500) {
 470                 ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
 471                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(R500_RS_IP_0, 16);
 472                 for (i = 0; i < 8; i++) {
 473                         r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
 474                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 475                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 476                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 477                           (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
 478                 }
 479                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 480                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R500_RS_INST_0, 1);
 481         } else {
 482                 ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
 483                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(R300_RS_IP_0, 8);
 484                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 485                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, 1);
 486         }
 487         ALLOC_STATE(sc_hyperz, always, 3, 0);
 488         r300->hw.sc_hyperz.cmd[0] = cmdpacket0(R300_SC_HYPERZ, 2);
 489         ALLOC_STATE(sc_screendoor, always, 2, 0);
 490         r300->hw.sc_screendoor.cmd[0] = cmdpacket0(R300_SC_SCREENDOOR, 1);
 491         ALLOC_STATE(us_out_fmt, always, 6, 0);
 492         r300->hw.us_out_fmt.cmd[0] = cmdpacket0(R300_US_OUT_FMT, 5);
 493
 494         if (is_r500) {
 495                 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
 496                 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(R500_US_CONFIG, 2);
 497                 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
 498                 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(R500_US_CODE_ADDR, 3);
 499                 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(R500_US_FC_CTRL, 1);
 500                 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
 501
 502                 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
 503                 r300->hw.r500fp.cmd[R300_FPI_CMD_0] = cmdr500fp(0, 0, 0, 0);
 504                 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
 505                 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] = cmdr500fp(0, 0, 1, 0);
 506         } else {
 507                 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 508                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(R300_US_CONFIG, 3);
 509                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(R300_US_CODE_ADDR_0, 4);
 510                 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
 511                 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(R300_US_TEX_INST_0, 0);
 512
 513                 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
 514                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_INST_0, 1);
 515                 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
 516                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_ADDR_0, 1);
 517                 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
 518                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_INST_0, 1);
 519                 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
 520                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_ADDR_0, 1);
 521                 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
 522                 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(R300_PFS_PARAM_0_X, 0);
 523         }
 524         ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
 525         r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(R300_FG_FOG_BLEND, 1);
 526         ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
 527         r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(R300_FG_FOG_COLOR_R, 3);
 528         ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
 529         r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(R300_FG_ALPHA_FUNC, 2);
 530         ALLOC_STATE(fg_depth_src, always, 2, 0);
 531         r300->hw.fg_depth_src.cmd[0] = cmdpacket0(R300_FG_DEPTH_SRC, 1);
 532         ALLOC_STATE(rb3d_cctl, always, 2, 0);
 533         r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(R300_RB3D_CCTL, 1);
 534         ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
 535         r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(R300_RB3D_CBLEND, 2);
 536         ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
 537         r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(RB3D_COLOR_CHANNEL_MASK, 1);
 538         if (is_r500) {
 539                 ALLOC_STATE(blend_color, always, 3, 0);
 540                 r300->hw.blend_color.cmd[0] = cmdpacket0(R500_RB3D_CONSTANT_COLOR_AR, 2);
 541         } else {
 542                 ALLOC_STATE(blend_color, always, 2, 0);
 543                 r300->hw.blend_color.cmd[0] = cmdpacket0(R300_RB3D_BLEND_COLOR, 1);
 544         }
 545         ALLOC_STATE(rop, always, 2, 0);
 546         r300->hw.rop.cmd[0] = cmdpacket0(R300_RB3D_ROPCNTL, 1);
 547         ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
 548         r300->hw.cb.emit = &emit_cb_offset;
 549         ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
 550         r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(R300_RB3D_DITHER_CTL, 9);
 551         ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 552         r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(R300_RB3D_AARESOLVE_CTL, 1);
 553         ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
 554         r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
 555         ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
 556         r300->hw.zs.cmd[R300_ZS_CMD_0] =
 557             cmdpacket0(R300_ZB_CNTL, 3);
 558         ALLOC_STATE(zstencil_format, always, 5, 0);
 559         r300->hw.zstencil_format.cmd[0] =
 560             cmdpacket0(R300_ZB_FORMAT, 4);
 561         ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
 562         r300->hw.zb.emit = emit_zb_offset;
 563         ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
 564         r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(R300_ZB_DEPTHCLEARVALUE, 1);
 565         ALLOC_STATE(unk4F30, always, 3, 0);
 566         r300->hw.unk4F30.cmd[0] = cmdpacket0(0x4F30, 2);
 567         ALLOC_STATE(zb_hiz_offset, always, 2, 0);
 568         r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(R300_ZB_HIZ_OFFSET, 1);
 569         ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
 570         r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(R300_ZB_HIZ_PITCH, 1);
 571
 572         /* VPU only on TCL */
 573         if (has_tcl) {
 574                 int i;
 575                 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 576                 r300->hw.vpi.cmd[R300_VPI_CMD_0] =
 577                     cmdvpu(R300_PVS_CODE_START, 0);
 578
 579                 if (is_r500) {
 580                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 581                     r300->hw.vpp.cmd[R300_VPP_CMD_0] =
 582                         cmdvpu(R500_PVS_CONST_START, 0);
 583
 584                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 585                     r300->hw.vps.cmd[R300_VPS_CMD_0] =
 586                         cmdvpu(R500_POINT_VPORT_SCALE_OFFSET, 1);
 587
 588                         for (i = 0; i < 6; i++) {
 589                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 590                                 r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] =
 591                                         cmdvpu(R500_PVS_UCP_START + i, 1);
 592                         }
 593                 } else {
 594                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 595                     r300->hw.vpp.cmd[R300_VPP_CMD_0] =
 596                         cmdvpu(R300_PVS_CONST_START, 0);
 597
 598                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 599                     r300->hw.vps.cmd[R300_VPS_CMD_0] =
 600                         cmdvpu(R300_POINT_VPORT_SCALE_OFFSET, 1);
 601
 602                         for (i = 0; i < 6; i++) {
 603                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 604                                 r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] =
 605                                         cmdvpu(R300_PVS_UCP_START + i, 1);
 606                         }
 607                 }
 608         }
 609
 610         /* Textures */
 611         ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
 612         r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
 613             cmdpacket0(R300_TX_FILTER0_0, 0);
 614
 615         ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
 616         r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
 617             cmdpacket0(R300_TX_FILTER1_0, 0);
 618
 619         ALLOC_STATE(tex.size, variable, mtu + 1, 0);
 620         r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_SIZE_0, 0);
 621
 622         ALLOC_STATE(tex.format, variable, mtu + 1, 0);
 623         r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
 624             cmdpacket0(R300_TX_FORMAT_0, 0);
 625
 626         ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
 627         r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FORMAT2_0, 0);
 628
 629         ALLOC_STATE(tex.offset, variable, 1, 0);
 630         r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
 631             cmdpacket0(R300_TX_OFFSET_0, 0);
 632         r300->hw.tex.offset.emit = &emit_tex_offsets;
 633
 634         ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
 635         r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
 636             cmdpacket0(R300_TX_CHROMA_KEY_0, 0);
 637
 638         ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
 639         r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
 640             cmdpacket0(R300_TX_BORDER_COLOR_0, 0);
 641
 642         r300->hw.is_dirty = GL_TRUE;
 643         r300->hw.all_dirty = GL_TRUE;
 644
 645         /* Initialize command buffer */
 646         size =
 647             256 * driQueryOptioni(&r300->radeon.optionCache,
 648                                   "command_buffer_size");
 649         if (size < 2 * r300->hw.max_state_size) {
 650                 size = 2 * r300->hw.max_state_size + 65535;
 651         }
 652         if (size > 64 * 256)
 653                 size = 64 * 256;
 654
 655     size = 64 * 1024 / 4;
 656         if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) {
 657                 fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n",
 658                         sizeof(drm_r300_cmd_header_t));
 659                 fprintf(stderr, "sizeof(drm_radeon_cmd_buffer_t)=%zd\n",
 660                         sizeof(drm_radeon_cmd_buffer_t));
 661                 fprintf(stderr,
 662                         "Allocating %d bytes command buffer (max state is %d bytes)\n",
 663                         size * 4, r300->hw.max_state_size * 4);
 664         }
 665
 666     r300->cmdbuf.csm = radeon_cs_manager_legacy(&r300->radeon);
 667     if (r300->cmdbuf.csm == NULL) {
 668         /* FIXME: fatal error */
 669         return;
 670     }
 671     r300->cmdbuf.cs = radeon_cs_create(r300->cmdbuf.csm, size);
 672     assert(r300->cmdbuf.cs != NULL);
 673         r300->cmdbuf.size = size;
 674 }
 675
 676 /**
 677  * Destroy the command buffer and state atoms.
 678  */
 679 void r300DestroyCmdBuf(r300ContextPtr r300)
 680 {
 681         struct r300_state_atom *atom;
 682
 683     radeon_cs_destroy(r300->cmdbuf.cs);
 684         foreach(atom, &r300->hw.atomlist) {
 685                 FREE(atom->cmd);
 686         }
 687 }