src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #include "main/glheader.h"
  37 #include "main/state.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42
  43 #include "drm.h"
  44 #include "radeon_drm.h"
  45
  46 #include "r300_context.h"
  47 #include "r300_reg.h"
  48 #include "r300_cmdbuf.h"
  49 #include "r300_emit.h"
  50 #include "radeon_bocs_wrapper.h"
  51 #include "radeon_mipmap_tree.h"
  52 #include "radeon_queryobj.h"
  53
  54 /** # of dwords reserved for additional instructions that may need to be written
  55  * during flushing.
  56  */
  57 #define SPACE_FOR_FLUSHING      4
  58
  59 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
  60 {
  61     if (r300->radeon.radeonScreen->kernel_mm) {
  62         return ((((*pkt) >> 16) & 0x3FFF) + 1);
  63     } else {
  64         drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
  65         return t->packet0.count;
  66     }
  67 }
  68
  69 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
  70 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
  71
  72 static int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
  73 {
  74         r300ContextPtr r300 = R300_CONTEXT(ctx);
  75         int cnt;
  76         int extra = 1;
  77         cnt = vpu_count(atom->cmd);
  78
  79         if (r300->radeon.radeonScreen->kernel_mm) {
  80                 extra = 5;
  81         }
  82
  83         return cnt ? (cnt * 4) + extra : 0;
  84 }
  85
  86 void r300_emit_vpu(struct r300_context *r300,
  87                    uint32_t *data,
  88                    unsigned len,
  89                    uint32_t addr)
  90 {
  91     BATCH_LOCALS(&r300->radeon);
  92
  93     BEGIN_BATCH_NO_AUTOSTATE(3 + len);
  94     OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
  95     OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, len-1) | RADEON_ONE_REG_WR);
  96     OUT_BATCH_TABLE(data, len);
  97     END_BATCH();
  98 }
  99
 100 static void emit_vpu_state(GLcontext *ctx, struct radeon_state_atom * atom)
 101 {
 102     r300ContextPtr r300 = R300_CONTEXT(ctx);
 103     drm_r300_cmd_header_t cmd;
 104     uint32_t addr, ndw;
 105
 106     cmd.u = atom->cmd[0];
 107     addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
 108     ndw = atom->check(ctx, atom);
 109
 110     r300_emit_vpu(r300, &atom->cmd[1], vpu_count(atom->cmd) * 4, addr);
 111 }
 112
 113 void r500_emit_fp(struct r300_context *r300,
 114                   uint32_t *data,
 115                   unsigned len,
 116                   uint32_t addr,
 117                   unsigned type,
 118                   unsigned clamp)
 119 {
 120     BATCH_LOCALS(&r300->radeon);
 121
 122     addr |= (type << 16);
 123     addr |= (clamp << 17);
 124
 125     BEGIN_BATCH_NO_AUTOSTATE(len + 3);
 126     OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
 127     OUT_BATCH(addr);
 128     OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, len-1) | RADEON_ONE_REG_WR);
 129     OUT_BATCH_TABLE(data, len);
 130     END_BATCH();
 131 }
 132
 133 static void emit_r500fp_atom(GLcontext *ctx, struct radeon_state_atom * atom)
 134 {
 135     r300ContextPtr r300 = R300_CONTEXT(ctx);
 136     drm_r300_cmd_header_t cmd;
 137     uint32_t addr, count;
 138     int type, clamp;
 139
 140     cmd.u = atom->cmd[0];
 141     addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
 142     type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
 143     clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
 144
 145     if (type) {
 146         count = r500fp_count(atom->cmd) * 4;
 147     } else {
 148         count = r500fp_count(atom->cmd) * 6;
 149     }
 150
 151     r500_emit_fp(r300, &atom->cmd[1], count, addr, type, clamp);
 152 }
 153
 154 static int check_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 155 {
 156         r300ContextPtr r300 = R300_CONTEXT(ctx);
 157         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 158         int dw = 0, i;
 159         if (atom->cmd[0] == CP_PACKET2) {
 160                 return dw;
 161         }
 162         for(i = 0; i < numtmus; ++i) {
 163                 radeonTexObj *t = r300->hw.textures[i];
 164                 if (!t && !r300->radeon.radeonScreen->kernel_mm) {
 165                         dw += 0;
 166                 } else if (t && t->image_override && !t->bo) {
 167                         if (!r300->radeon.radeonScreen->kernel_mm)
 168                                 dw += 2;
 169                 } else
 170                         dw += 4;
 171         }
 172         return dw;
 173 }
 174
 175 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 176 {
 177         r300ContextPtr r300 = R300_CONTEXT(ctx);
 178         BATCH_LOCALS(&r300->radeon);
 179         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 180         int i;
 181
 182         for(i = 0; i < numtmus; ++i) {
 183                 radeonTexObj *t = r300->hw.textures[i];
 184                 if (t && !t->image_override) {
 185                         BEGIN_BATCH_NO_AUTOSTATE(4);
 186                         OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 187                         OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
 188                                         RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 189                         END_BATCH();
 190                 } else if (!t) {
 191                         /* Texture unit hasn't a texture bound.
 192                          * We assign the current color buffer as a fakery to make
 193                          * KIL work on KMS (without it, the CS checker will complain).
 194                          */
 195                         if (r300->radeon.radeonScreen->kernel_mm) {
 196                                 struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
 197                                 if (rrb && rrb->bo) {
 198                                         BEGIN_BATCH_NO_AUTOSTATE(4);
 199                                         OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 200                                         OUT_BATCH_RELOC(0, rrb->bo, 0,
 201                                                         RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 202                                         END_BATCH();
 203                                 }
 204                         }
 205                 } else { /* override cases */
 206                         if (t->bo) {
 207                                 BEGIN_BATCH_NO_AUTOSTATE(4);
 208                                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 209                                 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
 210                                                 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 211                                 END_BATCH();
 212                         } else if (!r300->radeon.radeonScreen->kernel_mm) {
 213                                 BEGIN_BATCH_NO_AUTOSTATE(2);
 214                                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 215                                 OUT_BATCH(t->override_offset);
 216                                 END_BATCH();
 217                         } else {
 218                                 /* Texture unit hasn't a texture bound nothings to do */
 219                         }
 220                 }
 221         }
 222 }
 223
 224 void r300_emit_scissor(GLcontext *ctx)
 225 {
 226         r300ContextPtr r300 = R300_CONTEXT(ctx);
 227         BATCH_LOCALS(&r300->radeon);
 228     unsigned x1, y1, x2, y2;
 229         struct radeon_renderbuffer *rrb;
 230
 231     if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 232         return;
 233     }
 234         rrb = radeon_get_colorbuffer(&r300->radeon);
 235         if (!rrb || !rrb->bo) {
 236                 fprintf(stderr, "no rrb\n");
 237                 return;
 238         }
 239     if (r300->radeon.state.scissor.enabled) {
 240         x1 = r300->radeon.state.scissor.rect.x1;
 241         y1 = r300->radeon.state.scissor.rect.y1;
 242         x2 = r300->radeon.state.scissor.rect.x2;
 243         y2 = r300->radeon.state.scissor.rect.y2;
 244     } else {
 245         x1 = 0;
 246         y1 = 0;
 247         x2 = rrb->base.Width - 1;
 248         y2 = rrb->base.Height - 1;
 249     }
 250     if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
 251         x1 += R300_SCISSORS_OFFSET;
 252         y1 += R300_SCISSORS_OFFSET;
 253         x2 += R300_SCISSORS_OFFSET;
 254         y2 += R300_SCISSORS_OFFSET;
 255     }
 256     BEGIN_BATCH_NO_AUTOSTATE(3);
 257     OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 258     OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
 259     OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
 260     END_BATCH();
 261 }
 262 static int check_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 263 {
 264         r300ContextPtr r300 = R300_CONTEXT(ctx);
 265         uint32_t dw = 6 + 3 + 16;
 266         if (r300->radeon.radeonScreen->kernel_mm)
 267                 dw += 2;
 268         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 269                 dw -= 3 + 16;
 270         }
 271         return dw;
 272 }
 273
 274 static void emit_scissor(struct r300_context *r300,
 275                          unsigned width,
 276                          unsigned height)
 277 {
 278     int i;
 279     BATCH_LOCALS(&r300->radeon);
 280     if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 281         BEGIN_BATCH_NO_AUTOSTATE(3);
 282         OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 283         OUT_BATCH(0);
 284         OUT_BATCH(((width - 1) << R300_SCISSORS_X_SHIFT) |
 285                 ((height - 1) << R300_SCISSORS_Y_SHIFT));
 286         END_BATCH();
 287         BEGIN_BATCH_NO_AUTOSTATE(16);
 288         for (i = 0; i < 4; i++) {
 289             OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 290             OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
 291             OUT_BATCH(((width - 1) << R300_CLIPRECT_X_SHIFT) | ((height - 1) << R300_CLIPRECT_Y_SHIFT));
 292         }
 293         OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 294         OUT_BATCH(0xAAAA);
 295         OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 296         OUT_BATCH(0xffffff);
 297         END_BATCH();
 298     } else {
 299         BEGIN_BATCH_NO_AUTOSTATE(3);
 300         OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 301         OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
 302                 (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
 303         OUT_BATCH(((width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
 304                 ((height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
 305         END_BATCH();
 306         BEGIN_BATCH_NO_AUTOSTATE(16);
 307         for (i = 0; i < 4; i++) {
 308             OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 309             OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
 310             OUT_BATCH(((R300_SCISSORS_OFFSET + width - 1) << R300_CLIPRECT_X_SHIFT) |
 311                         ((R300_SCISSORS_OFFSET + height - 1) << R300_CLIPRECT_Y_SHIFT));
 312         }
 313         OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 314         OUT_BATCH(0xAAAA);
 315         OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 316         OUT_BATCH(0xffffff);
 317         END_BATCH();
 318     }
 319 }
 320
 321 void r300_emit_cb_setup(struct r300_context *r300,
 322                         struct radeon_bo *bo,
 323                         uint32_t offset,
 324                         GLuint format,
 325                         unsigned cpp,
 326                         unsigned pitch)
 327 {
 328     BATCH_LOCALS(&r300->radeon);
 329     uint32_t cbpitch = pitch / cpp;
 330     uint32_t dw = 6;
 331
 332     assert(offset % 32 == 0);
 333
 334     switch (format) {
 335         case MESA_FORMAT_SL8:
 336         case MESA_FORMAT_A8:
 337         case MESA_FORMAT_L8:
 338         case MESA_FORMAT_I8:
 339             cbpitch |= R300_COLOR_FORMAT_I8;
 340             break;
 341         case MESA_FORMAT_RGB565:
 342         case MESA_FORMAT_RGB565_REV:
 343             cbpitch |= R300_COLOR_FORMAT_RGB565;
 344             break;
 345         case MESA_FORMAT_ARGB4444:
 346         case MESA_FORMAT_ARGB4444_REV:
 347             cbpitch |= R300_COLOR_FORMAT_ARGB4444;
 348             break;
 349         case MESA_FORMAT_RGBA5551:
 350         case MESA_FORMAT_ARGB1555:
 351         case MESA_FORMAT_ARGB1555_REV:
 352             cbpitch |= R300_COLOR_FORMAT_ARGB1555;
 353             break;
 354         case MESA_FORMAT_RGBA8888:
 355         case MESA_FORMAT_RGBA8888_REV:
 356         case MESA_FORMAT_XRGB8888:
 357         case MESA_FORMAT_ARGB8888:
 358         case MESA_FORMAT_XRGB8888_REV:
 359         case MESA_FORMAT_ARGB8888_REV:
 360         case MESA_FORMAT_SRGBA8:
 361         case MESA_FORMAT_SARGB8:
 362             cbpitch |= R300_COLOR_FORMAT_ARGB8888;
 363             break;
 364         default:
 365             _mesa_problem(r300->radeon.glCtx, "unexpected format in emit_cb_offset()");
 366             break;
 367     }
 368
 369     if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 370         cbpitch |= R300_COLOR_TILE_ENABLE;
 371
 372     if (r300->radeon.radeonScreen->kernel_mm)
 373         dw += 2;
 374
 375     BEGIN_BATCH_NO_AUTOSTATE(dw);
 376     OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
 377     OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 378     OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
 379     if (!r300->radeon.radeonScreen->kernel_mm)
 380         OUT_BATCH(cbpitch);
 381     else
 382         OUT_BATCH_RELOC(cbpitch, bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 383     END_BATCH();
 384 }
 385
 386 static void emit_cb_offset_atom(GLcontext *ctx, struct radeon_state_atom * atom)
 387 {
 388     r300ContextPtr r300 = R300_CONTEXT(ctx);
 389     struct radeon_renderbuffer *rrb;
 390     uint32_t offset = r300->radeon.state.color.draw_offset;
 391
 392     rrb = radeon_get_colorbuffer(&r300->radeon);
 393     if (!rrb || !rrb->bo) {
 394         fprintf(stderr, "no rrb\n");
 395         return;
 396     }
 397
 398     if (RADEON_DEBUG & RADEON_STATE)
 399         fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
 400
 401     r300_emit_cb_setup(r300, rrb->bo, offset, rrb->base.Format, rrb->cpp, rrb->pitch);
 402
 403     if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 404         emit_scissor(r300, rrb->base.Width, rrb->base.Height);
 405     }
 406 }
 407
 408 static int check_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 409 {
 410         r300ContextPtr r300 = R300_CONTEXT(ctx);
 411         uint32_t dw;
 412         dw = 6;
 413         if (r300->radeon.radeonScreen->kernel_mm)
 414                 dw += 2;
 415         return dw;
 416 }
 417
 418 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 419 {
 420         r300ContextPtr r300 = R300_CONTEXT(ctx);
 421         BATCH_LOCALS(&r300->radeon);
 422         struct radeon_renderbuffer *rrb;
 423         uint32_t zbpitch;
 424         uint32_t dw = atom->check(ctx, atom);
 425
 426         rrb = radeon_get_depthbuffer(&r300->radeon);
 427         if (!rrb)
 428                 return;
 429
 430         zbpitch = (rrb->pitch / rrb->cpp);
 431         if (!r300->radeon.radeonScreen->kernel_mm) {
 432             if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
 433                 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
 434            }
 435             if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 436                 zbpitch |= R300_DEPTHMICROTILE_TILED;
 437             }
 438         }
 439
 440         BEGIN_BATCH_NO_AUTOSTATE(dw);
 441         OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 442         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 443         OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
 444         if (!r300->radeon.radeonScreen->kernel_mm)
 445             OUT_BATCH(zbpitch);
 446         else
 447             OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 448         END_BATCH();
 449 }
 450
 451 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
 452 {
 453         r300ContextPtr r300 = R300_CONTEXT(ctx);
 454         BATCH_LOCALS(&r300->radeon);
 455         struct radeon_renderbuffer *rrb;
 456         uint32_t format = 0;
 457
 458         rrb = radeon_get_depthbuffer(&r300->radeon);
 459         if (!rrb)
 460           format = 0;
 461         else {
 462           if (rrb->cpp == 2)
 463             format = R300_DEPTHFORMAT_16BIT_INT_Z;
 464           else if (rrb->cpp == 4)
 465             format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
 466         }
 467
 468         BEGIN_BATCH_NO_AUTOSTATE(atom->cmd_size);
 469         OUT_BATCH(atom->cmd[0]);
 470         atom->cmd[1] &= ~0xf;
 471         atom->cmd[1] |= format;
 472         OUT_BATCH(atom->cmd[1]);
 473         OUT_BATCH(atom->cmd[2]);
 474         OUT_BATCH(atom->cmd[3]);
 475         OUT_BATCH(atom->cmd[4]);
 476         END_BATCH();
 477 }
 478
 479 static int check_never(GLcontext *ctx, struct radeon_state_atom *atom)
 480 {
 481    return 0;
 482 }
 483
 484 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 485 {
 486         return atom->cmd_size;
 487 }
 488
 489 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
 490 {
 491         r300ContextPtr r300 = R300_CONTEXT(ctx);
 492         int cnt;
 493         if (atom->cmd[0] == CP_PACKET2) {
 494                 return 0;
 495         }
 496         cnt = packet0_count(r300, atom->cmd);
 497         return cnt ? cnt + 1 : 0;
 498 }
 499
 500 static int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
 501 {
 502         int cnt;
 503         r300ContextPtr r300 = R300_CONTEXT(ctx);
 504         int extra = 1;
 505         cnt = r500fp_count(atom->cmd);
 506         if (r300->radeon.radeonScreen->kernel_mm)
 507                 extra = 3;
 508
 509         return cnt ? (cnt * 6) + extra : 0;
 510 }
 511
 512 static int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
 513 {
 514         int cnt;
 515         r300ContextPtr r300 = R300_CONTEXT(ctx);
 516         int extra = 1;
 517         cnt = r500fp_count(atom->cmd);
 518         if (r300->radeon.radeonScreen->kernel_mm)
 519                 extra = 3;
 520
 521         cnt = r500fp_count(atom->cmd);
 522         return cnt ? (cnt * 4) + extra : 0;
 523 }
 524
 525 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )                               \
 526    do {                                                                 \
 527       r300->hw.ATOM.cmd_size = (SZ);                                    \
 528       r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 529       r300->hw.ATOM.name = #ATOM;                                       \
 530       r300->hw.ATOM.idx = (IDX);                                        \
 531       r300->hw.ATOM.check = check_##CHK;                                \
 532       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 533       r300->radeon.hw.max_state_size += (SZ);                                   \
 534       insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM);                \
 535    } while (0)
 536 /**
 537  * Allocate memory for the command buffer and initialize the state atom
 538  * list. Note that the initial hardware state is set by r300InitState().
 539  */
 540 void r300InitCmdBuf(r300ContextPtr r300)
 541 {
 542         int mtu;
 543         int has_tcl;
 544         int is_r500 = 0;
 545
 546         has_tcl = r300->options.hw_tcl_enabled;
 547
 548         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 549                 is_r500 = 1;
 550
 551         r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
 552
 553         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 554         if (RADEON_DEBUG & RADEON_TEXTURE) {
 555                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 556         }
 557
 558         /* Setup the atom linked list */
 559         make_empty_list(&r300->radeon.hw.atomlist);
 560         r300->radeon.hw.atomlist.name = "atom-list";
 561
 562         /* Initialize state atoms */
 563         ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
 564         r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
 565         ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
 566         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 567         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
 568         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
 569         if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
 570             ALLOC_STATE(vap_index_offset, always, 2, 0);
 571             r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
 572             r300->hw.vap_index_offset.cmd[1] = 0;
 573         }
 574         ALLOC_STATE(vte, always, 3, 0);
 575         r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
 576         ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
 577         r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
 578         ALLOC_STATE(vap_cntl_status, always, 2, 0);
 579         r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
 580         ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
 581         r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
 582             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
 583         ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
 584         r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
 585             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 586         ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
 587         r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
 588         ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 589         r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 590
 591         if (has_tcl) {
 592                 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 593                 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
 594                 ALLOC_STATE(vap_clip, always, 5, 0);
 595                 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
 596                 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
 597                 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
 598         }
 599
 600         ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
 601         r300->hw.vof.cmd[R300_VOF_CMD_0] =
 602             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
 603
 604         if (has_tcl) {
 605                 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
 606                 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
 607                     cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
 608         }
 609
 610         ALLOC_STATE(gb_enable, always, 2, 0);
 611         r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
 612         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 613                 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
 614         } else {
 615                 ALLOC_STATE(gb_misc, never, R300_GB_MISC_CMDSIZE, 0);
 616         }
 617         r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
 618         ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
 619         r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
 620         ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
 621         r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
 622         ALLOC_STATE(ga_point_s0, always, 5, 0);
 623         r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
 624         ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
 625         r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
 626         ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
 627         r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
 628         ALLOC_STATE(ga_point_minmax, always, 4, 0);
 629         r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
 630         ALLOC_STATE(lcntl, always, 2, 0);
 631         r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
 632         ALLOC_STATE(ga_line_stipple, always, 4, 0);
 633         r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
 634         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 635                 ALLOC_STATE(shade, always, 2, 0);
 636         } else {
 637                 ALLOC_STATE(shade, never, 2, 0);
 638         }
 639         r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
 640         ALLOC_STATE(shade2, always, 4, 0);
 641         r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
 642         ALLOC_STATE(polygon_mode, always, 4, 0);
 643         r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
 644         ALLOC_STATE(fogp, always, 3, 0);
 645         r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
 646         ALLOC_STATE(zbias_cntl, always, 2, 0);
 647         r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
 648         ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
 649         r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
 650             cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 651         ALLOC_STATE(occlusion_cntl, always, 2, 0);
 652         r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
 653         ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
 654         r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
 655         ALLOC_STATE(su_depth_scale, always, 3, 0);
 656         r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
 657         ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
 658         r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
 659         if (is_r500) {
 660                 ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0);
 661                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
 662                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 663                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
 664         } else {
 665                 ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0);
 666                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
 667                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 668                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
 669         }
 670         ALLOC_STATE(sc_hyperz, always, 3, 0);
 671         r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
 672         ALLOC_STATE(sc_screendoor, always, 2, 0);
 673         r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 674         ALLOC_STATE(us_out_fmt, always, 6, 0);
 675         r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
 676
 677         if (is_r500) {
 678                 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
 679                 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
 680                 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
 681                 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
 682                 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
 683                 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
 684
 685                 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
 686                 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
 687                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
 688                 if (r300->radeon.radeonScreen->kernel_mm)
 689                         r300->hw.r500fp.emit = emit_r500fp_atom;
 690
 691                 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
 692                 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
 693                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
 694                 if (r300->radeon.radeonScreen->kernel_mm)
 695                         r300->hw.r500fp_const.emit = emit_r500fp_atom;
 696         } else {
 697                 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 698                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
 699                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
 700
 701                 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
 702                 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
 703
 704                 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
 705                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
 706                 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
 707                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
 708                 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
 709                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
 710                 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
 711                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
 712                 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
 713                 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
 714         }
 715         ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
 716         r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
 717         ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
 718         r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
 719         ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
 720         r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
 721         ALLOC_STATE(fg_depth_src, always, 2, 0);
 722         r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
 723         ALLOC_STATE(rb3d_cctl, always, 2, 0);
 724         r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
 725         ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
 726         r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
 727         ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
 728         r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
 729         if (is_r500) {
 730                 ALLOC_STATE(blend_color, always, 3, 0);
 731                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
 732         } else {
 733                 ALLOC_STATE(blend_color, always, 2, 0);
 734                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
 735         }
 736         ALLOC_STATE(rop, always, 2, 0);
 737         r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
 738         ALLOC_STATE(cb, cb_offset, R300_CB_CMDSIZE, 0);
 739         r300->hw.cb.emit = &emit_cb_offset_atom;
 740         ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
 741         r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
 742         ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 743         r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
 744         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350) {
 745                 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
 746         } else {
 747                 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);
 748         }
 749         r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
 750         ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
 751         r300->hw.zs.cmd[R300_ZS_CMD_0] =
 752             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
 753         if (is_r500) {
 754                 if (r300->radeon.radeonScreen->kernel_mm)
 755                         ALLOC_STATE(zsb, always, R300_ZSB_CMDSIZE, 0);
 756                 else
 757                         ALLOC_STATE(zsb, never, R300_ZSB_CMDSIZE, 0);
 758                 r300->hw.zsb.cmd[R300_ZSB_CMD_0] =
 759                         cmdpacket0(r300->radeon.radeonScreen, R500_ZB_STENCILREFMASK_BF, 1);
 760         }
 761
 762         ALLOC_STATE(zstencil_format, always, 5, 0);
 763         r300->hw.zstencil_format.cmd[0] =
 764             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
 765         r300->hw.zstencil_format.emit = emit_zstencil_format;
 766
 767         ALLOC_STATE(zb, zb_offset, R300_ZB_CMDSIZE, 0);
 768         r300->hw.zb.emit = emit_zb_offset;
 769         ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
 770         r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
 771         ALLOC_STATE(zb_zmask, always, 3, 0);
 772         r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
 773         ALLOC_STATE(zb_hiz_offset, always, 2, 0);
 774         r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
 775         ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
 776         r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
 777
 778         /* VPU only on TCL */
 779         if (has_tcl) {
 780                 int i;
 781                 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 782                 r300->hw.vpi.cmd[0] =
 783                         cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
 784                 if (r300->radeon.radeonScreen->kernel_mm)
 785                         r300->hw.vpi.emit = emit_vpu_state;
 786
 787                 if (is_r500) {
 788                         ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 789                         r300->hw.vpp.cmd[0] =
 790                                 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
 791                         if (r300->radeon.radeonScreen->kernel_mm)
 792                                 r300->hw.vpp.emit = emit_vpu_state;
 793
 794                         ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 795                         r300->hw.vps.cmd[0] =
 796                                 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
 797                         if (r300->radeon.radeonScreen->kernel_mm)
 798                                 r300->hw.vps.emit = emit_vpu_state;
 799
 800                         for (i = 0; i < 6; i++) {
 801                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 802                                 r300->hw.vpucp[i].cmd[0] =
 803                                         cmdvpu(r300->radeon.radeonScreen,
 804                                                         R500_PVS_UCP_START + i, 1);
 805                                 if (r300->radeon.radeonScreen->kernel_mm)
 806                                         r300->hw.vpucp[i].emit = emit_vpu_state;
 807                         }
 808                 } else {
 809                         ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 810                         r300->hw.vpp.cmd[0] =
 811                                 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
 812                         if (r300->radeon.radeonScreen->kernel_mm)
 813                                 r300->hw.vpp.emit = emit_vpu_state;
 814
 815                         ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 816                         r300->hw.vps.cmd[0] =
 817                                 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
 818                         if (r300->radeon.radeonScreen->kernel_mm)
 819                                 r300->hw.vps.emit = emit_vpu_state;
 820
 821                         for (i = 0; i < 6; i++) {
 822                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 823                                 r300->hw.vpucp[i].cmd[0] =
 824                                         cmdvpu(r300->radeon.radeonScreen,
 825                                                         R300_PVS_UCP_START + i, 1);
 826                                 if (r300->radeon.radeonScreen->kernel_mm)
 827                                         r300->hw.vpucp[i].emit = emit_vpu_state;
 828                         }
 829                 }
 830         }
 831
 832         /* Textures */
 833         ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
 834         r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
 835             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
 836
 837         ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
 838         r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
 839             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
 840
 841         ALLOC_STATE(tex.size, variable, mtu + 1, 0);
 842         r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
 843
 844         ALLOC_STATE(tex.format, variable, mtu + 1, 0);
 845         r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
 846             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
 847
 848         ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
 849         r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
 850
 851         ALLOC_STATE(tex.offset, tex_offsets, 1, 0);
 852         r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
 853             cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
 854         r300->hw.tex.offset.emit = &emit_tex_offsets;
 855
 856         ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
 857         r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
 858             cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
 859
 860         ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
 861         r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
 862             cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
 863
 864         radeon_init_query_stateobj(&r300->radeon, R300_QUERYOBJ_CMDSIZE);
 865         if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 866                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RV530_FG_ZBREG_DEST, 1);
 867                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL;
 868         } else {
 869                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_REG_DEST, 1);
 870                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = R300_RASTER_PIPE_SELECT_ALL;
 871         }
 872         r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZPASS_DATA, 1);
 873         r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_1] = 0;
 874
 875         r300->radeon.hw.is_dirty = GL_TRUE;
 876         r300->radeon.hw.all_dirty = GL_TRUE;
 877
 878         rcommonInitCmdBuf(&r300->radeon);
 879 }