src/mesa/drivers/dri/r300/r300_context.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  *
  35  * \author Nicolai Haehnle <prefect_@gmx.net>
  36  */
  37
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "main/imports.h"
  43 #include "main/extensions.h"
  44 #include "main/bufferobj.h"
  45 #include "main/texobj.h"
  46
  47 #include "swrast/swrast.h"
  48 #include "swrast_setup/swrast_setup.h"
  49 #include "vbo/vbo.h"
  50
  51 #include "tnl/tnl.h"
  52 #include "tnl/t_pipeline.h"
  53
  54 #include "drivers/common/driverfuncs.h"
  55 #include "drivers/common/meta.h"
  56
  57 #include "r300_context.h"
  58 #include "radeon_span.h"
  59 #include "r300_blit.h"
  60 #include "r300_cmdbuf.h"
  61 #include "r300_state.h"
  62 #include "r300_tex.h"
  63 #include "r300_emit.h"
  64 #include "r300_render.h"
  65 #include "r300_swtcl.h"
  66 #include "radeon_bocs_wrapper.h"
  67 #include "radeon_buffer_objects.h"
  68 #include "radeon_queryobj.h"
  69
  70 #include "utils.h"
  71 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  72
  73 #define need_GL_VERSION_2_0
  74 #define need_GL_ARB_occlusion_query
  75 #define need_GL_ARB_point_parameters
  76 #define need_GL_ARB_vertex_program
  77 #define need_GL_EXT_blend_equation_separate
  78 #define need_GL_EXT_blend_func_separate
  79 #define need_GL_EXT_blend_minmax
  80 #define need_GL_EXT_framebuffer_blit
  81 #define need_GL_EXT_framebuffer_object
  82 #define need_GL_EXT_fog_coord
  83 #define need_GL_EXT_gpu_program_parameters
  84 #define need_GL_EXT_provoking_vertex
  85 #define need_GL_EXT_secondary_color
  86 #define need_GL_EXT_stencil_two_side
  87 #define need_GL_ATI_separate_stencil
  88 #define need_GL_NV_vertex_program
  89
  90 #include "main/remap_helper.h"
  91
  92 static const struct dri_extension card_extensions[] = {
  93   /* *INDENT-OFF* */
  94   {"GL_ARB_depth_texture",              NULL},
  95   {"GL_ARB_fragment_program",           NULL},
  96   {"GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  97   {"GL_ARB_multitexture",               NULL},
  98   {"GL_ARB_point_parameters",           GL_ARB_point_parameters_functions},
  99   {"GL_ARB_shadow",                     NULL},
 100   {"GL_ARB_shadow_ambient",             NULL},
 101   {"GL_ARB_texture_border_clamp",       NULL},
 102   {"GL_ARB_texture_cube_map",           NULL},
 103   {"GL_ARB_texture_env_add",            NULL},
 104   {"GL_ARB_texture_env_combine",        NULL},
 105   {"GL_ARB_texture_env_crossbar",       NULL},
 106   {"GL_ARB_texture_env_dot3",           NULL},
 107   {"GL_ARB_texture_mirrored_repeat",    NULL},
 108   {"GL_ARB_vertex_program",             GL_ARB_vertex_program_functions},
 109   {"GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions},
 110   {"GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions},
 111   {"GL_EXT_blend_minmax",               GL_EXT_blend_minmax_functions},
 112   {"GL_EXT_blend_subtract",             NULL},
 113   {"GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
 114   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
 115   {"GL_EXT_provoking_vertex",           GL_EXT_provoking_vertex_functions },
 116   {"GL_EXT_secondary_color",            GL_EXT_secondary_color_functions},
 117   {"GL_EXT_shadow_funcs",               NULL},
 118   {"GL_EXT_stencil_two_side",           GL_EXT_stencil_two_side_functions},
 119   {"GL_EXT_stencil_wrap",               NULL},
 120   {"GL_EXT_texture_edge_clamp",         NULL},
 121   {"GL_EXT_texture_env_combine",        NULL},
 122   {"GL_EXT_texture_env_dot3",           NULL},
 123   {"GL_EXT_texture_filter_anisotropic", NULL},
 124   {"GL_EXT_texture_lod_bias",           NULL},
 125   {"GL_EXT_texture_mirror_clamp",       NULL},
 126   {"GL_EXT_texture_rectangle",          NULL},
 127   {"GL_EXT_texture_sRGB",               NULL},
 128   {"GL_EXT_vertex_array_bgra",          NULL},
 129   {"GL_ATI_separate_stencil",           GL_ATI_separate_stencil_functions},
 130   {"GL_ATI_texture_env_combine3",       NULL},
 131   {"GL_ATI_texture_mirror_once",        NULL},
 132   {"GL_MESA_pack_invert",               NULL},
 133   {"GL_MESA_ycbcr_texture",             NULL},
 134   {"GL_MESAX_texture_float",            NULL},
 135   {"GL_NV_blend_square",                NULL},
 136   {"GL_NV_vertex_program",              GL_NV_vertex_program_functions},
 137   {"GL_SGIS_generate_mipmap",           NULL},
 138   {NULL,                                NULL}
 139   /* *INDENT-ON* */
 140 };
 141
 142
 143 static const struct dri_extension mm_extensions[] = {
 144   { "GL_EXT_framebuffer_blit",  GL_EXT_framebuffer_blit_functions },
 145   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 146   { NULL, NULL }
 147 };
 148
 149 /**
 150  * The GL 2.0 functions are needed to make display lists work with
 151  * functions added by GL_ATI_separate_stencil.
 152  */
 153 static const struct dri_extension gl_20_extension[] = {
 154   {"GL_VERSION_2_0",                    GL_VERSION_2_0_functions },
 155 };
 156
 157 static const struct tnl_pipeline_stage *r300_pipeline[] = {
 158         /* Catch any t&l fallbacks
 159          */
 160         &_tnl_vertex_transform_stage,
 161         &_tnl_normal_transform_stage,
 162         &_tnl_lighting_stage,
 163         &_tnl_fog_coordinate_stage,
 164         &_tnl_texgen_stage,
 165         &_tnl_texture_transform_stage,
 166         &_tnl_point_attenuation_stage,
 167         &_tnl_vertex_program_stage,
 168         &_tnl_render_stage,
 169         0,
 170 };
 171
 172 static void r300_get_lock(radeonContextPtr rmesa)
 173 {
 174         drm_radeon_sarea_t *sarea = rmesa->sarea;
 175
 176         if (sarea->ctx_owner != rmesa->dri.hwContext) {
 177                 sarea->ctx_owner = rmesa->dri.hwContext;
 178                 if (!rmesa->radeonScreen->kernel_mm)
 179                         radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
 180         }
 181 }
 182
 183 static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 184 {
 185     /* please flush pipe do all pending work */
 186     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 187                                   R300_SC_SCREENDOOR, 1));
 188     radeon_cs_write_dword(cs, 0x0);
 189     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 190                                   R300_SC_SCREENDOOR, 1));
 191     radeon_cs_write_dword(cs, 0x00FFFFFF);
 192     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 193                                   R300_SC_HYPERZ, 1));
 194     radeon_cs_write_dword(cs, 0x0);
 195     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 196                                   R300_US_CONFIG, 1));
 197     radeon_cs_write_dword(cs, 0x0);
 198     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 199                                   R300_ZB_CNTL, 1));
 200     radeon_cs_write_dword(cs, 0x0);
 201     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
 202     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 203                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 204     radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 205     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 206                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 207     radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 208     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
 209                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 210 }
 211
 212 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 213 {
 214         BATCH_LOCALS(radeon);
 215
 216         cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 217         BEGIN_BATCH_NO_AUTOSTATE(2);
 218         OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
 219         END_BATCH();
 220         end_3d(radeon);
 221 }
 222
 223 static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
 224 {
 225         r300ContextPtr r300 = R300_CONTEXT(ctx);
 226         if (mode)
 227                 r300->radeon.Fallback |= bit;
 228         else
 229                 r300->radeon.Fallback &= ~bit;
 230
 231         r300SwitchFallback(ctx, R300_FALLBACK_RADEON_COMMON, mode);
 232 }
 233
 234 static void r300_emit_query_finish(radeonContextPtr radeon)
 235 {
 236         r300ContextPtr r300 = (r300ContextPtr)radeon;
 237         struct radeon_query_object *query = radeon->query.current;
 238         BATCH_LOCALS(radeon);
 239
 240         BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2);
 241         switch (r300->radeon.radeonScreen->num_gb_pipes) {
 242         case 4:
 243                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 244                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 245                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 246         case 3:
 247                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
 248                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 249                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 250         case 2:
 251                 if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
 252                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 253                 } else {
 254                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
 255                 }
 256                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 257                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 258         case 1:
 259         default:
 260                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
 261                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 262                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 263                 break;
 264         }
 265         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 266         END_BATCH();
 267         query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t);
 268         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 269         query->emitted_begin = GL_FALSE;
 270 }
 271
 272 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
 273 {
 274         BATCH_LOCALS(radeon);
 275         struct radeon_query_object *query = radeon->query.current;
 276
 277         BEGIN_BATCH_NO_AUTOSTATE(8);
 278         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 279         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 280         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 281         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 282         END_BATCH();
 283
 284         query->curr_offset += sizeof(uint32_t);
 285         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 286         query->emitted_begin = GL_FALSE;
 287 }
 288
 289 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 290 {
 291         BATCH_LOCALS(radeon);
 292         struct radeon_query_object *query = radeon->query.current;
 293
 294         BEGIN_BATCH_NO_AUTOSTATE(14);
 295         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 296         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 297         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 298         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 299         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 300         OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 301         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 302         END_BATCH();
 303
 304         query->curr_offset += 2 * sizeof(uint32_t);
 305         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 306         query->emitted_begin = GL_FALSE;
 307 }
 308
 309 static void r300_init_vtbl(radeonContextPtr radeon)
 310 {
 311         radeon->vtbl.get_lock = r300_get_lock;
 312         radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
 313         radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
 314         radeon->vtbl.swtcl_flush = r300_swtcl_flush;
 315         radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
 316         radeon->vtbl.fallback = r300_fallback;
 317         if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 318                 if (radeon->radeonScreen->num_z_pipes == 2)
 319                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z;
 320                 else
 321                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
 322         } else
 323                 radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 324
 325         radeon->vtbl.check_blit = r300_check_blit;
 326         radeon->vtbl.blit = r300_blit;
 327
 328         if (radeon->radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 329                 radeon->vtbl.is_format_renderable = r500IsFormatRenderable;
 330         } else {
 331                 radeon->vtbl.is_format_renderable = r300IsFormatRenderable;
 332         }
 333 }
 334
 335 static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
 336 {
 337         r300ContextPtr r300 = R300_CONTEXT(ctx);
 338
 339         ctx->Const.MaxTextureImageUnits =
 340             driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
 341         ctx->Const.MaxTextureCoordUnits =
 342             driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
 343         ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
 344                  ctx->Const.MaxTextureCoordUnits);
 345         ctx->Const.MaxCombinedTextureImageUnits =
 346                 ctx->Const.MaxVertexTextureImageUnits +
 347                 ctx->Const.MaxTextureImageUnits;
 348
 349
 350         ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 351         ctx->Const.MaxTextureLodBias = 16.0;
 352
 353         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 354                 ctx->Const.MaxTextureLevels = 13;
 355                 ctx->Const.MaxCubeTextureLevels = 13;
 356                 ctx->Const.MaxTextureRectSize = 4096;
 357                 ctx->Const.MaxRenderbufferSize = 4096;
 358         }
 359         else {
 360                 ctx->Const.MaxTextureLevels = 12;
 361                 ctx->Const.MaxCubeTextureLevels = 12;
 362                 ctx->Const.MaxTextureRectSize = 2048;
 363                 ctx->Const.MaxRenderbufferSize = 2048;
 364         }
 365
 366         ctx->Const.MinPointSize = 1.0;
 367         ctx->Const.MinPointSizeAA = 1.0;
 368         ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
 369         ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
 370
 371         ctx->Const.MinLineWidth = 1.0;
 372         ctx->Const.MinLineWidthAA = 1.0;
 373         ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
 374         ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
 375
 376         ctx->Const.MaxDrawBuffers = 1;
 377         ctx->Const.MaxColorAttachments = 1;
 378
 379         /* currently bogus data */
 380         if (r300->options.hw_tcl_enabled) {
 381                 ctx->Const.VertexProgram.MaxNativeInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 382                 ctx->Const.VertexProgram.MaxNativeAluInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 383                 ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */
 384                 ctx->Const.VertexProgram.MaxNativeTemps = 32;
 385                 ctx->Const.VertexProgram.MaxNativeParameters = 256;     /* r420 */
 386                 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 387         }
 388
 389         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 390                 ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
 391                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 392
 393                 /* The hardware limits are higher than this,
 394                  * but the non-KMS DRM interface artificially limits us
 395                  * to this many instructions.
 396                  *
 397                  * We could of course work around it in the KMS path,
 398                  * but it would be a mess, so it seems wiser
 399                  * to leave it as is. Going forward, the Gallium driver
 400                  * will not be subject to these limitations.
 401                  */
 402                 ctx->Const.FragmentProgram.MaxNativeParameters = 255;
 403                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = 255;
 404                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = 255;
 405                 ctx->Const.FragmentProgram.MaxNativeInstructions = 255;
 406                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = 255;
 407                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 408         } else {
 409                 ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
 410                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 411                 ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
 412                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
 413                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
 414                 ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
 415                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
 416                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 417         }
 418
 419 }
 420
 421 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
 422 {
 423         struct r300_options options = { 0 };
 424
 425         driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
 426                             screen->driScreen->myNum, "r300");
 427
 428         r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
 429
 430         options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
 431         options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
 432         options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
 433
 434         if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
 435                 options.hw_tcl_enabled = 0;
 436         else
 437                 options.hw_tcl_enabled = 1;
 438
 439         options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
 440
 441         r300->options = options;
 442 }
 443
 444 static void r300InitGLExtensions(GLcontext *ctx)
 445 {
 446         r300ContextPtr r300 = R300_CONTEXT(ctx);
 447
 448         driInitExtensions(ctx, card_extensions, GL_TRUE);
 449         if (r300->radeon.radeonScreen->kernel_mm)
 450                 driInitExtensions(ctx, mm_extensions, GL_FALSE);
 451
 452         if (r300->options.stencil_two_side_disabled)
 453                 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
 454
 455         if (r300->options.s3tc_force_disabled) {
 456                 _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 457         } else if (ctx->Mesa_DXTn || r300->options.s3tc_force_enabled) {
 458                 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 459                 _mesa_enable_extension(ctx, "GL_S3_s3tc");
 460         }
 461
 462         if (!r300->radeon.radeonScreen->drmSupportsOcclusionQueries) {
 463                 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 464         }
 465         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350)
 466                 _mesa_enable_extension(ctx, "GL_ARB_half_float_vertex");
 467
 468         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 469                 _mesa_enable_extension(ctx, "GL_EXT_packed_depth_stencil");
 470 }
 471
 472 static void r300InitIoctlFuncs(struct dd_function_table *functions)
 473 {
 474         functions->Clear = _mesa_meta_Clear;
 475         functions->Finish = radeonFinish;
 476         functions->Flush = radeonFlush;
 477 }
 478
 479 /* Create the device specific rendering context.
 480  */
 481 GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 482                             __DRIcontext * driContextPriv,
 483                             void *sharedContextPrivate)
 484 {
 485         __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 486         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 487         struct dd_function_table functions;
 488         r300ContextPtr r300;
 489         GLcontext *ctx;
 490
 491         assert(glVisual);
 492         assert(driContextPriv);
 493         assert(screen);
 494
 495         r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
 496         if (!r300)
 497                 return GL_FALSE;
 498
 499         r300ParseOptions(r300, screen);
 500
 501         r300->radeon.radeonScreen = screen;
 502         r300_init_vtbl(&r300->radeon);
 503
 504         _mesa_init_driver_functions(&functions);
 505         r300InitIoctlFuncs(&functions);
 506         r300InitStateFuncs(&r300->radeon, &functions);
 507         r300InitTextureFuncs(&r300->radeon, &functions);
 508         r300InitShaderFuncs(&functions);
 509         radeonInitQueryObjFunctions(&functions);
 510         radeonInitBufferObjectFuncs(&functions);
 511
 512         if (!radeonInitContext(&r300->radeon, &functions,
 513                                glVisual, driContextPriv,
 514                                sharedContextPrivate)) {
 515                 FREE(r300);
 516                 return GL_FALSE;
 517         }
 518
 519         ctx = r300->radeon.glCtx;
 520
 521         r300->fallback = 0;
 522         if (r300->options.hw_tcl_enabled)
 523                 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
 524
 525         ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 526
 527         r300InitConstValues(ctx, screen);
 528
 529         _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 530
 531         /* Initialize the software rasterizer and helper modules.
 532          */
 533         _swrast_CreateContext(ctx);
 534         _vbo_CreateContext(ctx);
 535         _tnl_CreateContext(ctx);
 536         _swsetup_CreateContext(ctx);
 537         _swsetup_Wakeup(ctx);
 538
 539         /* Install the customized pipeline:
 540          */
 541         _tnl_destroy_pipeline(ctx);
 542         _tnl_install_pipeline(ctx, r300_pipeline);
 543         TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 544
 545         /* Configure swrast and TNL to match hardware characteristics:
 546          */
 547         _swrast_allow_pixel_fog(ctx, GL_FALSE);
 548         _swrast_allow_vertex_fog(ctx, GL_TRUE);
 549         _tnl_allow_pixel_fog(ctx, GL_FALSE);
 550         _tnl_allow_vertex_fog(ctx, GL_TRUE);
 551
 552         if (r300->options.hw_tcl_enabled) {
 553                 r300InitDraw(ctx);
 554         } else {
 555                 r300InitSwtcl(ctx);
 556         }
 557
 558         r300_blit_init(r300);
 559         radeon_fbo_init(&r300->radeon);
 560         radeonInitSpanFuncs( ctx );
 561         r300InitCmdBuf(r300);
 562         r300InitState(r300);
 563         r300InitShaderFunctions(r300);
 564
 565         r300InitGLExtensions(ctx);
 566
 567         return GL_TRUE;
 568 }
 569