src/mesa/drivers/dri/r300/r300_context.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  *
  35  * \author Nicolai Haehnle <prefect_@gmx.net>
  36  */
  37
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "main/imports.h"
  43 #include "main/matrix.h"
  44 #include "main/extensions.h"
  45 #include "main/state.h"
  46 #include "main/bufferobj.h"
  47 #include "main/texobj.h"
  48
  49 #include "swrast/swrast.h"
  50 #include "swrast_setup/swrast_setup.h"
  51 #include "vbo/vbo.h"
  52
  53 #include "tnl/tnl.h"
  54 #include "tnl/t_pipeline.h"
  55 #include "tnl/t_vp_build.h"
  56
  57 #include "drivers/common/driverfuncs.h"
  58
  59 #include "r300_context.h"
  60 #include "radeon_context.h"
  61 #include "radeon_span.h"
  62 #include "r300_cmdbuf.h"
  63 #include "r300_state.h"
  64 #include "r300_ioctl.h"
  65 #include "r300_tex.h"
  66 #include "r300_emit.h"
  67 #include "r300_swtcl.h"
  68 #include "radeon_bocs_wrapper.h"
  69 #include "radeon_buffer_objects.h"
  70 #include "radeon_queryobj.h"
  71
  72 #include "vblank.h"
  73 #include "utils.h"
  74 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  75
  76 #define need_GL_VERSION_2_0
  77 #define need_GL_ARB_occlusion_query
  78 #define need_GL_ARB_point_parameters
  79 #define need_GL_ARB_vertex_program
  80 #define need_GL_EXT_blend_equation_separate
  81 #define need_GL_EXT_blend_func_separate
  82 #define need_GL_EXT_blend_minmax
  83 #define need_GL_EXT_framebuffer_blit
  84 #define need_GL_EXT_framebuffer_object
  85 #define need_GL_EXT_fog_coord
  86 #define need_GL_EXT_gpu_program_parameters
  87 #define need_GL_EXT_secondary_color
  88 #define need_GL_EXT_stencil_two_side
  89 #define need_GL_ATI_separate_stencil
  90 #define need_GL_NV_vertex_program
  91
  92 #include "extension_helper.h"
  93
  94
  95 const struct dri_extension card_extensions[] = {
  96   /* *INDENT-OFF* */
  97   {"GL_ARB_depth_texture",              NULL},
  98   {"GL_ARB_fragment_program",           NULL},
  99   {"GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
 100   {"GL_ARB_multitexture",               NULL},
 101   {"GL_ARB_point_parameters",           GL_ARB_point_parameters_functions},
 102   {"GL_ARB_shadow",                     NULL},
 103   {"GL_ARB_shadow_ambient",             NULL},
 104   {"GL_ARB_texture_border_clamp",       NULL},
 105   {"GL_ARB_texture_cube_map",           NULL},
 106   {"GL_ARB_texture_env_add",            NULL},
 107   {"GL_ARB_texture_env_combine",        NULL},
 108   {"GL_ARB_texture_env_crossbar",       NULL},
 109   {"GL_ARB_texture_env_dot3",           NULL},
 110   {"GL_ARB_texture_mirrored_repeat",    NULL},
 111   {"GL_ARB_vertex_program",             GL_ARB_vertex_program_functions},
 112   {"GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions},
 113   {"GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions},
 114   {"GL_EXT_blend_minmax",               GL_EXT_blend_minmax_functions},
 115   {"GL_EXT_blend_subtract",             NULL},
 116   {"GL_EXT_packed_depth_stencil",       NULL},
 117   {"GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
 118   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
 119   {"GL_EXT_secondary_color",            GL_EXT_secondary_color_functions},
 120   {"GL_EXT_shadow_funcs",               NULL},
 121   {"GL_EXT_stencil_two_side",           GL_EXT_stencil_two_side_functions},
 122   {"GL_EXT_stencil_wrap",               NULL},
 123   {"GL_EXT_texture_edge_clamp",         NULL},
 124   {"GL_EXT_texture_env_combine",        NULL},
 125   {"GL_EXT_texture_env_dot3",           NULL},
 126   {"GL_EXT_texture_filter_anisotropic", NULL},
 127   {"GL_EXT_texture_lod_bias",           NULL},
 128   {"GL_EXT_texture_mirror_clamp",       NULL},
 129   {"GL_EXT_texture_rectangle",          NULL},
 130   {"GL_EXT_texture_sRGB",               NULL},
 131   {"GL_EXT_vertex_array_bgra",          NULL},
 132   {"GL_ATI_separate_stencil",           GL_ATI_separate_stencil_functions},
 133   {"GL_ATI_texture_env_combine3",       NULL},
 134   {"GL_ATI_texture_mirror_once",        NULL},
 135   {"GL_MESA_pack_invert",               NULL},
 136   {"GL_MESA_ycbcr_texture",             NULL},
 137   {"GL_MESAX_texture_float",            NULL},
 138   {"GL_NV_blend_square",                NULL},
 139   {"GL_NV_vertex_program",              GL_NV_vertex_program_functions},
 140   {"GL_SGIS_generate_mipmap",           NULL},
 141   {NULL,                                NULL}
 142   /* *INDENT-ON* */
 143 };
 144
 145
 146 const struct dri_extension mm_extensions[] = {
 147   { "GL_EXT_framebuffer_blit",  GL_EXT_framebuffer_blit_functions },
 148   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 149   { NULL, NULL }
 150 };
 151
 152 /**
 153  * The GL 2.0 functions are needed to make display lists work with
 154  * functions added by GL_ATI_separate_stencil.
 155  */
 156 const struct dri_extension gl_20_extension[] = {
 157   {"GL_VERSION_2_0",                    GL_VERSION_2_0_functions },
 158 };
 159
 160 static const struct tnl_pipeline_stage *r300_pipeline[] = {
 161         /* Catch any t&l fallbacks
 162          */
 163         &_tnl_vertex_transform_stage,
 164         &_tnl_normal_transform_stage,
 165         &_tnl_lighting_stage,
 166         &_tnl_fog_coordinate_stage,
 167         &_tnl_texgen_stage,
 168         &_tnl_texture_transform_stage,
 169         &_tnl_point_attenuation_stage,
 170         &_tnl_vertex_program_stage,
 171         &_tnl_render_stage,
 172         0,
 173 };
 174
 175 static void r300_get_lock(radeonContextPtr rmesa)
 176 {
 177         drm_radeon_sarea_t *sarea = rmesa->sarea;
 178
 179         if (sarea->ctx_owner != rmesa->dri.hwContext) {
 180                 sarea->ctx_owner = rmesa->dri.hwContext;
 181                 if (!rmesa->radeonScreen->kernel_mm)
 182                         radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
 183         }
 184 }
 185
 186 static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 187 {
 188     /* please flush pipe do all pending work */
 189     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 190                                   R300_SC_SCREENDOOR, 1));
 191     radeon_cs_write_dword(cs, 0x0);
 192     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 193                                   R300_SC_SCREENDOOR, 1));
 194     radeon_cs_write_dword(cs, 0x00FFFFFF);
 195     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 196                                   R300_SC_HYPERZ, 1));
 197     radeon_cs_write_dword(cs, 0x0);
 198     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 199                                   R300_US_CONFIG, 1));
 200     radeon_cs_write_dword(cs, 0x0);
 201     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 202                                   R300_ZB_CNTL, 1));
 203     radeon_cs_write_dword(cs, 0x0);
 204     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
 205     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 206                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 207     radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 208     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 209                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 210     radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 211     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
 212                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 213 }
 214
 215 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 216 {
 217         r300ContextPtr r300 = (r300ContextPtr)radeon;
 218         BATCH_LOCALS(radeon);
 219
 220         r300->vap_flush_needed = GL_TRUE;
 221
 222         cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 223         BEGIN_BATCH_NO_AUTOSTATE(2);
 224         OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
 225         END_BATCH();
 226         end_3d(radeon);
 227 }
 228
 229 static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
 230 {
 231         r300ContextPtr r300 = R300_CONTEXT(ctx);
 232         if (mode)
 233                 r300->radeon.Fallback |= bit;
 234         else
 235                 r300->radeon.Fallback &= ~bit;
 236 }
 237
 238 static void r300_emit_query_finish(radeonContextPtr radeon)
 239 {
 240         r300ContextPtr r300 = (r300ContextPtr)radeon;
 241         struct radeon_query_object *query = radeon->query.current;
 242         BATCH_LOCALS(radeon);
 243
 244         BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->num_z_pipes + 2);
 245         switch (r300->num_z_pipes) {
 246         case 4:
 247                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 248                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 249                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 250         case 3:
 251                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
 252                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 253                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 254         case 2:
 255                 if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
 256                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 257                 } else {
 258                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
 259                 }
 260                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 261                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 262         case 1:
 263         default:
 264                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
 265                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 266                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 267                 break;
 268         }
 269         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 270         END_BATCH();
 271         query->curr_offset += r300->num_z_pipes * sizeof(uint32_t);
 272         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 273         query->emitted_begin = GL_FALSE;
 274 }
 275
 276 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
 277 {
 278         BATCH_LOCALS(radeon);
 279         struct radeon_query_object *query = radeon->query.current;
 280
 281         BEGIN_BATCH_NO_AUTOSTATE(8);
 282         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 283         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 284         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 285         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 286         END_BATCH();
 287
 288         query->curr_offset += sizeof(uint32_t);
 289         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 290         query->emitted_begin = GL_FALSE;
 291 }
 292
 293 #if 0
 294 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 295 {
 296         r300ContextPtr r300 = (r300ContextPtr)radeon;
 297         BATCH_LOCALS(radeon);
 298         struct radeon_query_object *query = radeon->query.current;
 299
 300         BEGIN_BATCH_NO_AUTOSTATE(6);
 301         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 302         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 303         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 304         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 305         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 306         OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 307         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 308         END_BATCH();
 309
 310         query->curr_offset += 2 * sizeof(uint32_t);
 311         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 312         query->emitted_begin = GL_FALSE;
 313 }
 314 #endif
 315
 316 static void r300_init_vtbl(radeonContextPtr radeon)
 317 {
 318         radeon->vtbl.get_lock = r300_get_lock;
 319         radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
 320         radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
 321         radeon->vtbl.swtcl_flush = r300_swtcl_flush;
 322         radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
 323         radeon->vtbl.fallback = r300_fallback;
 324         if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530)
 325                 /* single Z gives me correct results on my hw need to check if we ever need
 326                  * double z */
 327                 radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
 328         else
 329                 radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 330 }
 331
 332 static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
 333 {
 334         r300ContextPtr r300 = R300_CONTEXT(ctx);
 335
 336         ctx->Const.MaxTextureImageUnits =
 337             driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
 338         ctx->Const.MaxTextureCoordUnits =
 339             driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
 340         ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
 341                  ctx->Const.MaxTextureCoordUnits);
 342
 343         ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 344         ctx->Const.MaxTextureLodBias = 16.0;
 345
 346         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 347                 ctx->Const.MaxTextureLevels = 13;
 348                 ctx->Const.MaxCubeTextureLevels = 13;
 349                 ctx->Const.MaxTextureRectSize = 4096;
 350         }
 351         else {
 352                 ctx->Const.MaxTextureLevels = 12;
 353                 ctx->Const.MaxCubeTextureLevels = 12;
 354                 ctx->Const.MaxTextureRectSize = 2048;
 355         }
 356
 357         ctx->Const.MinPointSize = 1.0;
 358         ctx->Const.MinPointSizeAA = 1.0;
 359         ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
 360         ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
 361
 362         ctx->Const.MinLineWidth = 1.0;
 363         ctx->Const.MinLineWidthAA = 1.0;
 364         ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
 365         ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
 366
 367         ctx->Const.MaxDrawBuffers = 1;
 368
 369         /* currently bogus data */
 370         if (r300->options.hw_tcl_enabled) {
 371                 ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 372                 ctx->Const.VertexProgram.MaxNativeInstructions =
 373                   VSF_MAX_FRAGMENT_LENGTH / 4;
 374                 ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */
 375                 ctx->Const.VertexProgram.MaxTemps = 32;
 376                 ctx->Const.VertexProgram.MaxNativeTemps =
 377                   /*VSF_MAX_FRAGMENT_TEMPS */ 32;
 378                 ctx->Const.VertexProgram.MaxNativeParameters = 256;     /* r420 */
 379                 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 380         }
 381
 382         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 383                 ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
 384                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 385                 ctx->Const.FragmentProgram.MaxNativeParameters = R500_PFS_NUM_CONST_REGS;
 386                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R500_PFS_MAX_INST;
 387                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R500_PFS_MAX_INST;
 388                 ctx->Const.FragmentProgram.MaxNativeInstructions = R500_PFS_MAX_INST;
 389                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R500_PFS_MAX_INST;
 390                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 391         } else {
 392                 ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
 393                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 394                 ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
 395                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
 396                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
 397                 ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
 398                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
 399                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 400         }
 401
 402         if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530)
 403                 r300->num_z_pipes = 2;
 404         else
 405                 r300->num_z_pipes = r300->radeon.radeonScreen->num_gb_pipes;
 406 }
 407
 408 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
 409 {
 410         struct r300_options options = { 0 };
 411
 412         driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
 413                             screen->driScreen->myNum, "r300");
 414
 415         r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
 416
 417         options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
 418         options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
 419         options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
 420
 421         if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
 422                 options.hw_tcl_enabled = 0;
 423         else
 424                 options.hw_tcl_enabled = 1;
 425
 426         options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
 427
 428         r300->options = options;
 429 }
 430
 431 static void r300InitGLExtensions(GLcontext *ctx)
 432 {
 433         r300ContextPtr r300 = R300_CONTEXT(ctx);
 434
 435         driInitExtensions(ctx, card_extensions, GL_TRUE);
 436         if (r300->radeon.radeonScreen->kernel_mm)
 437                 driInitExtensions(ctx, mm_extensions, GL_FALSE);
 438
 439         if (r300->options.stencil_two_side_disabled)
 440                 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
 441
 442         if (ctx->Mesa_DXTn && !r300->options.s3tc_force_enabled) {
 443                 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 444                 _mesa_enable_extension(ctx, "GL_S3_s3tc");
 445         } else if (r300->options.s3tc_force_disabled) {
 446                 _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 447         }
 448
 449         if (!r300->radeon.radeonScreen->drmSupportsOcclusionQueries) {
 450                 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 451         }
 452 }
 453
 454 /* Create the device specific rendering context.
 455  */
 456 GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 457                             __DRIcontextPrivate * driContextPriv,
 458                             void *sharedContextPrivate)
 459 {
 460         __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 461         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 462         struct dd_function_table functions;
 463         r300ContextPtr r300;
 464         GLcontext *ctx;
 465
 466         assert(glVisual);
 467         assert(driContextPriv);
 468         assert(screen);
 469
 470         r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
 471         if (!r300)
 472                 return GL_FALSE;
 473
 474         r300ParseOptions(r300, screen);
 475
 476         r300->radeon.radeonScreen = screen;
 477         r300_init_vtbl(&r300->radeon);
 478
 479         _mesa_init_driver_functions(&functions);
 480         r300InitIoctlFuncs(&functions);
 481         r300InitStateFuncs(&functions);
 482         r300InitTextureFuncs(&functions);
 483         r300InitShaderFuncs(&functions);
 484         radeonInitQueryObjFunctions(&functions);
 485         radeonInitBufferObjectFuncs(&functions);
 486
 487         if (!radeonInitContext(&r300->radeon, &functions,
 488                                glVisual, driContextPriv,
 489                                sharedContextPrivate)) {
 490                 FREE(r300);
 491                 return GL_FALSE;
 492         }
 493
 494         ctx = r300->radeon.glCtx;
 495
 496         r300->fallback = 0;
 497         if (r300->options.hw_tcl_enabled)
 498                 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
 499
 500         ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 501
 502         r300InitConstValues(ctx, screen);
 503
 504         _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 505
 506         /* Initialize the software rasterizer and helper modules.
 507          */
 508         _swrast_CreateContext(ctx);
 509         _vbo_CreateContext(ctx);
 510         _tnl_CreateContext(ctx);
 511         _swsetup_CreateContext(ctx);
 512         _swsetup_Wakeup(ctx);
 513
 514         /* Install the customized pipeline:
 515          */
 516         _tnl_destroy_pipeline(ctx);
 517         _tnl_install_pipeline(ctx, r300_pipeline);
 518         TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 519
 520         /* Configure swrast and TNL to match hardware characteristics:
 521          */
 522         _swrast_allow_pixel_fog(ctx, GL_FALSE);
 523         _swrast_allow_vertex_fog(ctx, GL_TRUE);
 524         _tnl_allow_pixel_fog(ctx, GL_FALSE);
 525         _tnl_allow_vertex_fog(ctx, GL_TRUE);
 526
 527         if (r300->options.hw_tcl_enabled) {
 528                 r300InitDraw(ctx);
 529         } else {
 530                 r300InitSwtcl(ctx);
 531         }
 532
 533         radeon_fbo_init(&r300->radeon);
 534         radeonInitSpanFuncs( ctx );
 535         r300InitCmdBuf(r300);
 536         r300InitState(r300);
 537         r300InitShaderFunctions(r300);
 538
 539         r300InitGLExtensions(ctx);
 540
 541         return GL_TRUE;
 542 }
 543