src/mesa/drivers/dri/r300/r300_context.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  *
  35  * \author Nicolai Haehnle <prefect_@gmx.net>
  36  */
  37
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "main/imports.h"
  43 #include "main/matrix.h"
  44 #include "main/extensions.h"
  45 #include "main/state.h"
  46 #include "main/bufferobj.h"
  47 #include "main/texobj.h"
  48
  49 #include "swrast/swrast.h"
  50 #include "swrast_setup/swrast_setup.h"
  51 #include "vbo/vbo.h"
  52
  53 #include "tnl/tnl.h"
  54 #include "tnl/t_pipeline.h"
  55 #include "tnl/t_vp_build.h"
  56
  57 #include "drivers/common/driverfuncs.h"
  58
  59 #include "r300_context.h"
  60 #include "radeon_context.h"
  61 #include "radeon_span.h"
  62 #include "r300_cmdbuf.h"
  63 #include "r300_state.h"
  64 #include "r300_ioctl.h"
  65 #include "r300_tex.h"
  66 #include "r300_emit.h"
  67 #include "r300_swtcl.h"
  68 #include "radeon_bocs_wrapper.h"
  69 #include "radeon_buffer_objects.h"
  70 #include "radeon_queryobj.h"
  71
  72 #include "vblank.h"
  73 #include "utils.h"
  74 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  75
  76 #define need_GL_VERSION_2_0
  77 #define need_GL_ARB_occlusion_query
  78 #define need_GL_ARB_point_parameters
  79 #define need_GL_ARB_vertex_program
  80 #define need_GL_EXT_blend_equation_separate
  81 #define need_GL_EXT_blend_func_separate
  82 #define need_GL_EXT_blend_minmax
  83 #define need_GL_EXT_framebuffer_blit
  84 #define need_GL_EXT_framebuffer_object
  85 #define need_GL_EXT_fog_coord
  86 #define need_GL_EXT_gpu_program_parameters
  87 #define need_GL_EXT_provoking_vertex
  88 #define need_GL_EXT_secondary_color
  89 #define need_GL_EXT_stencil_two_side
  90 #define need_GL_ATI_separate_stencil
  91 #define need_GL_NV_vertex_program
  92
  93 #include "extension_helper.h"
  94
  95
  96 const struct dri_extension card_extensions[] = {
  97   /* *INDENT-OFF* */
  98   {"GL_ARB_depth_texture",              NULL},
  99   {"GL_ARB_fragment_program",           NULL},
 100   {"GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
 101   {"GL_ARB_multitexture",               NULL},
 102   {"GL_ARB_point_parameters",           GL_ARB_point_parameters_functions},
 103   {"GL_ARB_shadow",                     NULL},
 104   {"GL_ARB_shadow_ambient",             NULL},
 105   {"GL_ARB_texture_border_clamp",       NULL},
 106   {"GL_ARB_texture_cube_map",           NULL},
 107   {"GL_ARB_texture_env_add",            NULL},
 108   {"GL_ARB_texture_env_combine",        NULL},
 109   {"GL_ARB_texture_env_crossbar",       NULL},
 110   {"GL_ARB_texture_env_dot3",           NULL},
 111   {"GL_ARB_texture_mirrored_repeat",    NULL},
 112   {"GL_ARB_vertex_program",             GL_ARB_vertex_program_functions},
 113   {"GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions},
 114   {"GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions},
 115   {"GL_EXT_blend_minmax",               GL_EXT_blend_minmax_functions},
 116   {"GL_EXT_blend_subtract",             NULL},
 117   {"GL_EXT_packed_depth_stencil",       NULL},
 118   {"GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
 119   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
 120   {"GL_EXT_provoking_vertex",           GL_EXT_provoking_vertex_functions },
 121   {"GL_EXT_secondary_color",            GL_EXT_secondary_color_functions},
 122   {"GL_EXT_shadow_funcs",               NULL},
 123   {"GL_EXT_stencil_two_side",           GL_EXT_stencil_two_side_functions},
 124   {"GL_EXT_stencil_wrap",               NULL},
 125   {"GL_EXT_texture_edge_clamp",         NULL},
 126   {"GL_EXT_texture_env_combine",        NULL},
 127   {"GL_EXT_texture_env_dot3",           NULL},
 128   {"GL_EXT_texture_filter_anisotropic", NULL},
 129   {"GL_EXT_texture_lod_bias",           NULL},
 130   {"GL_EXT_texture_mirror_clamp",       NULL},
 131   {"GL_EXT_texture_rectangle",          NULL},
 132   {"GL_EXT_texture_sRGB",               NULL},
 133   {"GL_EXT_vertex_array_bgra",          NULL},
 134   {"GL_ATI_separate_stencil",           GL_ATI_separate_stencil_functions},
 135   {"GL_ATI_texture_env_combine3",       NULL},
 136   {"GL_ATI_texture_mirror_once",        NULL},
 137   {"GL_MESA_pack_invert",               NULL},
 138   {"GL_MESA_ycbcr_texture",             NULL},
 139   {"GL_MESAX_texture_float",            NULL},
 140   {"GL_NV_blend_square",                NULL},
 141   {"GL_NV_vertex_program",              GL_NV_vertex_program_functions},
 142   {"GL_SGIS_generate_mipmap",           NULL},
 143   {NULL,                                NULL}
 144   /* *INDENT-ON* */
 145 };
 146
 147
 148 const struct dri_extension mm_extensions[] = {
 149   { "GL_EXT_framebuffer_blit",  GL_EXT_framebuffer_blit_functions },
 150   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 151   { NULL, NULL }
 152 };
 153
 154 /**
 155  * The GL 2.0 functions are needed to make display lists work with
 156  * functions added by GL_ATI_separate_stencil.
 157  */
 158 const struct dri_extension gl_20_extension[] = {
 159   {"GL_VERSION_2_0",                    GL_VERSION_2_0_functions },
 160 };
 161
 162 static const struct tnl_pipeline_stage *r300_pipeline[] = {
 163         /* Catch any t&l fallbacks
 164          */
 165         &_tnl_vertex_transform_stage,
 166         &_tnl_normal_transform_stage,
 167         &_tnl_lighting_stage,
 168         &_tnl_fog_coordinate_stage,
 169         &_tnl_texgen_stage,
 170         &_tnl_texture_transform_stage,
 171         &_tnl_point_attenuation_stage,
 172         &_tnl_vertex_program_stage,
 173         &_tnl_render_stage,
 174         0,
 175 };
 176
 177 static void r300_get_lock(radeonContextPtr rmesa)
 178 {
 179         drm_radeon_sarea_t *sarea = rmesa->sarea;
 180
 181         if (sarea->ctx_owner != rmesa->dri.hwContext) {
 182                 sarea->ctx_owner = rmesa->dri.hwContext;
 183                 if (!rmesa->radeonScreen->kernel_mm)
 184                         radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
 185         }
 186 }
 187
 188 static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 189 {
 190     /* please flush pipe do all pending work */
 191     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 192                                   R300_SC_SCREENDOOR, 1));
 193     radeon_cs_write_dword(cs, 0x0);
 194     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 195                                   R300_SC_SCREENDOOR, 1));
 196     radeon_cs_write_dword(cs, 0x00FFFFFF);
 197     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 198                                   R300_SC_HYPERZ, 1));
 199     radeon_cs_write_dword(cs, 0x0);
 200     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 201                                   R300_US_CONFIG, 1));
 202     radeon_cs_write_dword(cs, 0x0);
 203     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 204                                   R300_ZB_CNTL, 1));
 205     radeon_cs_write_dword(cs, 0x0);
 206     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
 207     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 208                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 209     radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 210     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 211                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 212     radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 213     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
 214                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 215 }
 216
 217 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 218 {
 219         BATCH_LOCALS(radeon);
 220
 221         cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 222         BEGIN_BATCH_NO_AUTOSTATE(2);
 223         OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
 224         END_BATCH();
 225         end_3d(radeon);
 226 }
 227
 228 static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
 229 {
 230         r300ContextPtr r300 = R300_CONTEXT(ctx);
 231         if (mode)
 232                 r300->radeon.Fallback |= bit;
 233         else
 234                 r300->radeon.Fallback &= ~bit;
 235 }
 236
 237 static void r300_emit_query_finish(radeonContextPtr radeon)
 238 {
 239         r300ContextPtr r300 = (r300ContextPtr)radeon;
 240         struct radeon_query_object *query = radeon->query.current;
 241         BATCH_LOCALS(radeon);
 242
 243         BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2);
 244         switch (r300->radeon.radeonScreen->num_gb_pipes) {
 245         case 4:
 246                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 247                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 248                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 249         case 3:
 250                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
 251                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 252                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 253         case 2:
 254                 if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
 255                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 256                 } else {
 257                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
 258                 }
 259                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 260                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 261         case 1:
 262         default:
 263                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
 264                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 265                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 266                 break;
 267         }
 268         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 269         END_BATCH();
 270         query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t);
 271         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 272         query->emitted_begin = GL_FALSE;
 273 }
 274
 275 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
 276 {
 277         BATCH_LOCALS(radeon);
 278         struct radeon_query_object *query = radeon->query.current;
 279
 280         BEGIN_BATCH_NO_AUTOSTATE(8);
 281         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 282         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 283         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 284         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 285         END_BATCH();
 286
 287         query->curr_offset += sizeof(uint32_t);
 288         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 289         query->emitted_begin = GL_FALSE;
 290 }
 291
 292 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 293 {
 294         BATCH_LOCALS(radeon);
 295         struct radeon_query_object *query = radeon->query.current;
 296
 297         BEGIN_BATCH_NO_AUTOSTATE(14);
 298         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 299         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 300         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 301         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 302         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 303         OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 304         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 305         END_BATCH();
 306
 307         query->curr_offset += 2 * sizeof(uint32_t);
 308         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 309         query->emitted_begin = GL_FALSE;
 310 }
 311
 312 static void r300_init_vtbl(radeonContextPtr radeon)
 313 {
 314         radeon->vtbl.get_lock = r300_get_lock;
 315         radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
 316         radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
 317         radeon->vtbl.swtcl_flush = r300_swtcl_flush;
 318         radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
 319         radeon->vtbl.fallback = r300_fallback;
 320         if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 321                 if (radeon->radeonScreen->num_z_pipes == 2)
 322                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z;
 323                 else
 324                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
 325         } else
 326                 radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 327 }
 328
 329 static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
 330 {
 331         r300ContextPtr r300 = R300_CONTEXT(ctx);
 332
 333         ctx->Const.MaxTextureImageUnits =
 334             driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
 335         ctx->Const.MaxTextureCoordUnits =
 336             driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
 337         ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
 338                  ctx->Const.MaxTextureCoordUnits);
 339
 340         ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 341         ctx->Const.MaxTextureLodBias = 16.0;
 342
 343         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 344                 ctx->Const.MaxTextureLevels = 13;
 345                 ctx->Const.MaxCubeTextureLevels = 13;
 346                 ctx->Const.MaxTextureRectSize = 4096;
 347         }
 348         else {
 349                 ctx->Const.MaxTextureLevels = 12;
 350                 ctx->Const.MaxCubeTextureLevels = 12;
 351                 ctx->Const.MaxTextureRectSize = 2048;
 352         }
 353
 354         ctx->Const.MinPointSize = 1.0;
 355         ctx->Const.MinPointSizeAA = 1.0;
 356         ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
 357         ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
 358
 359         ctx->Const.MinLineWidth = 1.0;
 360         ctx->Const.MinLineWidthAA = 1.0;
 361         ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
 362         ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
 363
 364         ctx->Const.MaxDrawBuffers = 1;
 365
 366         /* currently bogus data */
 367         if (r300->options.hw_tcl_enabled) {
 368                 ctx->Const.VertexProgram.MaxNativeInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 369                 ctx->Const.VertexProgram.MaxNativeAluInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 370                 ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */
 371                 ctx->Const.VertexProgram.MaxNativeTemps = 32;
 372                 ctx->Const.VertexProgram.MaxNativeParameters = 256;     /* r420 */
 373                 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 374         }
 375
 376         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 377                 ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
 378                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 379                 ctx->Const.FragmentProgram.MaxNativeParameters = R500_PFS_NUM_CONST_REGS;
 380                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R500_PFS_MAX_INST;
 381                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R500_PFS_MAX_INST;
 382                 ctx->Const.FragmentProgram.MaxNativeInstructions = R500_PFS_MAX_INST;
 383                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R500_PFS_MAX_INST;
 384                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 385         } else {
 386                 ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
 387                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 388                 ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
 389                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
 390                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
 391                 ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
 392                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
 393                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 394         }
 395
 396 }
 397
 398 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
 399 {
 400         struct r300_options options = { 0 };
 401
 402         driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
 403                             screen->driScreen->myNum, "r300");
 404
 405         r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
 406
 407         options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
 408         options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
 409         options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
 410
 411         if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
 412                 options.hw_tcl_enabled = 0;
 413         else
 414                 options.hw_tcl_enabled = 1;
 415
 416         options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
 417
 418         r300->options = options;
 419 }
 420
 421 static void r300InitGLExtensions(GLcontext *ctx)
 422 {
 423         r300ContextPtr r300 = R300_CONTEXT(ctx);
 424
 425         driInitExtensions(ctx, card_extensions, GL_TRUE);
 426         if (r300->radeon.radeonScreen->kernel_mm)
 427                 driInitExtensions(ctx, mm_extensions, GL_FALSE);
 428
 429         if (r300->options.stencil_two_side_disabled)
 430                 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
 431
 432         if (r300->options.s3tc_force_enabled) {
 433                 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 434                 _mesa_enable_extension(ctx, "GL_S3_s3tc");
 435         } else if (r300->options.s3tc_force_disabled) {
 436                 _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 437         }
 438
 439         if (!r300->radeon.radeonScreen->drmSupportsOcclusionQueries) {
 440                 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 441         }
 442 }
 443
 444 /* Create the device specific rendering context.
 445  */
 446 GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 447                             __DRIcontextPrivate * driContextPriv,
 448                             void *sharedContextPrivate)
 449 {
 450         __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 451         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 452         struct dd_function_table functions;
 453         r300ContextPtr r300;
 454         GLcontext *ctx;
 455
 456         assert(glVisual);
 457         assert(driContextPriv);
 458         assert(screen);
 459
 460         r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
 461         if (!r300)
 462                 return GL_FALSE;
 463
 464         r300ParseOptions(r300, screen);
 465
 466         r300->radeon.radeonScreen = screen;
 467         r300_init_vtbl(&r300->radeon);
 468
 469         _mesa_init_driver_functions(&functions);
 470         r300InitIoctlFuncs(&functions);
 471         r300InitStateFuncs(&functions);
 472         r300InitTextureFuncs(&functions);
 473         r300InitShaderFuncs(&functions);
 474         radeonInitQueryObjFunctions(&functions);
 475         radeonInitBufferObjectFuncs(&functions);
 476
 477         if (!radeonInitContext(&r300->radeon, &functions,
 478                                glVisual, driContextPriv,
 479                                sharedContextPrivate)) {
 480                 FREE(r300);
 481                 return GL_FALSE;
 482         }
 483
 484         ctx = r300->radeon.glCtx;
 485
 486         r300->fallback = 0;
 487         if (r300->options.hw_tcl_enabled)
 488                 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
 489
 490         ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 491
 492         r300InitConstValues(ctx, screen);
 493
 494         _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 495
 496         /* Initialize the software rasterizer and helper modules.
 497          */
 498         _swrast_CreateContext(ctx);
 499         _vbo_CreateContext(ctx);
 500         _tnl_CreateContext(ctx);
 501         _swsetup_CreateContext(ctx);
 502         _swsetup_Wakeup(ctx);
 503
 504         /* Install the customized pipeline:
 505          */
 506         _tnl_destroy_pipeline(ctx);
 507         _tnl_install_pipeline(ctx, r300_pipeline);
 508         TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 509
 510         /* Configure swrast and TNL to match hardware characteristics:
 511          */
 512         _swrast_allow_pixel_fog(ctx, GL_FALSE);
 513         _swrast_allow_vertex_fog(ctx, GL_TRUE);
 514         _tnl_allow_pixel_fog(ctx, GL_FALSE);
 515         _tnl_allow_vertex_fog(ctx, GL_TRUE);
 516
 517         if (r300->options.hw_tcl_enabled) {
 518                 r300InitDraw(ctx);
 519         } else {
 520                 r300InitSwtcl(ctx);
 521         }
 522
 523         radeon_fbo_init(&r300->radeon);
 524         radeonInitSpanFuncs( ctx );
 525         r300InitCmdBuf(r300);
 526         r300InitState(r300);
 527         r300InitShaderFunctions(r300);
 528
 529         r300InitGLExtensions(ctx);
 530
 531         return GL_TRUE;
 532 }
 533