src/mesa/drivers/dri/r300/r300_context.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  *
  35  * \author Nicolai Haehnle <prefect_@gmx.net>
  36  */
  37
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "main/imports.h"
  43 #include "main/matrix.h"
  44 #include "main/extensions.h"
  45 #include "main/state.h"
  46 #include "main/bufferobj.h"
  47 #include "main/texobj.h"
  48
  49 #include "swrast/swrast.h"
  50 #include "swrast_setup/swrast_setup.h"
  51 #include "vbo/vbo.h"
  52
  53 #include "tnl/tnl.h"
  54 #include "tnl/t_pipeline.h"
  55 #include "tnl/t_vp_build.h"
  56
  57 #include "drivers/common/driverfuncs.h"
  58
  59 #include "r300_context.h"
  60 #include "radeon_context.h"
  61 #include "radeon_span.h"
  62 #include "r300_cmdbuf.h"
  63 #include "r300_state.h"
  64 #include "r300_ioctl.h"
  65 #include "r300_tex.h"
  66 #include "r300_emit.h"
  67 #include "r300_swtcl.h"
  68 #include "radeon_bocs_wrapper.h"
  69 #include "radeon_buffer_objects.h"
  70 #include "radeon_queryobj.h"
  71
  72 #include "vblank.h"
  73 #include "utils.h"
  74 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  75
  76 #define need_GL_VERSION_2_0
  77 #define need_GL_ARB_occlusion_query
  78 #define need_GL_ARB_point_parameters
  79 #define need_GL_ARB_vertex_program
  80 #define need_GL_EXT_blend_equation_separate
  81 #define need_GL_EXT_blend_func_separate
  82 #define need_GL_EXT_blend_minmax
  83 #define need_GL_EXT_framebuffer_object
  84 #define need_GL_EXT_fog_coord
  85 #define need_GL_EXT_gpu_program_parameters
  86 #define need_GL_EXT_secondary_color
  87 #define need_GL_EXT_stencil_two_side
  88 #define need_GL_ATI_separate_stencil
  89 #define need_GL_NV_vertex_program
  90
  91 #include "extension_helper.h"
  92
  93
  94 const struct dri_extension card_extensions[] = {
  95   /* *INDENT-OFF* */
  96   {"GL_ARB_depth_texture",              NULL},
  97   {"GL_ARB_fragment_program",           NULL},
  98   {"GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  99   {"GL_ARB_multitexture",               NULL},
 100   {"GL_ARB_point_parameters",           GL_ARB_point_parameters_functions},
 101   {"GL_ARB_shadow",                     NULL},
 102   {"GL_ARB_shadow_ambient",             NULL},
 103   {"GL_ARB_texture_border_clamp",       NULL},
 104   {"GL_ARB_texture_cube_map",           NULL},
 105   {"GL_ARB_texture_env_add",            NULL},
 106   {"GL_ARB_texture_env_combine",        NULL},
 107   {"GL_ARB_texture_env_crossbar",       NULL},
 108   {"GL_ARB_texture_env_dot3",           NULL},
 109   {"GL_ARB_texture_mirrored_repeat",    NULL},
 110   {"GL_ARB_vertex_program",             GL_ARB_vertex_program_functions},
 111   {"GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions},
 112   {"GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions},
 113   {"GL_EXT_blend_minmax",               GL_EXT_blend_minmax_functions},
 114   {"GL_EXT_blend_subtract",             NULL},
 115   {"GL_EXT_packed_depth_stencil",       NULL},
 116   {"GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
 117   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
 118   {"GL_EXT_secondary_color",            GL_EXT_secondary_color_functions},
 119   {"GL_EXT_shadow_funcs",               NULL},
 120   {"GL_EXT_stencil_two_side",           GL_EXT_stencil_two_side_functions},
 121   {"GL_EXT_stencil_wrap",               NULL},
 122   {"GL_EXT_texture_edge_clamp",         NULL},
 123   {"GL_EXT_texture_env_combine",        NULL},
 124   {"GL_EXT_texture_env_dot3",           NULL},
 125   {"GL_EXT_texture_filter_anisotropic", NULL},
 126   {"GL_EXT_texture_lod_bias",           NULL},
 127   {"GL_EXT_texture_mirror_clamp",       NULL},
 128   {"GL_EXT_texture_rectangle",          NULL},
 129   {"GL_EXT_texture_sRGB",               NULL},
 130   {"GL_EXT_vertex_array_bgra",          NULL},
 131   {"GL_ATI_separate_stencil",           GL_ATI_separate_stencil_functions},
 132   {"GL_ATI_texture_env_combine3",       NULL},
 133   {"GL_ATI_texture_mirror_once",        NULL},
 134   {"GL_MESA_pack_invert",               NULL},
 135   {"GL_MESA_ycbcr_texture",             NULL},
 136   {"GL_MESAX_texture_float",            NULL},
 137   {"GL_NV_blend_square",                NULL},
 138   {"GL_NV_vertex_program",              GL_NV_vertex_program_functions},
 139   {"GL_SGIS_generate_mipmap",           NULL},
 140   {NULL,                                NULL}
 141   /* *INDENT-ON* */
 142 };
 143
 144
 145 const struct dri_extension mm_extensions[] = {
 146   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 147   { NULL, NULL }
 148 };
 149
 150 /**
 151  * The GL 2.0 functions are needed to make display lists work with
 152  * functions added by GL_ATI_separate_stencil.
 153  */
 154 const struct dri_extension gl_20_extension[] = {
 155   {"GL_VERSION_2_0",                    GL_VERSION_2_0_functions },
 156 };
 157
 158 static const struct tnl_pipeline_stage *r300_pipeline[] = {
 159         /* Catch any t&l fallbacks
 160          */
 161         &_tnl_vertex_transform_stage,
 162         &_tnl_normal_transform_stage,
 163         &_tnl_lighting_stage,
 164         &_tnl_fog_coordinate_stage,
 165         &_tnl_texgen_stage,
 166         &_tnl_texture_transform_stage,
 167         &_tnl_point_attenuation_stage,
 168         &_tnl_vertex_program_stage,
 169         &_tnl_render_stage,
 170         0,
 171 };
 172
 173 static void r300_get_lock(radeonContextPtr rmesa)
 174 {
 175         drm_radeon_sarea_t *sarea = rmesa->sarea;
 176
 177         if (sarea->ctx_owner != rmesa->dri.hwContext) {
 178                 sarea->ctx_owner = rmesa->dri.hwContext;
 179                 if (!rmesa->radeonScreen->kernel_mm)
 180                         radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
 181         }
 182 }
 183
 184 static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 185 {
 186     /* please flush pipe do all pending work */
 187     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 188                                   R300_SC_SCREENDOOR, 1));
 189     radeon_cs_write_dword(cs, 0x0);
 190     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 191                                   R300_SC_SCREENDOOR, 1));
 192     radeon_cs_write_dword(cs, 0x00FFFFFF);
 193     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 194                                   R300_SC_HYPERZ, 1));
 195     radeon_cs_write_dword(cs, 0x0);
 196     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 197                                   R300_US_CONFIG, 1));
 198     radeon_cs_write_dword(cs, 0x0);
 199     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 200                                   R300_ZB_CNTL, 1));
 201     radeon_cs_write_dword(cs, 0x0);
 202     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
 203     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 204                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 205     radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 206     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 207                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 208     radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 209     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
 210                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 211 }
 212
 213 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 214 {
 215         BATCH_LOCALS(radeon);
 216
 217         cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 218         BEGIN_BATCH_NO_AUTOSTATE(2);
 219         OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
 220         END_BATCH();
 221         end_3d(radeon);
 222 }
 223
 224 static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
 225 {
 226         r300ContextPtr r300 = R300_CONTEXT(ctx);
 227         if (mode)
 228                 r300->radeon.Fallback |= bit;
 229         else
 230                 r300->radeon.Fallback &= ~bit;
 231 }
 232
 233 static void r300_emit_query_finish(radeonContextPtr radeon)
 234 {
 235         r300ContextPtr r300 = (r300ContextPtr)radeon;
 236         struct radeon_query_object *query = radeon->query.current;
 237         BATCH_LOCALS(radeon);
 238
 239         BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->num_z_pipes + 2);
 240         switch (r300->num_z_pipes) {
 241         case 4:
 242                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 243                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 244                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 245         case 3:
 246                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
 247                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 248                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 249         case 2:
 250                 if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
 251                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 252                 } else {
 253                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
 254                 }
 255                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 256                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 257         case 1:
 258         default:
 259                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
 260                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 261                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 262                 break;
 263         }
 264         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 265         END_BATCH();
 266         query->curr_offset += r300->num_z_pipes * sizeof(uint32_t);
 267         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 268         query->emitted_begin = GL_FALSE;
 269 }
 270
 271 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
 272 {
 273         BATCH_LOCALS(radeon);
 274         struct radeon_query_object *query = radeon->query.current;
 275
 276         BEGIN_BATCH_NO_AUTOSTATE(8);
 277         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 278         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 279         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 280         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 281         END_BATCH();
 282
 283         query->curr_offset += sizeof(uint32_t);
 284         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 285         query->emitted_begin = GL_FALSE;
 286 }
 287
 288 #if 0
 289 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 290 {
 291         r300ContextPtr r300 = (r300ContextPtr)radeon;
 292         BATCH_LOCALS(radeon);
 293         struct radeon_query_object *query = radeon->query.current;
 294
 295         BEGIN_BATCH_NO_AUTOSTATE(6);
 296         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 297         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 298         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 299         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 300         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 301         OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 302         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 303         END_BATCH();
 304
 305         query->curr_offset += 2 * sizeof(uint32_t);
 306         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 307         query->emitted_begin = GL_FALSE;
 308 }
 309 #endif
 310
 311 static void r300_init_vtbl(radeonContextPtr radeon)
 312 {
 313         radeon->vtbl.get_lock = r300_get_lock;
 314         radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
 315         radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
 316         radeon->vtbl.swtcl_flush = r300_swtcl_flush;
 317         radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
 318         radeon->vtbl.fallback = r300_fallback;
 319         if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530)
 320                 /* single Z gives me correct results on my hw need to check if we ever need
 321                  * double z */
 322                 radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
 323         else
 324                 radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 325 }
 326
 327 static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
 328 {
 329         r300ContextPtr r300 = R300_CONTEXT(ctx);
 330
 331         ctx->Const.MaxTextureImageUnits =
 332             driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
 333         ctx->Const.MaxTextureCoordUnits =
 334             driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
 335         ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
 336                  ctx->Const.MaxTextureCoordUnits);
 337
 338         ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 339         ctx->Const.MaxTextureLodBias = 16.0;
 340
 341         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 342                 ctx->Const.MaxTextureLevels = 13;
 343                 ctx->Const.MaxCubeTextureLevels = 13;
 344                 ctx->Const.MaxTextureRectSize = 4096;
 345         }
 346         else {
 347                 ctx->Const.MaxTextureLevels = 12;
 348                 ctx->Const.MaxCubeTextureLevels = 12;
 349                 ctx->Const.MaxTextureRectSize = 2048;
 350         }
 351
 352         ctx->Const.MinPointSize = 1.0;
 353         ctx->Const.MinPointSizeAA = 1.0;
 354         ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
 355         ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
 356
 357         ctx->Const.MinLineWidth = 1.0;
 358         ctx->Const.MinLineWidthAA = 1.0;
 359         ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
 360         ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
 361
 362         ctx->Const.MaxDrawBuffers = 1;
 363
 364         /* currently bogus data */
 365         if (r300->options.hw_tcl_enabled) {
 366                 ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 367                 ctx->Const.VertexProgram.MaxNativeInstructions =
 368                   VSF_MAX_FRAGMENT_LENGTH / 4;
 369                 ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */
 370                 ctx->Const.VertexProgram.MaxTemps = 32;
 371                 ctx->Const.VertexProgram.MaxNativeTemps =
 372                   /*VSF_MAX_FRAGMENT_TEMPS */ 32;
 373                 ctx->Const.VertexProgram.MaxNativeParameters = 256;     /* r420 */
 374                 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 375         }
 376
 377         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 378                 ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
 379                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 380                 ctx->Const.FragmentProgram.MaxNativeParameters = R500_PFS_NUM_CONST_REGS;
 381                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R500_PFS_MAX_INST;
 382                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R500_PFS_MAX_INST;
 383                 ctx->Const.FragmentProgram.MaxNativeInstructions = R500_PFS_MAX_INST;
 384                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R500_PFS_MAX_INST;
 385                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 386         } else {
 387                 ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
 388                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 389                 ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
 390                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
 391                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
 392                 ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
 393                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
 394                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 395         }
 396
 397         if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530)
 398                 r300->num_z_pipes = 2;
 399         else
 400                 r300->num_z_pipes = r300->radeon.radeonScreen->num_gb_pipes;
 401 }
 402
 403 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
 404 {
 405         struct r300_options options = { 0 };
 406
 407         driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
 408                             screen->driScreen->myNum, "r300");
 409
 410         r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
 411
 412         options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
 413         options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
 414         options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
 415
 416         if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
 417                 options.hw_tcl_enabled = 0;
 418         else
 419                 options.hw_tcl_enabled = 1;
 420
 421         options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
 422
 423         r300->options = options;
 424 }
 425
 426 static void r300InitGLExtensions(GLcontext *ctx)
 427 {
 428         r300ContextPtr r300 = R300_CONTEXT(ctx);
 429
 430         driInitExtensions(ctx, card_extensions, GL_TRUE);
 431         if (r300->radeon.radeonScreen->kernel_mm)
 432                 driInitExtensions(ctx, mm_extensions, GL_FALSE);
 433
 434         if (r300->options.stencil_two_side_disabled)
 435                 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
 436
 437         if (ctx->Mesa_DXTn && !r300->options.s3tc_force_enabled) {
 438                 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 439                 _mesa_enable_extension(ctx, "GL_S3_s3tc");
 440         } else if (r300->options.s3tc_force_disabled) {
 441                 _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 442         }
 443
 444         if (!r300->radeon.radeonScreen->drmSupportsOcclusionQueries) {
 445                 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 446         }
 447 }
 448
 449 /* Create the device specific rendering context.
 450  */
 451 GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 452                             __DRIcontextPrivate * driContextPriv,
 453                             void *sharedContextPrivate)
 454 {
 455         __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 456         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 457         struct dd_function_table functions;
 458         r300ContextPtr r300;
 459         GLcontext *ctx;
 460
 461         assert(glVisual);
 462         assert(driContextPriv);
 463         assert(screen);
 464
 465         r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
 466         if (!r300)
 467                 return GL_FALSE;
 468
 469         r300ParseOptions(r300, screen);
 470
 471         r300->radeon.radeonScreen = screen;
 472         r300_init_vtbl(&r300->radeon);
 473
 474         _mesa_init_driver_functions(&functions);
 475         r300InitIoctlFuncs(&functions);
 476         r300InitStateFuncs(&functions);
 477         r300InitTextureFuncs(&functions);
 478         r300InitShaderFuncs(&functions);
 479         radeonInitQueryObjFunctions(&functions);
 480         radeonInitBufferObjectFuncs(&functions);
 481
 482         if (!radeonInitContext(&r300->radeon, &functions,
 483                                glVisual, driContextPriv,
 484                                sharedContextPrivate)) {
 485                 FREE(r300);
 486                 return GL_FALSE;
 487         }
 488
 489         ctx = r300->radeon.glCtx;
 490
 491         r300->fallback = 0;
 492         if (r300->options.hw_tcl_enabled)
 493                 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
 494
 495         ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 496
 497         r300InitConstValues(ctx, screen);
 498
 499         _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 500
 501         /* Initialize the software rasterizer and helper modules.
 502          */
 503         _swrast_CreateContext(ctx);
 504         _vbo_CreateContext(ctx);
 505         _tnl_CreateContext(ctx);
 506         _swsetup_CreateContext(ctx);
 507         _swsetup_Wakeup(ctx);
 508
 509         /* Install the customized pipeline:
 510          */
 511         _tnl_destroy_pipeline(ctx);
 512         _tnl_install_pipeline(ctx, r300_pipeline);
 513         TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 514
 515         /* Configure swrast and TNL to match hardware characteristics:
 516          */
 517         _swrast_allow_pixel_fog(ctx, GL_FALSE);
 518         _swrast_allow_vertex_fog(ctx, GL_TRUE);
 519         _tnl_allow_pixel_fog(ctx, GL_FALSE);
 520         _tnl_allow_vertex_fog(ctx, GL_TRUE);
 521
 522         if (r300->options.hw_tcl_enabled) {
 523                 r300InitDraw(ctx);
 524         } else {
 525                 r300InitSwtcl(ctx);
 526         }
 527
 528         radeon_fbo_init(&r300->radeon);
 529         radeonInitSpanFuncs( ctx );
 530         r300InitCmdBuf(r300);
 531         r300InitState(r300);
 532         r300InitShaderFunctions(r300);
 533
 534         r300InitGLExtensions(ctx);
 535
 536         return GL_TRUE;
 537 }
 538