src/mesa/drivers/dri/r300/r300_context.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  *
  35  * \author Nicolai Haehnle <prefect_@gmx.net>
  36  */
  37
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "main/imports.h"
  43 #include "main/matrix.h"
  44 #include "main/extensions.h"
  45 #include "main/state.h"
  46 #include "main/bufferobj.h"
  47 #include "main/texobj.h"
  48
  49 #include "swrast/swrast.h"
  50 #include "swrast_setup/swrast_setup.h"
  51 #include "vbo/vbo.h"
  52
  53 #include "tnl/tnl.h"
  54 #include "tnl/t_pipeline.h"
  55 #include "tnl/t_vp_build.h"
  56
  57 #include "drivers/common/driverfuncs.h"
  58
  59 #include "r300_context.h"
  60 #include "radeon_context.h"
  61 #include "radeon_span.h"
  62 #include "r300_cmdbuf.h"
  63 #include "r300_state.h"
  64 #include "r300_ioctl.h"
  65 #include "r300_tex.h"
  66 #include "r300_emit.h"
  67 #include "r300_swtcl.h"
  68 #include "radeon_bocs_wrapper.h"
  69 #include "radeon_buffer_objects.h"
  70 #include "radeon_queryobj.h"
  71
  72 #include "vblank.h"
  73 #include "utils.h"
  74 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  75
  76 #define need_GL_VERSION_2_0
  77 #define need_GL_ARB_occlusion_query
  78 #define need_GL_ARB_point_parameters
  79 #define need_GL_ARB_vertex_program
  80 #define need_GL_EXT_blend_equation_separate
  81 #define need_GL_EXT_blend_func_separate
  82 #define need_GL_EXT_blend_minmax
  83 #define need_GL_EXT_framebuffer_object
  84 #define need_GL_EXT_fog_coord
  85 #define need_GL_EXT_gpu_program_parameters
  86 #define need_GL_EXT_secondary_color
  87 #define need_GL_EXT_stencil_two_side
  88 #define need_GL_ATI_separate_stencil
  89 #define need_GL_NV_vertex_program
  90
  91 #include "extension_helper.h"
  92
  93
  94 const struct dri_extension card_extensions[] = {
  95   /* *INDENT-OFF* */
  96   {"GL_ARB_depth_texture",              NULL},
  97   {"GL_ARB_fragment_program",           NULL},
  98   {"GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  99   {"GL_ARB_multitexture",               NULL},
 100   {"GL_ARB_point_parameters",           GL_ARB_point_parameters_functions},
 101   {"GL_ARB_shadow",                     NULL},
 102   {"GL_ARB_shadow_ambient",             NULL},
 103   {"GL_ARB_texture_border_clamp",       NULL},
 104   {"GL_ARB_texture_cube_map",           NULL},
 105   {"GL_ARB_texture_env_add",            NULL},
 106   {"GL_ARB_texture_env_combine",        NULL},
 107   {"GL_ARB_texture_env_crossbar",       NULL},
 108   {"GL_ARB_texture_env_dot3",           NULL},
 109   {"GL_ARB_texture_mirrored_repeat",    NULL},
 110   {"GL_ARB_vertex_program",             GL_ARB_vertex_program_functions},
 111   {"GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions},
 112   {"GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions},
 113   {"GL_EXT_blend_minmax",               GL_EXT_blend_minmax_functions},
 114   {"GL_EXT_blend_subtract",             NULL},
 115   {"GL_EXT_packed_depth_stencil",       NULL},
 116   {"GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
 117   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
 118   {"GL_EXT_secondary_color",            GL_EXT_secondary_color_functions},
 119   {"GL_EXT_shadow_funcs",               NULL},
 120   {"GL_EXT_stencil_two_side",           GL_EXT_stencil_two_side_functions},
 121   {"GL_EXT_stencil_wrap",               NULL},
 122   {"GL_EXT_texture_edge_clamp",         NULL},
 123   {"GL_EXT_texture_env_combine",        NULL},
 124   {"GL_EXT_texture_env_dot3",           NULL},
 125   {"GL_EXT_texture_filter_anisotropic", NULL},
 126   {"GL_EXT_texture_lod_bias",           NULL},
 127   {"GL_EXT_texture_mirror_clamp",       NULL},
 128   {"GL_EXT_texture_rectangle",          NULL},
 129   {"GL_EXT_texture_sRGB",               NULL},
 130   {"GL_EXT_vertex_array_bgra",          NULL},
 131   {"GL_ATI_separate_stencil",           GL_ATI_separate_stencil_functions},
 132   {"GL_ATI_texture_env_combine3",       NULL},
 133   {"GL_ATI_texture_mirror_once",        NULL},
 134   {"GL_MESA_pack_invert",               NULL},
 135   {"GL_MESA_ycbcr_texture",             NULL},
 136   {"GL_MESAX_texture_float",            NULL},
 137   {"GL_NV_blend_square",                NULL},
 138   {"GL_NV_vertex_program",              GL_NV_vertex_program_functions},
 139   {"GL_SGIS_generate_mipmap",           NULL},
 140   {NULL,                                NULL}
 141   /* *INDENT-ON* */
 142 };
 143
 144
 145 const struct dri_extension mm_extensions[] = {
 146   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 147   { NULL, NULL }
 148 };
 149
 150 /**
 151  * The GL 2.0 functions are needed to make display lists work with
 152  * functions added by GL_ATI_separate_stencil.
 153  */
 154 const struct dri_extension gl_20_extension[] = {
 155   {"GL_VERSION_2_0",                    GL_VERSION_2_0_functions },
 156 };
 157
 158 static const struct tnl_pipeline_stage *r300_pipeline[] = {
 159         /* Catch any t&l fallbacks
 160          */
 161         &_tnl_vertex_transform_stage,
 162         &_tnl_normal_transform_stage,
 163         &_tnl_lighting_stage,
 164         &_tnl_fog_coordinate_stage,
 165         &_tnl_texgen_stage,
 166         &_tnl_texture_transform_stage,
 167         &_tnl_point_attenuation_stage,
 168         &_tnl_vertex_program_stage,
 169         &_tnl_render_stage,
 170         0,
 171 };
 172
 173 static void r300_get_lock(radeonContextPtr rmesa)
 174 {
 175         drm_radeon_sarea_t *sarea = rmesa->sarea;
 176
 177         if (sarea->ctx_owner != rmesa->dri.hwContext) {
 178                 sarea->ctx_owner = rmesa->dri.hwContext;
 179                 if (!rmesa->radeonScreen->kernel_mm)
 180                         radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
 181         }
 182 }
 183
 184 static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 185 {
 186     /* please flush pipe do all pending work */
 187     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 188                                   R300_SC_SCREENDOOR, 1));
 189     radeon_cs_write_dword(cs, 0x0);
 190     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 191                                   R300_SC_SCREENDOOR, 1));
 192     radeon_cs_write_dword(cs, 0x00FFFFFF);
 193     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 194                                   R300_SC_HYPERZ, 1));
 195     radeon_cs_write_dword(cs, 0x0);
 196     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 197                                   R300_US_CONFIG, 1));
 198     radeon_cs_write_dword(cs, 0x0);
 199     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 200                                   R300_ZB_CNTL, 1));
 201     radeon_cs_write_dword(cs, 0x0);
 202     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
 203     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 204                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 205     radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 206     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 207                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 208     radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 209     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
 210                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 211 }
 212
 213 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 214 {
 215         r300ContextPtr r300 = (r300ContextPtr)radeon;
 216         BATCH_LOCALS(radeon);
 217
 218         r300->vap_flush_needed = GL_TRUE;
 219
 220         cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 221         BEGIN_BATCH_NO_AUTOSTATE(2);
 222         OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
 223         END_BATCH();
 224         end_3d(radeon);
 225 }
 226
 227 static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
 228 {
 229         r300ContextPtr r300 = R300_CONTEXT(ctx);
 230         if (mode)
 231                 r300->radeon.Fallback |= bit;
 232         else
 233                 r300->radeon.Fallback &= ~bit;
 234 }
 235
 236 static void r300_emit_query_finish(radeonContextPtr radeon)
 237 {
 238         r300ContextPtr r300 = (r300ContextPtr)radeon;
 239         struct radeon_query_object *query = radeon->query.current;
 240         BATCH_LOCALS(radeon);
 241
 242         BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->num_z_pipes + 2);
 243         switch (r300->num_z_pipes) {
 244         case 4:
 245                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 246                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 247                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 248         case 3:
 249                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
 250                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 251                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 252         case 2:
 253                 if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
 254                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 255                 } else {
 256                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
 257                 }
 258                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 259                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 260         case 1:
 261         default:
 262                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
 263                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 264                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 265                 break;
 266         }
 267         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 268         END_BATCH();
 269         query->curr_offset += r300->num_z_pipes * sizeof(uint32_t);
 270         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 271         query->emitted_begin = GL_FALSE;
 272 }
 273
 274 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
 275 {
 276         BATCH_LOCALS(radeon);
 277         struct radeon_query_object *query = radeon->query.current;
 278
 279         BEGIN_BATCH_NO_AUTOSTATE(8);
 280         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 281         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 282         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 283         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 284         END_BATCH();
 285
 286         query->curr_offset += sizeof(uint32_t);
 287         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 288         query->emitted_begin = GL_FALSE;
 289 }
 290
 291 #if 0
 292 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 293 {
 294         r300ContextPtr r300 = (r300ContextPtr)radeon;
 295         BATCH_LOCALS(radeon);
 296         struct radeon_query_object *query = radeon->query.current;
 297
 298         BEGIN_BATCH_NO_AUTOSTATE(6);
 299         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 300         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 301         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 302         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 303         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 304         OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 305         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 306         END_BATCH();
 307
 308         query->curr_offset += 2 * sizeof(uint32_t);
 309         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 310         query->emitted_begin = GL_FALSE;
 311 }
 312 #endif
 313
 314 static void r300_init_vtbl(radeonContextPtr radeon)
 315 {
 316         radeon->vtbl.get_lock = r300_get_lock;
 317         radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
 318         radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
 319         radeon->vtbl.swtcl_flush = r300_swtcl_flush;
 320         radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
 321         radeon->vtbl.fallback = r300_fallback;
 322         if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530)
 323                 /* single Z gives me correct results on my hw need to check if we ever need
 324                  * double z */
 325                 radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
 326         else
 327                 radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 328 }
 329
 330 static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
 331 {
 332         r300ContextPtr r300 = R300_CONTEXT(ctx);
 333
 334         ctx->Const.MaxTextureImageUnits =
 335             driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
 336         ctx->Const.MaxTextureCoordUnits =
 337             driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
 338         ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
 339                  ctx->Const.MaxTextureCoordUnits);
 340
 341         ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 342         ctx->Const.MaxTextureLodBias = 16.0;
 343
 344         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 345                 ctx->Const.MaxTextureLevels = 13;
 346                 ctx->Const.MaxCubeTextureLevels = 13;
 347                 ctx->Const.MaxTextureRectSize = 4096;
 348         }
 349         else {
 350                 ctx->Const.MaxTextureLevels = 12;
 351                 ctx->Const.MaxCubeTextureLevels = 12;
 352                 ctx->Const.MaxTextureRectSize = 2048;
 353         }
 354
 355         ctx->Const.MinPointSize = 1.0;
 356         ctx->Const.MinPointSizeAA = 1.0;
 357         ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
 358         ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
 359
 360         ctx->Const.MinLineWidth = 1.0;
 361         ctx->Const.MinLineWidthAA = 1.0;
 362         ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
 363         ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
 364
 365         ctx->Const.MaxDrawBuffers = 1;
 366
 367         /* currently bogus data */
 368         if (r300->options.hw_tcl_enabled) {
 369                 ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 370                 ctx->Const.VertexProgram.MaxNativeInstructions =
 371                   VSF_MAX_FRAGMENT_LENGTH / 4;
 372                 ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */
 373                 ctx->Const.VertexProgram.MaxTemps = 32;
 374                 ctx->Const.VertexProgram.MaxNativeTemps =
 375                   /*VSF_MAX_FRAGMENT_TEMPS */ 32;
 376                 ctx->Const.VertexProgram.MaxNativeParameters = 256;     /* r420 */
 377                 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 378         }
 379
 380         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 381                 ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
 382                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 383                 ctx->Const.FragmentProgram.MaxNativeParameters = R500_PFS_NUM_CONST_REGS;
 384                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R500_PFS_MAX_INST;
 385                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R500_PFS_MAX_INST;
 386                 ctx->Const.FragmentProgram.MaxNativeInstructions = R500_PFS_MAX_INST;
 387                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R500_PFS_MAX_INST;
 388                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 389         } else {
 390                 ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
 391                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 392                 ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
 393                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
 394                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
 395                 ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
 396                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
 397                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 398         }
 399
 400         if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530)
 401                 r300->num_z_pipes = 2;
 402         else
 403                 r300->num_z_pipes = r300->radeon.radeonScreen->num_gb_pipes;
 404 }
 405
 406 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
 407 {
 408         struct r300_options options = { 0 };
 409
 410         driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
 411                             screen->driScreen->myNum, "r300");
 412
 413         r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
 414
 415         options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
 416         options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
 417         options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
 418
 419         if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
 420                 options.hw_tcl_enabled = 0;
 421         else
 422                 options.hw_tcl_enabled = 1;
 423
 424         options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
 425
 426         r300->options = options;
 427 }
 428
 429 static void r300InitGLExtensions(GLcontext *ctx)
 430 {
 431         r300ContextPtr r300 = R300_CONTEXT(ctx);
 432
 433         driInitExtensions(ctx, card_extensions, GL_TRUE);
 434         if (r300->radeon.radeonScreen->kernel_mm)
 435                 driInitExtensions(ctx, mm_extensions, GL_FALSE);
 436
 437         if (r300->options.stencil_two_side_disabled)
 438                 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
 439
 440         if (ctx->Mesa_DXTn && !r300->options.s3tc_force_enabled) {
 441                 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 442                 _mesa_enable_extension(ctx, "GL_S3_s3tc");
 443         } else if (r300->options.s3tc_force_disabled) {
 444                 _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 445         }
 446
 447         if (!r300->radeon.radeonScreen->drmSupportsOcclusionQueries) {
 448                 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 449         }
 450 }
 451
 452 /* Create the device specific rendering context.
 453  */
 454 GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 455                             __DRIcontextPrivate * driContextPriv,
 456                             void *sharedContextPrivate)
 457 {
 458         __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 459         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 460         struct dd_function_table functions;
 461         r300ContextPtr r300;
 462         GLcontext *ctx;
 463
 464         assert(glVisual);
 465         assert(driContextPriv);
 466         assert(screen);
 467
 468         r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
 469         if (!r300)
 470                 return GL_FALSE;
 471
 472         r300ParseOptions(r300, screen);
 473
 474         r300->radeon.radeonScreen = screen;
 475         r300_init_vtbl(&r300->radeon);
 476
 477         _mesa_init_driver_functions(&functions);
 478         r300InitIoctlFuncs(&functions);
 479         r300InitStateFuncs(&functions);
 480         r300InitTextureFuncs(&functions);
 481         r300InitShaderFuncs(&functions);
 482         radeonInitQueryObjFunctions(&functions);
 483         radeonInitBufferObjectFuncs(&functions);
 484
 485         if (!radeonInitContext(&r300->radeon, &functions,
 486                                glVisual, driContextPriv,
 487                                sharedContextPrivate)) {
 488                 FREE(r300);
 489                 return GL_FALSE;
 490         }
 491
 492         ctx = r300->radeon.glCtx;
 493
 494         r300->fallback = 0;
 495         if (r300->options.hw_tcl_enabled)
 496                 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
 497
 498         ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 499
 500         r300InitConstValues(ctx, screen);
 501
 502         _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 503
 504         /* Initialize the software rasterizer and helper modules.
 505          */
 506         _swrast_CreateContext(ctx);
 507         _vbo_CreateContext(ctx);
 508         _tnl_CreateContext(ctx);
 509         _swsetup_CreateContext(ctx);
 510         _swsetup_Wakeup(ctx);
 511
 512         /* Install the customized pipeline:
 513          */
 514         _tnl_destroy_pipeline(ctx);
 515         _tnl_install_pipeline(ctx, r300_pipeline);
 516         TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 517
 518         /* Configure swrast and TNL to match hardware characteristics:
 519          */
 520         _swrast_allow_pixel_fog(ctx, GL_FALSE);
 521         _swrast_allow_vertex_fog(ctx, GL_TRUE);
 522         _tnl_allow_pixel_fog(ctx, GL_FALSE);
 523         _tnl_allow_vertex_fog(ctx, GL_TRUE);
 524
 525         if (r300->options.hw_tcl_enabled) {
 526                 r300InitDraw(ctx);
 527         } else {
 528                 r300InitSwtcl(ctx);
 529         }
 530
 531         radeon_fbo_init(&r300->radeon);
 532         radeonInitSpanFuncs( ctx );
 533         r300InitCmdBuf(r300);
 534         r300InitState(r300);
 535         r300InitShaderFunctions(r300);
 536
 537         r300InitGLExtensions(ctx);
 538
 539         return GL_TRUE;
 540 }
 541