src/mesa/drivers/dri/r300/r300_context.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  *
  35  * \author Nicolai Haehnle <prefect_@gmx.net>
  36  */
  37
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "main/imports.h"
  43 #include "main/extensions.h"
  44 #include "main/bufferobj.h"
  45 #include "main/texobj.h"
  46
  47 #include "swrast/swrast.h"
  48 #include "swrast_setup/swrast_setup.h"
  49 #include "vbo/vbo.h"
  50
  51 #include "tnl/tnl.h"
  52 #include "tnl/t_pipeline.h"
  53
  54 #include "drivers/common/driverfuncs.h"
  55 #include "drivers/common/meta.h"
  56
  57 #include "r300_context.h"
  58 #include "radeon_span.h"
  59 #include "r300_blit.h"
  60 #include "r300_cmdbuf.h"
  61 #include "r300_state.h"
  62 #include "r300_tex.h"
  63 #include "r300_emit.h"
  64 #include "r300_swtcl.h"
  65 #include "radeon_bocs_wrapper.h"
  66 #include "radeon_buffer_objects.h"
  67 #include "radeon_queryobj.h"
  68
  69 #include "utils.h"
  70 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  71
  72 #define need_GL_VERSION_2_0
  73 #define need_GL_ARB_occlusion_query
  74 #define need_GL_ARB_point_parameters
  75 #define need_GL_ARB_vertex_program
  76 #define need_GL_EXT_blend_equation_separate
  77 #define need_GL_EXT_blend_func_separate
  78 #define need_GL_EXT_blend_minmax
  79 #define need_GL_EXT_framebuffer_blit
  80 #define need_GL_EXT_framebuffer_object
  81 #define need_GL_EXT_fog_coord
  82 #define need_GL_EXT_gpu_program_parameters
  83 #define need_GL_EXT_provoking_vertex
  84 #define need_GL_EXT_secondary_color
  85 #define need_GL_EXT_stencil_two_side
  86 #define need_GL_ATI_separate_stencil
  87 #define need_GL_NV_vertex_program
  88
  89 #include "main/remap_helper.h"
  90
  91 static const struct dri_extension card_extensions[] = {
  92   /* *INDENT-OFF* */
  93   {"GL_ARB_depth_texture",              NULL},
  94   {"GL_ARB_fragment_program",           NULL},
  95   {"GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  96   {"GL_ARB_multitexture",               NULL},
  97   {"GL_ARB_point_parameters",           GL_ARB_point_parameters_functions},
  98   {"GL_ARB_shadow",                     NULL},
  99   {"GL_ARB_shadow_ambient",             NULL},
 100   {"GL_ARB_texture_border_clamp",       NULL},
 101   {"GL_ARB_texture_cube_map",           NULL},
 102   {"GL_ARB_texture_env_add",            NULL},
 103   {"GL_ARB_texture_env_combine",        NULL},
 104   {"GL_ARB_texture_env_crossbar",       NULL},
 105   {"GL_ARB_texture_env_dot3",           NULL},
 106   {"GL_ARB_texture_mirrored_repeat",    NULL},
 107   {"GL_ARB_vertex_program",             GL_ARB_vertex_program_functions},
 108   {"GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions},
 109   {"GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions},
 110   {"GL_EXT_blend_minmax",               GL_EXT_blend_minmax_functions},
 111   {"GL_EXT_blend_subtract",             NULL},
 112   {"GL_EXT_packed_depth_stencil",       NULL},
 113   {"GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
 114   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
 115   {"GL_EXT_provoking_vertex",           GL_EXT_provoking_vertex_functions },
 116   {"GL_EXT_secondary_color",            GL_EXT_secondary_color_functions},
 117   {"GL_EXT_shadow_funcs",               NULL},
 118   {"GL_EXT_stencil_two_side",           GL_EXT_stencil_two_side_functions},
 119   {"GL_EXT_stencil_wrap",               NULL},
 120   {"GL_EXT_texture_edge_clamp",         NULL},
 121   {"GL_EXT_texture_env_combine",        NULL},
 122   {"GL_EXT_texture_env_dot3",           NULL},
 123   {"GL_EXT_texture_filter_anisotropic", NULL},
 124   {"GL_EXT_texture_lod_bias",           NULL},
 125   {"GL_EXT_texture_mirror_clamp",       NULL},
 126   {"GL_EXT_texture_rectangle",          NULL},
 127   {"GL_EXT_texture_sRGB",               NULL},
 128   {"GL_EXT_vertex_array_bgra",          NULL},
 129   {"GL_ATI_separate_stencil",           GL_ATI_separate_stencil_functions},
 130   {"GL_ATI_texture_env_combine3",       NULL},
 131   {"GL_ATI_texture_mirror_once",        NULL},
 132   {"GL_MESA_pack_invert",               NULL},
 133   {"GL_MESA_ycbcr_texture",             NULL},
 134   {"GL_MESAX_texture_float",            NULL},
 135   {"GL_NV_blend_square",                NULL},
 136   {"GL_NV_vertex_program",              GL_NV_vertex_program_functions},
 137   {"GL_SGIS_generate_mipmap",           NULL},
 138   {NULL,                                NULL}
 139   /* *INDENT-ON* */
 140 };
 141
 142
 143 static const struct dri_extension mm_extensions[] = {
 144   { "GL_EXT_framebuffer_blit",  GL_EXT_framebuffer_blit_functions },
 145   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 146   { NULL, NULL }
 147 };
 148
 149 /**
 150  * The GL 2.0 functions are needed to make display lists work with
 151  * functions added by GL_ATI_separate_stencil.
 152  */
 153 static const struct dri_extension gl_20_extension[] = {
 154   {"GL_VERSION_2_0",                    GL_VERSION_2_0_functions },
 155 };
 156
 157 static const struct tnl_pipeline_stage *r300_pipeline[] = {
 158         /* Catch any t&l fallbacks
 159          */
 160         &_tnl_vertex_transform_stage,
 161         &_tnl_normal_transform_stage,
 162         &_tnl_lighting_stage,
 163         &_tnl_fog_coordinate_stage,
 164         &_tnl_texgen_stage,
 165         &_tnl_texture_transform_stage,
 166         &_tnl_point_attenuation_stage,
 167         &_tnl_vertex_program_stage,
 168         &_tnl_render_stage,
 169         0,
 170 };
 171
 172 static void r300_get_lock(radeonContextPtr rmesa)
 173 {
 174         drm_radeon_sarea_t *sarea = rmesa->sarea;
 175
 176         if (sarea->ctx_owner != rmesa->dri.hwContext) {
 177                 sarea->ctx_owner = rmesa->dri.hwContext;
 178                 if (!rmesa->radeonScreen->kernel_mm)
 179                         radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
 180         }
 181 }
 182
 183 static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 184 {
 185     /* please flush pipe do all pending work */
 186     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 187                                   R300_SC_SCREENDOOR, 1));
 188     radeon_cs_write_dword(cs, 0x0);
 189     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 190                                   R300_SC_SCREENDOOR, 1));
 191     radeon_cs_write_dword(cs, 0x00FFFFFF);
 192     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 193                                   R300_SC_HYPERZ, 1));
 194     radeon_cs_write_dword(cs, 0x0);
 195     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 196                                   R300_US_CONFIG, 1));
 197     radeon_cs_write_dword(cs, 0x0);
 198     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 199                                   R300_ZB_CNTL, 1));
 200     radeon_cs_write_dword(cs, 0x0);
 201     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
 202     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 203                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 204     radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 205     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 206                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 207     radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 208     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
 209                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 210 }
 211
 212 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 213 {
 214         BATCH_LOCALS(radeon);
 215
 216         cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 217         BEGIN_BATCH_NO_AUTOSTATE(2);
 218         OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
 219         END_BATCH();
 220         end_3d(radeon);
 221 }
 222
 223 static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
 224 {
 225         r300ContextPtr r300 = R300_CONTEXT(ctx);
 226         if (mode)
 227                 r300->radeon.Fallback |= bit;
 228         else
 229                 r300->radeon.Fallback &= ~bit;
 230 }
 231
 232 static void r300_emit_query_finish(radeonContextPtr radeon)
 233 {
 234         r300ContextPtr r300 = (r300ContextPtr)radeon;
 235         struct radeon_query_object *query = radeon->query.current;
 236         BATCH_LOCALS(radeon);
 237
 238         BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2);
 239         switch (r300->radeon.radeonScreen->num_gb_pipes) {
 240         case 4:
 241                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 242                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 243                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 244         case 3:
 245                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
 246                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 247                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 248         case 2:
 249                 if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
 250                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 251                 } else {
 252                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
 253                 }
 254                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 255                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 256         case 1:
 257         default:
 258                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
 259                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 260                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 261                 break;
 262         }
 263         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 264         END_BATCH();
 265         query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t);
 266         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 267         query->emitted_begin = GL_FALSE;
 268 }
 269
 270 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
 271 {
 272         BATCH_LOCALS(radeon);
 273         struct radeon_query_object *query = radeon->query.current;
 274
 275         BEGIN_BATCH_NO_AUTOSTATE(8);
 276         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 277         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 278         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 279         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 280         END_BATCH();
 281
 282         query->curr_offset += sizeof(uint32_t);
 283         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 284         query->emitted_begin = GL_FALSE;
 285 }
 286
 287 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 288 {
 289         BATCH_LOCALS(radeon);
 290         struct radeon_query_object *query = radeon->query.current;
 291
 292         BEGIN_BATCH_NO_AUTOSTATE(14);
 293         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 294         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 295         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 296         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 297         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 298         OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 299         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 300         END_BATCH();
 301
 302         query->curr_offset += 2 * sizeof(uint32_t);
 303         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 304         query->emitted_begin = GL_FALSE;
 305 }
 306
 307 static void r300_init_vtbl(radeonContextPtr radeon)
 308 {
 309         radeon->vtbl.get_lock = r300_get_lock;
 310         radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
 311         radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
 312         radeon->vtbl.swtcl_flush = r300_swtcl_flush;
 313         radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
 314         radeon->vtbl.fallback = r300_fallback;
 315         if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 316                 if (radeon->radeonScreen->num_z_pipes == 2)
 317                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z;
 318                 else
 319                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
 320         } else
 321                 radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 322
 323         radeon->vtbl.check_blit = r300_check_blit;
 324         radeon->vtbl.blit = r300_blit;
 325 }
 326
 327 static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
 328 {
 329         r300ContextPtr r300 = R300_CONTEXT(ctx);
 330
 331         ctx->Const.MaxTextureImageUnits =
 332             driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
 333         ctx->Const.MaxTextureCoordUnits =
 334             driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
 335         ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
 336                  ctx->Const.MaxTextureCoordUnits);
 337         ctx->Const.MaxCombinedTextureImageUnits =
 338                 ctx->Const.MaxVertexTextureImageUnits +
 339                 ctx->Const.MaxTextureImageUnits;
 340
 341
 342         ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 343         ctx->Const.MaxTextureLodBias = 16.0;
 344
 345         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 346                 ctx->Const.MaxTextureLevels = 13;
 347                 ctx->Const.MaxCubeTextureLevels = 13;
 348                 ctx->Const.MaxTextureRectSize = 4096;
 349                 ctx->Const.MaxRenderbufferSize = 4096;
 350         }
 351         else {
 352                 ctx->Const.MaxTextureLevels = 12;
 353                 ctx->Const.MaxCubeTextureLevels = 12;
 354                 ctx->Const.MaxTextureRectSize = 2048;
 355                 ctx->Const.MaxRenderbufferSize = 2048;
 356         }
 357
 358         ctx->Const.MinPointSize = 1.0;
 359         ctx->Const.MinPointSizeAA = 1.0;
 360         ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
 361         ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
 362
 363         ctx->Const.MinLineWidth = 1.0;
 364         ctx->Const.MinLineWidthAA = 1.0;
 365         ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
 366         ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
 367
 368         ctx->Const.MaxDrawBuffers = 1;
 369         ctx->Const.MaxColorAttachments = 1;
 370
 371         /* currently bogus data */
 372         if (r300->options.hw_tcl_enabled) {
 373                 ctx->Const.VertexProgram.MaxNativeInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 374                 ctx->Const.VertexProgram.MaxNativeAluInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 375                 ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */
 376                 ctx->Const.VertexProgram.MaxNativeTemps = 32;
 377                 ctx->Const.VertexProgram.MaxNativeParameters = 256;     /* r420 */
 378                 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 379         }
 380
 381         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 382                 ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
 383                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 384
 385                 /* The hardware limits are higher than this,
 386                  * but the non-KMS DRM interface artificially limits us
 387                  * to this many instructions.
 388                  *
 389                  * We could of course work around it in the KMS path,
 390                  * but it would be a mess, so it seems wiser
 391                  * to leave it as is. Going forward, the Gallium driver
 392                  * will not be subject to these limitations.
 393                  */
 394                 ctx->Const.FragmentProgram.MaxNativeParameters = 255;
 395                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = 255;
 396                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = 255;
 397                 ctx->Const.FragmentProgram.MaxNativeInstructions = 255;
 398                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = 255;
 399                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 400         } else {
 401                 ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
 402                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 403                 ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
 404                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
 405                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
 406                 ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
 407                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
 408                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 409         }
 410
 411 }
 412
 413 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
 414 {
 415         struct r300_options options = { 0 };
 416
 417         driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
 418                             screen->driScreen->myNum, "r300");
 419
 420         r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
 421
 422         options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
 423         options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
 424         options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
 425
 426         if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
 427                 options.hw_tcl_enabled = 0;
 428         else
 429                 options.hw_tcl_enabled = 1;
 430
 431         options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
 432
 433         r300->options = options;
 434 }
 435
 436 static void r300InitGLExtensions(GLcontext *ctx)
 437 {
 438         r300ContextPtr r300 = R300_CONTEXT(ctx);
 439
 440         driInitExtensions(ctx, card_extensions, GL_TRUE);
 441         if (r300->radeon.radeonScreen->kernel_mm)
 442                 driInitExtensions(ctx, mm_extensions, GL_FALSE);
 443
 444         if (r300->options.stencil_two_side_disabled)
 445                 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
 446
 447         if (r300->options.s3tc_force_disabled) {
 448                 _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 449         } else if (ctx->Mesa_DXTn || r300->options.s3tc_force_enabled) {
 450                 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 451                 _mesa_enable_extension(ctx, "GL_S3_s3tc");
 452         }
 453
 454         if (!r300->radeon.radeonScreen->drmSupportsOcclusionQueries) {
 455                 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 456         }
 457         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350)
 458                 _mesa_enable_extension(ctx, "GL_ARB_half_float_vertex");
 459 }
 460
 461 static void r300InitIoctlFuncs(struct dd_function_table *functions)
 462 {
 463         functions->Clear = _mesa_meta_Clear;
 464         functions->Finish = radeonFinish;
 465         functions->Flush = radeonFlush;
 466 }
 467
 468 /* Create the device specific rendering context.
 469  */
 470 GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 471                             __DRIcontext * driContextPriv,
 472                             void *sharedContextPrivate)
 473 {
 474         __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 475         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 476         struct dd_function_table functions;
 477         r300ContextPtr r300;
 478         GLcontext *ctx;
 479
 480         assert(glVisual);
 481         assert(driContextPriv);
 482         assert(screen);
 483
 484         r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
 485         if (!r300)
 486                 return GL_FALSE;
 487
 488         r300ParseOptions(r300, screen);
 489
 490         r300->radeon.radeonScreen = screen;
 491         r300_init_vtbl(&r300->radeon);
 492
 493         _mesa_init_driver_functions(&functions);
 494         r300InitIoctlFuncs(&functions);
 495         r300InitStateFuncs(&functions);
 496         r300InitTextureFuncs(&r300->radeon, &functions);
 497         r300InitShaderFuncs(&functions);
 498         radeonInitQueryObjFunctions(&functions);
 499         radeonInitBufferObjectFuncs(&functions);
 500
 501         if (!radeonInitContext(&r300->radeon, &functions,
 502                                glVisual, driContextPriv,
 503                                sharedContextPrivate)) {
 504                 FREE(r300);
 505                 return GL_FALSE;
 506         }
 507
 508         ctx = r300->radeon.glCtx;
 509
 510         r300->fallback = 0;
 511         if (r300->options.hw_tcl_enabled)
 512                 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
 513
 514         ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 515
 516         r300InitConstValues(ctx, screen);
 517
 518         _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 519
 520         /* Initialize the software rasterizer and helper modules.
 521          */
 522         _swrast_CreateContext(ctx);
 523         _vbo_CreateContext(ctx);
 524         _tnl_CreateContext(ctx);
 525         _swsetup_CreateContext(ctx);
 526         _swsetup_Wakeup(ctx);
 527
 528         /* Install the customized pipeline:
 529          */
 530         _tnl_destroy_pipeline(ctx);
 531         _tnl_install_pipeline(ctx, r300_pipeline);
 532         TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 533
 534         /* Configure swrast and TNL to match hardware characteristics:
 535          */
 536         _swrast_allow_pixel_fog(ctx, GL_FALSE);
 537         _swrast_allow_vertex_fog(ctx, GL_TRUE);
 538         _tnl_allow_pixel_fog(ctx, GL_FALSE);
 539         _tnl_allow_vertex_fog(ctx, GL_TRUE);
 540
 541         if (r300->options.hw_tcl_enabled) {
 542                 r300InitDraw(ctx);
 543         } else {
 544                 r300InitSwtcl(ctx);
 545         }
 546
 547         r300_blit_init(r300);
 548         radeon_fbo_init(&r300->radeon);
 549         radeonInitSpanFuncs( ctx );
 550         r300InitCmdBuf(r300);
 551         r300InitState(r300);
 552         r300InitShaderFunctions(r300);
 553
 554         r300InitGLExtensions(ctx);
 555
 556         return GL_TRUE;
 557 }
 558