src/mesa/drivers/dri/r300/r300_context.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  *
  35  * \author Nicolai Haehnle <prefect_@gmx.net>
  36  */
  37
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "main/imports.h"
  43 #include "main/matrix.h"
  44 #include "main/extensions.h"
  45 #include "main/state.h"
  46 #include "main/bufferobj.h"
  47 #include "main/texobj.h"
  48
  49 #include "swrast/swrast.h"
  50 #include "swrast_setup/swrast_setup.h"
  51 #include "vbo/vbo.h"
  52
  53 #include "tnl/tnl.h"
  54 #include "tnl/t_pipeline.h"
  55 #include "tnl/t_vp_build.h"
  56
  57 #include "drivers/common/driverfuncs.h"
  58 #include "drivers/common/meta.h"
  59
  60 #include "r300_context.h"
  61 #include "radeon_context.h"
  62 #include "radeon_span.h"
  63 #include "r300_blit.h"
  64 #include "r300_cmdbuf.h"
  65 #include "r300_state.h"
  66 #include "r300_tex.h"
  67 #include "r300_emit.h"
  68 #include "r300_swtcl.h"
  69 #include "radeon_bocs_wrapper.h"
  70 #include "radeon_buffer_objects.h"
  71 #include "radeon_queryobj.h"
  72
  73 #include "vblank.h"
  74 #include "utils.h"
  75 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  76
  77 #define need_GL_VERSION_2_0
  78 #define need_GL_ARB_occlusion_query
  79 #define need_GL_ARB_point_parameters
  80 #define need_GL_ARB_vertex_program
  81 #define need_GL_EXT_blend_equation_separate
  82 #define need_GL_EXT_blend_func_separate
  83 #define need_GL_EXT_blend_minmax
  84 #define need_GL_EXT_framebuffer_blit
  85 #define need_GL_EXT_framebuffer_object
  86 #define need_GL_EXT_fog_coord
  87 #define need_GL_EXT_gpu_program_parameters
  88 #define need_GL_EXT_provoking_vertex
  89 #define need_GL_EXT_secondary_color
  90 #define need_GL_EXT_stencil_two_side
  91 #define need_GL_ATI_separate_stencil
  92 #define need_GL_NV_vertex_program
  93
  94 #include "main/remap_helper.h"
  95
  96 void r300_init_texcopy_functions(struct dd_function_table *table);
  97
  98 static const struct dri_extension card_extensions[] = {
  99   /* *INDENT-OFF* */
 100   {"GL_ARB_depth_texture",              NULL},
 101   {"GL_ARB_fragment_program",           NULL},
 102   {"GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
 103   {"GL_ARB_multitexture",               NULL},
 104   {"GL_ARB_point_parameters",           GL_ARB_point_parameters_functions},
 105   {"GL_ARB_shadow",                     NULL},
 106   {"GL_ARB_shadow_ambient",             NULL},
 107   {"GL_ARB_texture_border_clamp",       NULL},
 108   {"GL_ARB_texture_cube_map",           NULL},
 109   {"GL_ARB_texture_env_add",            NULL},
 110   {"GL_ARB_texture_env_combine",        NULL},
 111   {"GL_ARB_texture_env_crossbar",       NULL},
 112   {"GL_ARB_texture_env_dot3",           NULL},
 113   {"GL_ARB_texture_mirrored_repeat",    NULL},
 114   {"GL_ARB_vertex_program",             GL_ARB_vertex_program_functions},
 115   {"GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions},
 116   {"GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions},
 117   {"GL_EXT_blend_minmax",               GL_EXT_blend_minmax_functions},
 118   {"GL_EXT_blend_subtract",             NULL},
 119   {"GL_EXT_packed_depth_stencil",       NULL},
 120   {"GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
 121   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
 122   {"GL_EXT_provoking_vertex",           GL_EXT_provoking_vertex_functions },
 123   {"GL_EXT_secondary_color",            GL_EXT_secondary_color_functions},
 124   {"GL_EXT_shadow_funcs",               NULL},
 125   {"GL_EXT_stencil_two_side",           GL_EXT_stencil_two_side_functions},
 126   {"GL_EXT_stencil_wrap",               NULL},
 127   {"GL_EXT_texture_edge_clamp",         NULL},
 128   {"GL_EXT_texture_env_combine",        NULL},
 129   {"GL_EXT_texture_env_dot3",           NULL},
 130   {"GL_EXT_texture_filter_anisotropic", NULL},
 131   {"GL_EXT_texture_lod_bias",           NULL},
 132   {"GL_EXT_texture_mirror_clamp",       NULL},
 133   {"GL_EXT_texture_rectangle",          NULL},
 134   {"GL_EXT_texture_sRGB",               NULL},
 135   {"GL_EXT_vertex_array_bgra",          NULL},
 136   {"GL_ATI_separate_stencil",           GL_ATI_separate_stencil_functions},
 137   {"GL_ATI_texture_env_combine3",       NULL},
 138   {"GL_ATI_texture_mirror_once",        NULL},
 139   {"GL_MESA_pack_invert",               NULL},
 140   {"GL_MESA_ycbcr_texture",             NULL},
 141   {"GL_MESAX_texture_float",            NULL},
 142   {"GL_NV_blend_square",                NULL},
 143   {"GL_NV_vertex_program",              GL_NV_vertex_program_functions},
 144   {"GL_SGIS_generate_mipmap",           NULL},
 145   {NULL,                                NULL}
 146   /* *INDENT-ON* */
 147 };
 148
 149
 150 static const struct dri_extension mm_extensions[] = {
 151   { "GL_EXT_framebuffer_blit",  GL_EXT_framebuffer_blit_functions },
 152   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 153   { NULL, NULL }
 154 };
 155
 156 /**
 157  * The GL 2.0 functions are needed to make display lists work with
 158  * functions added by GL_ATI_separate_stencil.
 159  */
 160 static const struct dri_extension gl_20_extension[] = {
 161   {"GL_VERSION_2_0",                    GL_VERSION_2_0_functions },
 162 };
 163
 164 static const struct tnl_pipeline_stage *r300_pipeline[] = {
 165         /* Catch any t&l fallbacks
 166          */
 167         &_tnl_vertex_transform_stage,
 168         &_tnl_normal_transform_stage,
 169         &_tnl_lighting_stage,
 170         &_tnl_fog_coordinate_stage,
 171         &_tnl_texgen_stage,
 172         &_tnl_texture_transform_stage,
 173         &_tnl_point_attenuation_stage,
 174         &_tnl_vertex_program_stage,
 175         &_tnl_render_stage,
 176         0,
 177 };
 178
 179 static void r300_get_lock(radeonContextPtr rmesa)
 180 {
 181         drm_radeon_sarea_t *sarea = rmesa->sarea;
 182
 183         if (sarea->ctx_owner != rmesa->dri.hwContext) {
 184                 sarea->ctx_owner = rmesa->dri.hwContext;
 185                 if (!rmesa->radeonScreen->kernel_mm)
 186                         radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
 187         }
 188 }
 189
 190 static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 191 {
 192     /* please flush pipe do all pending work */
 193     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 194                                   R300_SC_SCREENDOOR, 1));
 195     radeon_cs_write_dword(cs, 0x0);
 196     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 197                                   R300_SC_SCREENDOOR, 1));
 198     radeon_cs_write_dword(cs, 0x00FFFFFF);
 199     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 200                                   R300_SC_HYPERZ, 1));
 201     radeon_cs_write_dword(cs, 0x0);
 202     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 203                                   R300_US_CONFIG, 1));
 204     radeon_cs_write_dword(cs, 0x0);
 205     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 206                                   R300_ZB_CNTL, 1));
 207     radeon_cs_write_dword(cs, 0x0);
 208     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
 209     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 210                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 211     radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 212     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 213                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 214     radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 215     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
 216                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 217 }
 218
 219 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 220 {
 221         BATCH_LOCALS(radeon);
 222
 223         cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 224         BEGIN_BATCH_NO_AUTOSTATE(2);
 225         OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
 226         END_BATCH();
 227         end_3d(radeon);
 228 }
 229
 230 static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
 231 {
 232         r300ContextPtr r300 = R300_CONTEXT(ctx);
 233         if (mode)
 234                 r300->radeon.Fallback |= bit;
 235         else
 236                 r300->radeon.Fallback &= ~bit;
 237 }
 238
 239 static void r300_emit_query_finish(radeonContextPtr radeon)
 240 {
 241         r300ContextPtr r300 = (r300ContextPtr)radeon;
 242         struct radeon_query_object *query = radeon->query.current;
 243         BATCH_LOCALS(radeon);
 244
 245         BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2);
 246         switch (r300->radeon.radeonScreen->num_gb_pipes) {
 247         case 4:
 248                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 249                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 250                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 251         case 3:
 252                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
 253                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 254                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 255         case 2:
 256                 if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
 257                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 258                 } else {
 259                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
 260                 }
 261                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 262                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 263         case 1:
 264         default:
 265                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
 266                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 267                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 268                 break;
 269         }
 270         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 271         END_BATCH();
 272         query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t);
 273         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 274         query->emitted_begin = GL_FALSE;
 275 }
 276
 277 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
 278 {
 279         BATCH_LOCALS(radeon);
 280         struct radeon_query_object *query = radeon->query.current;
 281
 282         BEGIN_BATCH_NO_AUTOSTATE(8);
 283         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 284         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 285         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 286         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 287         END_BATCH();
 288
 289         query->curr_offset += sizeof(uint32_t);
 290         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 291         query->emitted_begin = GL_FALSE;
 292 }
 293
 294 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 295 {
 296         BATCH_LOCALS(radeon);
 297         struct radeon_query_object *query = radeon->query.current;
 298
 299         BEGIN_BATCH_NO_AUTOSTATE(14);
 300         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 301         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 302         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 303         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 304         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 305         OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 306         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 307         END_BATCH();
 308
 309         query->curr_offset += 2 * sizeof(uint32_t);
 310         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 311         query->emitted_begin = GL_FALSE;
 312 }
 313
 314 static void r300_init_vtbl(radeonContextPtr radeon)
 315 {
 316         radeon->vtbl.get_lock = r300_get_lock;
 317         radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
 318         radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
 319         radeon->vtbl.swtcl_flush = r300_swtcl_flush;
 320         radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
 321         radeon->vtbl.fallback = r300_fallback;
 322         if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 323                 if (radeon->radeonScreen->num_z_pipes == 2)
 324                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z;
 325                 else
 326                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
 327         } else
 328                 radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 329
 330     radeon->vtbl.blit = r300_blit;
 331 }
 332
 333 static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
 334 {
 335         r300ContextPtr r300 = R300_CONTEXT(ctx);
 336
 337         ctx->Const.MaxTextureImageUnits =
 338             driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
 339         ctx->Const.MaxTextureCoordUnits =
 340             driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
 341         ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
 342                  ctx->Const.MaxTextureCoordUnits);
 343
 344         ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 345         ctx->Const.MaxTextureLodBias = 16.0;
 346
 347         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 348                 ctx->Const.MaxTextureLevels = 13;
 349                 ctx->Const.MaxCubeTextureLevels = 13;
 350                 ctx->Const.MaxTextureRectSize = 4096;
 351         }
 352         else {
 353                 ctx->Const.MaxTextureLevels = 12;
 354                 ctx->Const.MaxCubeTextureLevels = 12;
 355                 ctx->Const.MaxTextureRectSize = 2048;
 356         }
 357
 358         ctx->Const.MinPointSize = 1.0;
 359         ctx->Const.MinPointSizeAA = 1.0;
 360         ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
 361         ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
 362
 363         ctx->Const.MinLineWidth = 1.0;
 364         ctx->Const.MinLineWidthAA = 1.0;
 365         ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
 366         ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
 367
 368         ctx->Const.MaxDrawBuffers = 1;
 369
 370         /* currently bogus data */
 371         if (r300->options.hw_tcl_enabled) {
 372                 ctx->Const.VertexProgram.MaxNativeInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 373                 ctx->Const.VertexProgram.MaxNativeAluInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 374                 ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */
 375                 ctx->Const.VertexProgram.MaxNativeTemps = 32;
 376                 ctx->Const.VertexProgram.MaxNativeParameters = 256;     /* r420 */
 377                 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 378         }
 379
 380         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 381                 ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
 382                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 383
 384                 /* The hardware limits are higher than this,
 385                  * but the non-KMS DRM interface artificially limits us
 386                  * to this many instructions.
 387                  *
 388                  * We could of course work around it in the KMS path,
 389                  * but it would be a mess, so it seems wiser
 390                  * to leave it as is. Going forward, the Gallium driver
 391                  * will not be subject to these limitations.
 392                  */
 393                 ctx->Const.FragmentProgram.MaxNativeParameters = 255;
 394                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = 255;
 395                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = 255;
 396                 ctx->Const.FragmentProgram.MaxNativeInstructions = 255;
 397                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = 255;
 398                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 399         } else {
 400                 ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
 401                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 402                 ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
 403                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
 404                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
 405                 ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
 406                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
 407                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 408         }
 409
 410 }
 411
 412 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
 413 {
 414         struct r300_options options = { 0 };
 415
 416         driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
 417                             screen->driScreen->myNum, "r300");
 418
 419         r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
 420
 421         options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
 422         options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
 423         options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
 424
 425         if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
 426                 options.hw_tcl_enabled = 0;
 427         else
 428                 options.hw_tcl_enabled = 1;
 429
 430         options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
 431
 432         r300->options = options;
 433 }
 434
 435 static void r300InitGLExtensions(GLcontext *ctx)
 436 {
 437         r300ContextPtr r300 = R300_CONTEXT(ctx);
 438
 439         driInitExtensions(ctx, card_extensions, GL_TRUE);
 440         if (r300->radeon.radeonScreen->kernel_mm)
 441                 driInitExtensions(ctx, mm_extensions, GL_FALSE);
 442
 443         if (r300->options.stencil_two_side_disabled)
 444                 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
 445
 446         if (r300->options.s3tc_force_disabled) {
 447                 _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 448         } else if (ctx->Mesa_DXTn || r300->options.s3tc_force_enabled) {
 449                 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 450                 _mesa_enable_extension(ctx, "GL_S3_s3tc");
 451         }
 452
 453         if (!r300->radeon.radeonScreen->drmSupportsOcclusionQueries) {
 454                 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 455         }
 456 }
 457
 458 static void r300InitIoctlFuncs(struct dd_function_table *functions)
 459 {
 460         functions->Clear = _mesa_meta_Clear;
 461         functions->Finish = radeonFinish;
 462         functions->Flush = radeonFlush;
 463 }
 464
 465 /* Create the device specific rendering context.
 466  */
 467 GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 468                             __DRIcontext * driContextPriv,
 469                             void *sharedContextPrivate)
 470 {
 471         __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 472         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 473         struct dd_function_table functions;
 474         r300ContextPtr r300;
 475         GLcontext *ctx;
 476
 477         assert(glVisual);
 478         assert(driContextPriv);
 479         assert(screen);
 480
 481         r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
 482         if (!r300)
 483                 return GL_FALSE;
 484
 485         r300ParseOptions(r300, screen);
 486
 487         r300->radeon.radeonScreen = screen;
 488         r300_init_vtbl(&r300->radeon);
 489
 490         _mesa_init_driver_functions(&functions);
 491         r300InitIoctlFuncs(&functions);
 492         r300InitStateFuncs(&functions);
 493         r300InitTextureFuncs(&functions);
 494         r300InitShaderFuncs(&functions);
 495         radeonInitQueryObjFunctions(&functions);
 496         radeonInitBufferObjectFuncs(&functions);
 497
 498         if (r300->radeon.radeonScreen->kernel_mm) {
 499                 r300_init_texcopy_functions(&functions);
 500         }
 501
 502         if (!radeonInitContext(&r300->radeon, &functions,
 503                                glVisual, driContextPriv,
 504                                sharedContextPrivate)) {
 505                 FREE(r300);
 506                 return GL_FALSE;
 507         }
 508
 509         ctx = r300->radeon.glCtx;
 510
 511         r300->fallback = 0;
 512         if (r300->options.hw_tcl_enabled)
 513                 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
 514
 515         ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 516
 517         r300InitConstValues(ctx, screen);
 518
 519         _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 520
 521         /* Initialize the software rasterizer and helper modules.
 522          */
 523         _swrast_CreateContext(ctx);
 524         _vbo_CreateContext(ctx);
 525         _tnl_CreateContext(ctx);
 526         _swsetup_CreateContext(ctx);
 527         _swsetup_Wakeup(ctx);
 528
 529         /* Install the customized pipeline:
 530          */
 531         _tnl_destroy_pipeline(ctx);
 532         _tnl_install_pipeline(ctx, r300_pipeline);
 533         TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 534
 535         /* Configure swrast and TNL to match hardware characteristics:
 536          */
 537         _swrast_allow_pixel_fog(ctx, GL_FALSE);
 538         _swrast_allow_vertex_fog(ctx, GL_TRUE);
 539         _tnl_allow_pixel_fog(ctx, GL_FALSE);
 540         _tnl_allow_vertex_fog(ctx, GL_TRUE);
 541
 542         if (r300->options.hw_tcl_enabled) {
 543                 r300InitDraw(ctx);
 544         } else {
 545                 r300InitSwtcl(ctx);
 546         }
 547
 548         r300_blit_init(r300);
 549         radeon_fbo_init(&r300->radeon);
 550         radeonInitSpanFuncs( ctx );
 551         r300InitCmdBuf(r300);
 552         r300InitState(r300);
 553         r300InitShaderFunctions(r300);
 554
 555         r300InitGLExtensions(ctx);
 556
 557         return GL_TRUE;
 558 }
 559