src/mesa/drivers/dri/r300/r300_context.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  *
  35  * \author Nicolai Haehnle <prefect_@gmx.net>
  36  */
  37
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "main/imports.h"
  43 #include "main/matrix.h"
  44 #include "main/extensions.h"
  45 #include "main/state.h"
  46 #include "main/bufferobj.h"
  47 #include "main/texobj.h"
  48
  49 #include "swrast/swrast.h"
  50 #include "swrast_setup/swrast_setup.h"
  51 #include "vbo/vbo.h"
  52
  53 #include "tnl/tnl.h"
  54 #include "tnl/t_pipeline.h"
  55 #include "tnl/t_vp_build.h"
  56
  57 #include "drivers/common/driverfuncs.h"
  58
  59 #include "r300_context.h"
  60 #include "radeon_context.h"
  61 #include "radeon_span.h"
  62 #include "r300_cmdbuf.h"
  63 #include "r300_state.h"
  64 #include "r300_ioctl.h"
  65 #include "r300_tex.h"
  66 #include "r300_emit.h"
  67 #include "r300_swtcl.h"
  68 #include "radeon_bocs_wrapper.h"
  69 #include "radeon_buffer_objects.h"
  70 #include "radeon_queryobj.h"
  71
  72 #include "vblank.h"
  73 #include "utils.h"
  74 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  75
  76 #define need_GL_VERSION_2_0
  77 #define need_GL_ARB_occlusion_query
  78 #define need_GL_ARB_point_parameters
  79 #define need_GL_ARB_vertex_program
  80 #define need_GL_EXT_blend_equation_separate
  81 #define need_GL_EXT_blend_func_separate
  82 #define need_GL_EXT_blend_minmax
  83 #define need_GL_EXT_framebuffer_blit
  84 #define need_GL_EXT_framebuffer_object
  85 #define need_GL_EXT_fog_coord
  86 #define need_GL_EXT_gpu_program_parameters
  87 #define need_GL_EXT_secondary_color
  88 #define need_GL_EXT_stencil_two_side
  89 #define need_GL_ATI_separate_stencil
  90 #define need_GL_NV_vertex_program
  91
  92 #include "extension_helper.h"
  93
  94
  95 const struct dri_extension card_extensions[] = {
  96   /* *INDENT-OFF* */
  97   {"GL_ARB_depth_texture",              NULL},
  98   {"GL_ARB_fragment_program",           NULL},
  99   {"GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
 100   {"GL_ARB_multitexture",               NULL},
 101   {"GL_ARB_point_parameters",           GL_ARB_point_parameters_functions},
 102   {"GL_ARB_shadow",                     NULL},
 103   {"GL_ARB_shadow_ambient",             NULL},
 104   {"GL_ARB_texture_border_clamp",       NULL},
 105   {"GL_ARB_texture_cube_map",           NULL},
 106   {"GL_ARB_texture_env_add",            NULL},
 107   {"GL_ARB_texture_env_combine",        NULL},
 108   {"GL_ARB_texture_env_crossbar",       NULL},
 109   {"GL_ARB_texture_env_dot3",           NULL},
 110   {"GL_ARB_texture_mirrored_repeat",    NULL},
 111   {"GL_ARB_vertex_program",             GL_ARB_vertex_program_functions},
 112   {"GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions},
 113   {"GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions},
 114   {"GL_EXT_blend_minmax",               GL_EXT_blend_minmax_functions},
 115   {"GL_EXT_blend_subtract",             NULL},
 116   {"GL_EXT_packed_depth_stencil",       NULL},
 117   {"GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
 118   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
 119   {"GL_EXT_secondary_color",            GL_EXT_secondary_color_functions},
 120   {"GL_EXT_shadow_funcs",               NULL},
 121   {"GL_EXT_stencil_two_side",           GL_EXT_stencil_two_side_functions},
 122   {"GL_EXT_stencil_wrap",               NULL},
 123   {"GL_EXT_texture_edge_clamp",         NULL},
 124   {"GL_EXT_texture_env_combine",        NULL},
 125   {"GL_EXT_texture_env_dot3",           NULL},
 126   {"GL_EXT_texture_filter_anisotropic", NULL},
 127   {"GL_EXT_texture_lod_bias",           NULL},
 128   {"GL_EXT_texture_mirror_clamp",       NULL},
 129   {"GL_EXT_texture_rectangle",          NULL},
 130   {"GL_EXT_texture_sRGB",               NULL},
 131   {"GL_EXT_vertex_array_bgra",          NULL},
 132   {"GL_ATI_separate_stencil",           GL_ATI_separate_stencil_functions},
 133   {"GL_ATI_texture_env_combine3",       NULL},
 134   {"GL_ATI_texture_mirror_once",        NULL},
 135   {"GL_MESA_pack_invert",               NULL},
 136   {"GL_MESA_ycbcr_texture",             NULL},
 137   {"GL_MESAX_texture_float",            NULL},
 138   {"GL_NV_blend_square",                NULL},
 139   {"GL_NV_vertex_program",              GL_NV_vertex_program_functions},
 140   {"GL_SGIS_generate_mipmap",           NULL},
 141   {NULL,                                NULL}
 142   /* *INDENT-ON* */
 143 };
 144
 145
 146 const struct dri_extension mm_extensions[] = {
 147   { "GL_EXT_framebuffer_blit",  GL_EXT_framebuffer_blit_functions },
 148   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 149   { NULL, NULL }
 150 };
 151
 152 /**
 153  * The GL 2.0 functions are needed to make display lists work with
 154  * functions added by GL_ATI_separate_stencil.
 155  */
 156 const struct dri_extension gl_20_extension[] = {
 157   {"GL_VERSION_2_0",                    GL_VERSION_2_0_functions },
 158 };
 159
 160 static const struct tnl_pipeline_stage *r300_pipeline[] = {
 161         /* Catch any t&l fallbacks
 162          */
 163         &_tnl_vertex_transform_stage,
 164         &_tnl_normal_transform_stage,
 165         &_tnl_lighting_stage,
 166         &_tnl_fog_coordinate_stage,
 167         &_tnl_texgen_stage,
 168         &_tnl_texture_transform_stage,
 169         &_tnl_point_attenuation_stage,
 170         &_tnl_vertex_program_stage,
 171         &_tnl_render_stage,
 172         0,
 173 };
 174
 175 static void r300_get_lock(radeonContextPtr rmesa)
 176 {
 177         drm_radeon_sarea_t *sarea = rmesa->sarea;
 178
 179         if (sarea->ctx_owner != rmesa->dri.hwContext) {
 180                 sarea->ctx_owner = rmesa->dri.hwContext;
 181                 if (!rmesa->radeonScreen->kernel_mm)
 182                         radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
 183         }
 184 }
 185
 186 static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 187 {
 188     /* please flush pipe do all pending work */
 189     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 190                                   R300_SC_SCREENDOOR, 1));
 191     radeon_cs_write_dword(cs, 0x0);
 192     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 193                                   R300_SC_SCREENDOOR, 1));
 194     radeon_cs_write_dword(cs, 0x00FFFFFF);
 195     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 196                                   R300_SC_HYPERZ, 1));
 197     radeon_cs_write_dword(cs, 0x0);
 198     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 199                                   R300_US_CONFIG, 1));
 200     radeon_cs_write_dword(cs, 0x0);
 201     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 202                                   R300_ZB_CNTL, 1));
 203     radeon_cs_write_dword(cs, 0x0);
 204     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
 205     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 206                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 207     radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 208     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 209                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 210     radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 211     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
 212                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 213 }
 214
 215 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 216 {
 217         BATCH_LOCALS(radeon);
 218
 219         cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 220         BEGIN_BATCH_NO_AUTOSTATE(2);
 221         OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
 222         END_BATCH();
 223         end_3d(radeon);
 224 }
 225
 226 static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
 227 {
 228         r300ContextPtr r300 = R300_CONTEXT(ctx);
 229         if (mode)
 230                 r300->radeon.Fallback |= bit;
 231         else
 232                 r300->radeon.Fallback &= ~bit;
 233 }
 234
 235 static void r300_emit_query_finish(radeonContextPtr radeon)
 236 {
 237         r300ContextPtr r300 = (r300ContextPtr)radeon;
 238         struct radeon_query_object *query = radeon->query.current;
 239         BATCH_LOCALS(radeon);
 240
 241         BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2);
 242         switch (r300->radeon.radeonScreen->num_gb_pipes) {
 243         case 4:
 244                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 245                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 246                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 247         case 3:
 248                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
 249                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 250                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 251         case 2:
 252                 if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
 253                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 254                 } else {
 255                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
 256                 }
 257                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 258                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 259         case 1:
 260         default:
 261                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
 262                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 263                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 264                 break;
 265         }
 266         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 267         END_BATCH();
 268         query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t);
 269         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 270         query->emitted_begin = GL_FALSE;
 271 }
 272
 273 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
 274 {
 275         BATCH_LOCALS(radeon);
 276         struct radeon_query_object *query = radeon->query.current;
 277
 278         BEGIN_BATCH_NO_AUTOSTATE(8);
 279         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 280         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 281         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 282         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 283         END_BATCH();
 284
 285         query->curr_offset += sizeof(uint32_t);
 286         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 287         query->emitted_begin = GL_FALSE;
 288 }
 289
 290 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 291 {
 292         BATCH_LOCALS(radeon);
 293         struct radeon_query_object *query = radeon->query.current;
 294
 295         BEGIN_BATCH_NO_AUTOSTATE(14);
 296         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 297         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 298         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 299         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 300         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 301         OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 302         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 303         END_BATCH();
 304
 305         query->curr_offset += 2 * sizeof(uint32_t);
 306         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 307         query->emitted_begin = GL_FALSE;
 308 }
 309
 310 static void r300_init_vtbl(radeonContextPtr radeon)
 311 {
 312         radeon->vtbl.get_lock = r300_get_lock;
 313         radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
 314         radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
 315         radeon->vtbl.swtcl_flush = r300_swtcl_flush;
 316         radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
 317         radeon->vtbl.fallback = r300_fallback;
 318         if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 319                 if (radeon->radeonScreen->num_z_pipes == 2)
 320                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z;
 321                 else
 322                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
 323         } else
 324                 radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 325 }
 326
 327 static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
 328 {
 329         r300ContextPtr r300 = R300_CONTEXT(ctx);
 330
 331         ctx->Const.MaxTextureImageUnits =
 332             driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
 333         ctx->Const.MaxTextureCoordUnits =
 334             driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
 335         ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
 336                  ctx->Const.MaxTextureCoordUnits);
 337
 338         ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 339         ctx->Const.MaxTextureLodBias = 16.0;
 340
 341         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 342                 ctx->Const.MaxTextureLevels = 13;
 343                 ctx->Const.MaxCubeTextureLevels = 13;
 344                 ctx->Const.MaxTextureRectSize = 4096;
 345         }
 346         else {
 347                 ctx->Const.MaxTextureLevels = 12;
 348                 ctx->Const.MaxCubeTextureLevels = 12;
 349                 ctx->Const.MaxTextureRectSize = 2048;
 350         }
 351
 352         ctx->Const.MinPointSize = 1.0;
 353         ctx->Const.MinPointSizeAA = 1.0;
 354         ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
 355         ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
 356
 357         ctx->Const.MinLineWidth = 1.0;
 358         ctx->Const.MinLineWidthAA = 1.0;
 359         ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
 360         ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
 361
 362         ctx->Const.MaxDrawBuffers = 1;
 363
 364         /* currently bogus data */
 365         if (r300->options.hw_tcl_enabled) {
 366                 ctx->Const.VertexProgram.MaxNativeInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 367                 ctx->Const.VertexProgram.MaxNativeAluInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 368                 ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */
 369                 ctx->Const.VertexProgram.MaxNativeTemps = 32;
 370                 ctx->Const.VertexProgram.MaxNativeParameters = 256;     /* r420 */
 371                 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 372         }
 373
 374         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 375                 ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
 376                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 377                 ctx->Const.FragmentProgram.MaxNativeParameters = R500_PFS_NUM_CONST_REGS;
 378                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R500_PFS_MAX_INST;
 379                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R500_PFS_MAX_INST;
 380                 ctx->Const.FragmentProgram.MaxNativeInstructions = R500_PFS_MAX_INST;
 381                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R500_PFS_MAX_INST;
 382                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 383         } else {
 384                 ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
 385                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 386                 ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
 387                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
 388                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
 389                 ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
 390                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
 391                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 392         }
 393
 394 }
 395
 396 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
 397 {
 398         struct r300_options options = { 0 };
 399
 400         driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
 401                             screen->driScreen->myNum, "r300");
 402
 403         r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
 404
 405         options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
 406         options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
 407         options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
 408
 409         if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
 410                 options.hw_tcl_enabled = 0;
 411         else
 412                 options.hw_tcl_enabled = 1;
 413
 414         options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
 415
 416         r300->options = options;
 417 }
 418
 419 static void r300InitGLExtensions(GLcontext *ctx)
 420 {
 421         r300ContextPtr r300 = R300_CONTEXT(ctx);
 422
 423         driInitExtensions(ctx, card_extensions, GL_TRUE);
 424         if (r300->radeon.radeonScreen->kernel_mm)
 425                 driInitExtensions(ctx, mm_extensions, GL_FALSE);
 426
 427         if (r300->options.stencil_two_side_disabled)
 428                 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
 429
 430         if (r300->options.s3tc_force_enabled) {
 431                 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 432                 _mesa_enable_extension(ctx, "GL_S3_s3tc");
 433         } else if (r300->options.s3tc_force_disabled) {
 434                 _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 435         }
 436
 437         if (!r300->radeon.radeonScreen->drmSupportsOcclusionQueries) {
 438                 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 439         }
 440 }
 441
 442 /* Create the device specific rendering context.
 443  */
 444 GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 445                             __DRIcontextPrivate * driContextPriv,
 446                             void *sharedContextPrivate)
 447 {
 448         __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 449         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 450         struct dd_function_table functions;
 451         r300ContextPtr r300;
 452         GLcontext *ctx;
 453
 454         assert(glVisual);
 455         assert(driContextPriv);
 456         assert(screen);
 457
 458         r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
 459         if (!r300)
 460                 return GL_FALSE;
 461
 462         r300ParseOptions(r300, screen);
 463
 464         r300->radeon.radeonScreen = screen;
 465         r300_init_vtbl(&r300->radeon);
 466
 467         _mesa_init_driver_functions(&functions);
 468         r300InitIoctlFuncs(&functions);
 469         r300InitStateFuncs(&functions);
 470         r300InitTextureFuncs(&functions);
 471         r300InitShaderFuncs(&functions);
 472         radeonInitQueryObjFunctions(&functions);
 473         radeonInitBufferObjectFuncs(&functions);
 474
 475         if (!radeonInitContext(&r300->radeon, &functions,
 476                                glVisual, driContextPriv,
 477                                sharedContextPrivate)) {
 478                 FREE(r300);
 479                 return GL_FALSE;
 480         }
 481
 482         ctx = r300->radeon.glCtx;
 483
 484         r300->fallback = 0;
 485         if (r300->options.hw_tcl_enabled)
 486                 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
 487
 488         ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 489
 490         r300InitConstValues(ctx, screen);
 491
 492         _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 493
 494         /* Initialize the software rasterizer and helper modules.
 495          */
 496         _swrast_CreateContext(ctx);
 497         _vbo_CreateContext(ctx);
 498         _tnl_CreateContext(ctx);
 499         _swsetup_CreateContext(ctx);
 500         _swsetup_Wakeup(ctx);
 501
 502         /* Install the customized pipeline:
 503          */
 504         _tnl_destroy_pipeline(ctx);
 505         _tnl_install_pipeline(ctx, r300_pipeline);
 506         TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 507
 508         /* Configure swrast and TNL to match hardware characteristics:
 509          */
 510         _swrast_allow_pixel_fog(ctx, GL_FALSE);
 511         _swrast_allow_vertex_fog(ctx, GL_TRUE);
 512         _tnl_allow_pixel_fog(ctx, GL_FALSE);
 513         _tnl_allow_vertex_fog(ctx, GL_TRUE);
 514
 515         if (r300->options.hw_tcl_enabled) {
 516                 r300InitDraw(ctx);
 517         } else {
 518                 r300InitSwtcl(ctx);
 519         }
 520
 521         radeon_fbo_init(&r300->radeon);
 522         radeonInitSpanFuncs( ctx );
 523         r300InitCmdBuf(r300);
 524         r300InitState(r300);
 525         r300InitShaderFunctions(r300);
 526
 527         r300InitGLExtensions(ctx);
 528
 529         return GL_TRUE;
 530 }
 531