2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Keith Whitwell <keith@tungstengraphics.com>
35 * \author Nicolai Haehnle <prefect_@gmx.net>
38 #include "main/glheader.h"
39 #include "main/api_arrayelt.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "main/imports.h"
43 #include "main/matrix.h"
44 #include "main/extensions.h"
45 #include "main/state.h"
46 #include "main/bufferobj.h"
47 #include "main/texobj.h"
49 #include "swrast/swrast.h"
50 #include "swrast_setup/swrast_setup.h"
54 #include "tnl/t_pipeline.h"
55 #include "tnl/t_vp_build.h"
57 #include "drivers/common/driverfuncs.h"
59 #include "r300_context.h"
60 #include "radeon_context.h"
61 #include "radeon_span.h"
62 #include "r300_cmdbuf.h"
63 #include "r300_state.h"
64 #include "r300_ioctl.h"
66 #include "r300_emit.h"
67 #include "r300_swtcl.h"
68 #include "radeon_bocs_wrapper.h"
69 #include "radeon_buffer_objects.h"
70 #include "radeon_queryobj.h"
74 #include "xmlpool.h" /* for symbolic values of enum-type options */
76 #define need_GL_VERSION_2_0
77 #define need_GL_ARB_occlusion_query
78 #define need_GL_ARB_point_parameters
79 #define need_GL_ARB_vertex_program
80 #define need_GL_EXT_blend_equation_separate
81 #define need_GL_EXT_blend_func_separate
82 #define need_GL_EXT_blend_minmax
83 #define need_GL_EXT_framebuffer_blit
84 #define need_GL_EXT_framebuffer_object
85 #define need_GL_EXT_fog_coord
86 #define need_GL_EXT_gpu_program_parameters
87 #define need_GL_EXT_provoking_vertex
88 #define need_GL_EXT_secondary_color
89 #define need_GL_EXT_stencil_two_side
90 #define need_GL_ATI_separate_stencil
91 #define need_GL_NV_vertex_program
93 #include "extension_helper.h"
96 const struct dri_extension card_extensions
[] = {
98 {"GL_ARB_depth_texture", NULL
},
99 {"GL_ARB_fragment_program", NULL
},
100 {"GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions
},
101 {"GL_ARB_multitexture", NULL
},
102 {"GL_ARB_point_parameters", GL_ARB_point_parameters_functions
},
103 {"GL_ARB_shadow", NULL
},
104 {"GL_ARB_shadow_ambient", NULL
},
105 {"GL_ARB_texture_border_clamp", NULL
},
106 {"GL_ARB_texture_cube_map", NULL
},
107 {"GL_ARB_texture_env_add", NULL
},
108 {"GL_ARB_texture_env_combine", NULL
},
109 {"GL_ARB_texture_env_crossbar", NULL
},
110 {"GL_ARB_texture_env_dot3", NULL
},
111 {"GL_ARB_texture_mirrored_repeat", NULL
},
112 {"GL_ARB_vertex_program", GL_ARB_vertex_program_functions
},
113 {"GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions
},
114 {"GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions
},
115 {"GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions
},
116 {"GL_EXT_blend_subtract", NULL
},
117 {"GL_EXT_packed_depth_stencil", NULL
},
118 {"GL_EXT_fog_coord", GL_EXT_fog_coord_functions
},
119 {"GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions
},
120 {"GL_EXT_provoking_vertex", GL_EXT_provoking_vertex_functions
},
121 {"GL_EXT_secondary_color", GL_EXT_secondary_color_functions
},
122 {"GL_EXT_shadow_funcs", NULL
},
123 {"GL_EXT_stencil_two_side", GL_EXT_stencil_two_side_functions
},
124 {"GL_EXT_stencil_wrap", NULL
},
125 {"GL_EXT_texture_edge_clamp", NULL
},
126 {"GL_EXT_texture_env_combine", NULL
},
127 {"GL_EXT_texture_env_dot3", NULL
},
128 {"GL_EXT_texture_filter_anisotropic", NULL
},
129 {"GL_EXT_texture_lod_bias", NULL
},
130 {"GL_EXT_texture_mirror_clamp", NULL
},
131 {"GL_EXT_texture_rectangle", NULL
},
132 {"GL_EXT_texture_sRGB", NULL
},
133 {"GL_EXT_vertex_array_bgra", NULL
},
134 {"GL_ATI_separate_stencil", GL_ATI_separate_stencil_functions
},
135 {"GL_ATI_texture_env_combine3", NULL
},
136 {"GL_ATI_texture_mirror_once", NULL
},
137 {"GL_MESA_pack_invert", NULL
},
138 {"GL_MESA_ycbcr_texture", NULL
},
139 {"GL_MESAX_texture_float", NULL
},
140 {"GL_NV_blend_square", NULL
},
141 {"GL_NV_vertex_program", GL_NV_vertex_program_functions
},
142 {"GL_SGIS_generate_mipmap", NULL
},
148 const struct dri_extension mm_extensions
[] = {
149 { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions
},
150 { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions
},
155 * The GL 2.0 functions are needed to make display lists work with
156 * functions added by GL_ATI_separate_stencil.
158 const struct dri_extension gl_20_extension
[] = {
159 {"GL_VERSION_2_0", GL_VERSION_2_0_functions
},
162 static const struct tnl_pipeline_stage
*r300_pipeline
[] = {
163 /* Catch any t&l fallbacks
165 &_tnl_vertex_transform_stage
,
166 &_tnl_normal_transform_stage
,
167 &_tnl_lighting_stage
,
168 &_tnl_fog_coordinate_stage
,
170 &_tnl_texture_transform_stage
,
171 &_tnl_point_attenuation_stage
,
172 &_tnl_vertex_program_stage
,
177 static void r300_get_lock(radeonContextPtr rmesa
)
179 drm_radeon_sarea_t
*sarea
= rmesa
->sarea
;
181 if (sarea
->ctx_owner
!= rmesa
->dri
.hwContext
) {
182 sarea
->ctx_owner
= rmesa
->dri
.hwContext
;
183 if (!rmesa
->radeonScreen
->kernel_mm
)
184 radeon_bo_legacy_texture_age(rmesa
->radeonScreen
->bom
);
188 static void r300_vtbl_emit_cs_header(struct radeon_cs
*cs
, radeonContextPtr rmesa
)
190 /* please flush pipe do all pending work */
191 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
192 R300_SC_SCREENDOOR
, 1));
193 radeon_cs_write_dword(cs
, 0x0);
194 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
195 R300_SC_SCREENDOOR
, 1));
196 radeon_cs_write_dword(cs
, 0x00FFFFFF);
197 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
199 radeon_cs_write_dword(cs
, 0x0);
200 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
202 radeon_cs_write_dword(cs
, 0x0);
203 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
205 radeon_cs_write_dword(cs
, 0x0);
206 radeon_cs_write_dword(cs
, cmdwait(rmesa
->radeonScreen
, R300_WAIT_3D
));
207 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
208 R300_RB3D_DSTCACHE_CTLSTAT
, 1));
209 radeon_cs_write_dword(cs
, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
210 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
211 R300_ZB_ZCACHE_CTLSTAT
, 1));
212 radeon_cs_write_dword(cs
, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
);
213 radeon_cs_write_dword(cs
, cmdwait(rmesa
->radeonScreen
,
214 R300_WAIT_3D
| R300_WAIT_3D_CLEAN
));
217 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon
)
219 BATCH_LOCALS(radeon
);
221 cp_wait(radeon
, R300_WAIT_3D
| R300_WAIT_3D_CLEAN
);
222 BEGIN_BATCH_NO_AUTOSTATE(2);
223 OUT_BATCH_REGVAL(R300_TX_INVALTAGS
, R300_TX_FLUSH
);
228 static void r300_fallback(GLcontext
*ctx
, GLuint bit
, GLboolean mode
)
230 r300ContextPtr r300
= R300_CONTEXT(ctx
);
232 r300
->radeon
.Fallback
|= bit
;
234 r300
->radeon
.Fallback
&= ~bit
;
237 static void r300_emit_query_finish(radeonContextPtr radeon
)
239 r300ContextPtr r300
= (r300ContextPtr
)radeon
;
240 struct radeon_query_object
*query
= radeon
->query
.current
;
241 BATCH_LOCALS(radeon
);
243 BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300
->radeon
.radeonScreen
->num_gb_pipes
+ 2);
244 switch (r300
->radeon
.radeonScreen
->num_gb_pipes
) {
246 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_3
);
247 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
248 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
250 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_2
);
251 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
252 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
254 if (r300
->radeon
.radeonScreen
->chip_family
<= CHIP_FAMILY_RV380
) {
255 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_3
);
257 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_1
);
259 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
260 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
263 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_0
);
264 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
265 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
268 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
270 query
->curr_offset
+= r300
->radeon
.radeonScreen
->num_gb_pipes
* sizeof(uint32_t);
271 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
272 query
->emitted_begin
= GL_FALSE
;
275 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon
)
277 BATCH_LOCALS(radeon
);
278 struct radeon_query_object
*query
= radeon
->query
.current
;
280 BEGIN_BATCH_NO_AUTOSTATE(8);
281 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
282 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
283 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
284 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
287 query
->curr_offset
+= sizeof(uint32_t);
288 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
289 query
->emitted_begin
= GL_FALSE
;
292 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon
)
294 BATCH_LOCALS(radeon
);
295 struct radeon_query_object
*query
= radeon
->query
.current
;
297 BEGIN_BATCH_NO_AUTOSTATE(14);
298 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
299 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
300 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
301 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
302 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
303 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+ sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
304 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
307 query
->curr_offset
+= 2 * sizeof(uint32_t);
308 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
309 query
->emitted_begin
= GL_FALSE
;
312 static void r300_init_vtbl(radeonContextPtr radeon
)
314 radeon
->vtbl
.get_lock
= r300_get_lock
;
315 radeon
->vtbl
.update_viewport_offset
= r300UpdateViewportOffset
;
316 radeon
->vtbl
.emit_cs_header
= r300_vtbl_emit_cs_header
;
317 radeon
->vtbl
.swtcl_flush
= r300_swtcl_flush
;
318 radeon
->vtbl
.pre_emit_atoms
= r300_vtbl_pre_emit_atoms
;
319 radeon
->vtbl
.fallback
= r300_fallback
;
320 if (radeon
->radeonScreen
->chip_family
== CHIP_FAMILY_RV530
) {
321 if (radeon
->radeonScreen
->num_z_pipes
== 2)
322 radeon
->vtbl
.emit_query_finish
= rv530_emit_query_finish_double_z
;
324 radeon
->vtbl
.emit_query_finish
= rv530_emit_query_finish_single_z
;
326 radeon
->vtbl
.emit_query_finish
= r300_emit_query_finish
;
329 static void r300InitConstValues(GLcontext
*ctx
, radeonScreenPtr screen
)
331 r300ContextPtr r300
= R300_CONTEXT(ctx
);
333 ctx
->Const
.MaxTextureImageUnits
=
334 driQueryOptioni(&r300
->radeon
.optionCache
, "texture_image_units");
335 ctx
->Const
.MaxTextureCoordUnits
=
336 driQueryOptioni(&r300
->radeon
.optionCache
, "texture_coord_units");
337 ctx
->Const
.MaxTextureUnits
= MIN2(ctx
->Const
.MaxTextureImageUnits
,
338 ctx
->Const
.MaxTextureCoordUnits
);
340 ctx
->Const
.MaxTextureMaxAnisotropy
= 16.0;
341 ctx
->Const
.MaxTextureLodBias
= 16.0;
343 if (screen
->chip_family
>= CHIP_FAMILY_RV515
) {
344 ctx
->Const
.MaxTextureLevels
= 13;
345 ctx
->Const
.MaxCubeTextureLevels
= 13;
346 ctx
->Const
.MaxTextureRectSize
= 4096;
349 ctx
->Const
.MaxTextureLevels
= 12;
350 ctx
->Const
.MaxCubeTextureLevels
= 12;
351 ctx
->Const
.MaxTextureRectSize
= 2048;
354 ctx
->Const
.MinPointSize
= 1.0;
355 ctx
->Const
.MinPointSizeAA
= 1.0;
356 ctx
->Const
.MaxPointSize
= R300_POINTSIZE_MAX
;
357 ctx
->Const
.MaxPointSizeAA
= R300_POINTSIZE_MAX
;
359 ctx
->Const
.MinLineWidth
= 1.0;
360 ctx
->Const
.MinLineWidthAA
= 1.0;
361 ctx
->Const
.MaxLineWidth
= R300_LINESIZE_MAX
;
362 ctx
->Const
.MaxLineWidthAA
= R300_LINESIZE_MAX
;
364 ctx
->Const
.MaxDrawBuffers
= 1;
366 /* currently bogus data */
367 if (r300
->options
.hw_tcl_enabled
) {
368 ctx
->Const
.VertexProgram
.MaxNativeInstructions
= VSF_MAX_FRAGMENT_LENGTH
/ 4;
369 ctx
->Const
.VertexProgram
.MaxNativeAluInstructions
= VSF_MAX_FRAGMENT_LENGTH
/ 4;
370 ctx
->Const
.VertexProgram
.MaxNativeAttribs
= 16; /* r420 */
371 ctx
->Const
.VertexProgram
.MaxNativeTemps
= 32;
372 ctx
->Const
.VertexProgram
.MaxNativeParameters
= 256; /* r420 */
373 ctx
->Const
.VertexProgram
.MaxNativeAddressRegs
= 1;
376 if (screen
->chip_family
>= CHIP_FAMILY_RV515
) {
377 ctx
->Const
.FragmentProgram
.MaxNativeTemps
= R500_PFS_NUM_TEMP_REGS
;
378 ctx
->Const
.FragmentProgram
.MaxNativeAttribs
= 11; /* copy i915... */
380 /* The hardware limits are higher than this,
381 * but the non-KMS DRM interface artificially limits us
382 * to this many instructions.
384 * We could of course work around it in the KMS path,
385 * but it would be a mess, so it seems wiser
386 * to leave it as is. Going forward, the Gallium driver
387 * will not be subject to these limitations.
389 ctx
->Const
.FragmentProgram
.MaxNativeParameters
= 255;
390 ctx
->Const
.FragmentProgram
.MaxNativeAluInstructions
= 255;
391 ctx
->Const
.FragmentProgram
.MaxNativeTexInstructions
= 255;
392 ctx
->Const
.FragmentProgram
.MaxNativeInstructions
= 255;
393 ctx
->Const
.FragmentProgram
.MaxNativeTexIndirections
= 255;
394 ctx
->Const
.FragmentProgram
.MaxNativeAddressRegs
= 0;
396 ctx
->Const
.FragmentProgram
.MaxNativeTemps
= R300_PFS_NUM_TEMP_REGS
;
397 ctx
->Const
.FragmentProgram
.MaxNativeAttribs
= 11; /* copy i915... */
398 ctx
->Const
.FragmentProgram
.MaxNativeParameters
= R300_PFS_NUM_CONST_REGS
;
399 ctx
->Const
.FragmentProgram
.MaxNativeAluInstructions
= R300_PFS_MAX_ALU_INST
;
400 ctx
->Const
.FragmentProgram
.MaxNativeTexInstructions
= R300_PFS_MAX_TEX_INST
;
401 ctx
->Const
.FragmentProgram
.MaxNativeInstructions
= R300_PFS_MAX_ALU_INST
+ R300_PFS_MAX_TEX_INST
;
402 ctx
->Const
.FragmentProgram
.MaxNativeTexIndirections
= R300_PFS_MAX_TEX_INDIRECT
;
403 ctx
->Const
.FragmentProgram
.MaxNativeAddressRegs
= 0;
408 static void r300ParseOptions(r300ContextPtr r300
, radeonScreenPtr screen
)
410 struct r300_options options
= { 0 };
412 driParseConfigFiles(&r300
->radeon
.optionCache
, &screen
->optionCache
,
413 screen
->driScreen
->myNum
, "r300");
415 r300
->radeon
.initialMaxAnisotropy
= driQueryOptionf(&r300
->radeon
.optionCache
, "def_max_anisotropy");
417 options
.stencil_two_side_disabled
= driQueryOptionb(&r300
->radeon
.optionCache
, "disable_stencil_two_side");
418 options
.s3tc_force_enabled
= driQueryOptionb(&r300
->radeon
.optionCache
, "force_s3tc_enable");
419 options
.s3tc_force_disabled
= driQueryOptionb(&r300
->radeon
.optionCache
, "disable_s3tc");
421 if (!(screen
->chip_flags
& RADEON_CHIPSET_TCL
) || driQueryOptioni(&r300
->radeon
.optionCache
, "tcl_mode") == DRI_CONF_TCL_SW
)
422 options
.hw_tcl_enabled
= 0;
424 options
.hw_tcl_enabled
= 1;
426 options
.conformance_mode
= !driQueryOptionb(&r300
->radeon
.optionCache
, "disable_lowimpact_fallback");
428 r300
->options
= options
;
431 static void r300InitGLExtensions(GLcontext
*ctx
)
433 r300ContextPtr r300
= R300_CONTEXT(ctx
);
435 driInitExtensions(ctx
, card_extensions
, GL_TRUE
);
436 if (r300
->radeon
.radeonScreen
->kernel_mm
)
437 driInitExtensions(ctx
, mm_extensions
, GL_FALSE
);
439 if (r300
->options
.stencil_two_side_disabled
)
440 _mesa_disable_extension(ctx
, "GL_EXT_stencil_two_side");
442 if (r300
->options
.s3tc_force_enabled
) {
443 _mesa_enable_extension(ctx
, "GL_EXT_texture_compression_s3tc");
444 _mesa_enable_extension(ctx
, "GL_S3_s3tc");
445 } else if (r300
->options
.s3tc_force_disabled
) {
446 _mesa_disable_extension(ctx
, "GL_EXT_texture_compression_s3tc");
449 if (!r300
->radeon
.radeonScreen
->drmSupportsOcclusionQueries
) {
450 _mesa_disable_extension(ctx
, "GL_ARB_occlusion_query");
454 /* Create the device specific rendering context.
456 GLboolean
r300CreateContext(const __GLcontextModes
* glVisual
,
457 __DRIcontextPrivate
* driContextPriv
,
458 void *sharedContextPrivate
)
460 __DRIscreenPrivate
*sPriv
= driContextPriv
->driScreenPriv
;
461 radeonScreenPtr screen
= (radeonScreenPtr
) (sPriv
->private);
462 struct dd_function_table functions
;
467 assert(driContextPriv
);
470 r300
= (r300ContextPtr
) CALLOC(sizeof(*r300
));
474 r300ParseOptions(r300
, screen
);
476 r300
->radeon
.radeonScreen
= screen
;
477 r300_init_vtbl(&r300
->radeon
);
479 _mesa_init_driver_functions(&functions
);
480 r300InitIoctlFuncs(&functions
);
481 r300InitStateFuncs(&functions
);
482 r300InitTextureFuncs(&functions
);
483 r300InitShaderFuncs(&functions
);
484 radeonInitQueryObjFunctions(&functions
);
485 radeonInitBufferObjectFuncs(&functions
);
487 if (!radeonInitContext(&r300
->radeon
, &functions
,
488 glVisual
, driContextPriv
,
489 sharedContextPrivate
)) {
494 ctx
= r300
->radeon
.glCtx
;
497 if (r300
->options
.hw_tcl_enabled
)
498 ctx
->VertexProgram
._MaintainTnlProgram
= GL_TRUE
;
500 ctx
->FragmentProgram
._MaintainTexEnvProgram
= GL_TRUE
;
502 r300InitConstValues(ctx
, screen
);
504 _mesa_set_mvp_with_dp4( ctx
, GL_TRUE
);
506 /* Initialize the software rasterizer and helper modules.
508 _swrast_CreateContext(ctx
);
509 _vbo_CreateContext(ctx
);
510 _tnl_CreateContext(ctx
);
511 _swsetup_CreateContext(ctx
);
512 _swsetup_Wakeup(ctx
);
514 /* Install the customized pipeline:
516 _tnl_destroy_pipeline(ctx
);
517 _tnl_install_pipeline(ctx
, r300_pipeline
);
518 TNL_CONTEXT(ctx
)->Driver
.RunPipeline
= _tnl_run_pipeline
;
520 /* Configure swrast and TNL to match hardware characteristics:
522 _swrast_allow_pixel_fog(ctx
, GL_FALSE
);
523 _swrast_allow_vertex_fog(ctx
, GL_TRUE
);
524 _tnl_allow_pixel_fog(ctx
, GL_FALSE
);
525 _tnl_allow_vertex_fog(ctx
, GL_TRUE
);
527 if (r300
->options
.hw_tcl_enabled
) {
533 radeon_fbo_init(&r300
->radeon
);
534 radeonInitSpanFuncs( ctx
);
535 r300InitCmdBuf(r300
);
537 r300InitShaderFunctions(r300
);
539 r300InitGLExtensions(ctx
);