src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 #define USER_BUFFERS
  51 /* KW: Disable this code.  Driver should hook into vbo module
  52  * directly, see i965 driver for example.
  53  */
  54 /* #define RADEON_VTXFMT_A */
  55 #define HW_VBOS
  56
  57 /* We don't handle 16 bits elts swapping yet */
  58 #ifdef MESA_BIG_ENDIAN
  59 #define FORCE_32BITS_ELTS
  60 #endif
  61
  62 //#define OPTIMIZE_ELTS
  63 #define CB_DPATH
  64
  65 struct r300_context;
  66 typedef struct r300_context r300ContextRec;
  67 typedef struct r300_context *r300ContextPtr;
  68
  69 #include "radeon_lock.h"
  70 #include "mm.h"
  71
  72 /* Checkpoint.. for convenience */
  73 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  74 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  75    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  76    with other compilers ... GLUE!
  77 */
  78 #if 1
  79 #define WARN_ONCE(a, ...)       { \
  80         static int warn##__LINE__=1; \
  81         if(warn##__LINE__){ \
  82                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  83                 fprintf(stderr, "File %s function %s line %d\n", \
  84                         __FILE__, __FUNCTION__, __LINE__); \
  85                 fprintf(stderr,  a, ## __VA_ARGS__);\
  86                 fprintf(stderr, "***************************************************************************\n"); \
  87                 warn##__LINE__=0;\
  88                 } \
  89         }
  90 #else
  91 #define WARN_ONCE(a, ...) {}
  92 #endif
  93
  94   /* We should probably change types within vertex_shader
  95       and pixel_shader structure later on */
  96 #define CARD32 GLuint
  97 #include "vertex_shader.h"
  98 #include "r300_fragprog.h"
  99 #undef CARD32
 100
 101 static __inline__ uint32_t r300PackFloat32(float fl)
 102 {
 103         union { float fl; uint32_t u; } u;
 104
 105         u.fl = fl;
 106         return u.u;
 107 }
 108
 109
 110 /************ DMA BUFFERS **************/
 111
 112 /* Need refcounting on dma buffers:
 113  */
 114 struct r300_dma_buffer {
 115         int refcount;           /* the number of retained regions in buf */
 116         drmBufPtr buf;
 117         int id;
 118 };
 119 #undef GET_START
 120 #ifdef USER_BUFFERS
 121 #define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start))
 122 #else
 123 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 124                         (rvb)->address - rmesa->dma.buf0_address +      \
 125                         (rvb)->start)
 126 #endif
 127 /* A retained region, eg vertices for indexed vertices.
 128  */
 129 struct r300_dma_region {
 130         struct r300_dma_buffer *buf;
 131         char *address;          /* == buf->address */
 132         int start, end, ptr;    /* offsets from start of buf */
 133
 134     int aos_offset;     /* address in GART memory */
 135     int aos_stride;     /* distance between elements, in dwords */
 136     int aos_size;       /* number of components (1-4) */
 137     int aos_reg;        /* VAP register assignment */
 138 };
 139
 140 struct r300_dma {
 141         /* Active dma region.  Allocations for vertices and retained
 142          * regions come from here.  Also used for emitting random vertices,
 143          * these may be flushed by calling flush_current();
 144          */
 145         struct r300_dma_region current;
 146
 147         void (*flush) (r300ContextPtr);
 148
 149         char *buf0_address;     /* start of buf[0], for index calcs */
 150
 151         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 152          * for which a DISCARD command is currently queued in the command buffer.
 153          */
 154         GLuint nr_released_bufs;
 155 };
 156
 157        /* Texture related */
 158
 159 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 160
 161 /* Texture object in locally shared texture space.
 162  */
 163 struct r300_tex_obj {
 164         driTextureObject base;
 165
 166         GLuint bufAddr;         /* Offset to start of locally
 167                                    shared texture block */
 168
 169         GLuint dirty_state;     /* Flags (1 per texunit) for
 170                                    whether or not this texobj
 171                                    has dirty hardware state
 172                                    (pp_*) that needs to be
 173                                    brought into the
 174                                    texunit. */
 175
 176         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 177         /* Six, for the cube faces */
 178
 179
 180         GLuint pitch; /* this isn't sent to hardware just used in calculations */
 181         /* hardware register values */
 182         /* Note that R200 has 8 registers per texture and R300 only 7 */
 183         GLuint filter;
 184         GLuint pitch_reg;
 185         GLuint size;    /* npot only */
 186         GLuint format;
 187         GLuint offset;  /* Image location in the card's address space.
 188                                    All cube faces follow. */
 189         GLuint unknown4;
 190         GLuint unknown5;
 191         /* end hardware registers */
 192
 193         /* registers computed by r200 code - keep them here to
 194            compare against what is actually written.
 195
 196            to be removed later.. */
 197         GLuint pp_border_color;
 198         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 199         GLuint format_x;
 200
 201
 202         GLboolean border_fallback;
 203
 204         GLuint tile_bits; /* hw texture tile bits used on this texture */
 205 };
 206
 207 struct r300_texture_env_state {
 208         r300TexObjPtr texobj;
 209         GLenum format;
 210         GLenum envMode;
 211 };
 212
 213
 214 /* The blit width for texture uploads
 215  */
 216 #define R300_BLIT_WIDTH_BYTES 1024
 217 #define R300_MAX_TEXTURE_UNITS 8
 218
 219 struct r300_texture_state {
 220         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 221         int tc_count; /* number of incoming texture coordinates from VAP */
 222 };
 223
 224 /**
 225  * A block of hardware state.
 226  *
 227  * When check returns non-zero, the returned number of dwords must be
 228  * copied verbatim into the command buffer in order to update a state atom
 229  * when it is dirty.
 230  */
 231 struct r300_state_atom {
 232         struct r300_state_atom *next, *prev;
 233         const char* name;       /* for debug */
 234         int cmd_size;           /* maximum size in dwords */
 235         GLuint idx;             /* index in an array (e.g. textures) */
 236         uint32_t* cmd;
 237         GLboolean dirty;
 238
 239         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 240 };
 241
 242
 243 #define R300_VPT_CMD_0          0
 244 #define R300_VPT_XSCALE         1
 245 #define R300_VPT_XOFFSET        2
 246 #define R300_VPT_YSCALE         3
 247 #define R300_VPT_YOFFSET        4
 248 #define R300_VPT_ZSCALE         5
 249 #define R300_VPT_ZOFFSET        6
 250 #define R300_VPT_CMDSIZE        7
 251
 252 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 253 #define R300_VIR_CNTL_0         1
 254 #define R300_VIR_CNTL_1         2
 255 #define R300_VIR_CNTL_2         3
 256 #define R300_VIR_CNTL_3         4
 257 #define R300_VIR_CNTL_4         5
 258 #define R300_VIR_CNTL_5         6
 259 #define R300_VIR_CNTL_6         7
 260 #define R300_VIR_CNTL_7         8
 261 #define R300_VIR_CMDSIZE        9
 262
 263 #define R300_VIC_CMD_0          0
 264 #define R300_VIC_CNTL_0         1
 265 #define R300_VIC_CNTL_1         2
 266 #define R300_VIC_CMDSIZE        3
 267
 268 #define R300_VOF_CMD_0          0
 269 #define R300_VOF_CNTL_0         1
 270 #define R300_VOF_CNTL_1         2
 271 #define R300_VOF_CMDSIZE        3
 272
 273
 274 #define R300_PVS_CMD_0          0
 275 #define R300_PVS_CNTL_1         1
 276 #define R300_PVS_CNTL_2         2
 277 #define R300_PVS_CNTL_3         3
 278 #define R300_PVS_CMDSIZE        4
 279
 280 #define R300_GB_MISC_CMD_0              0
 281 #define R300_GB_MISC_MSPOS_0            1
 282 #define R300_GB_MISC_MSPOS_1            2
 283 #define R300_GB_MISC_TILE_CONFIG        3
 284 #define R300_GB_MISC_SELECT             4
 285 #define R300_GB_MISC_AA_CONFIG          5
 286 #define R300_GB_MISC_CMDSIZE            6
 287
 288 #define R300_TXE_CMD_0          0
 289 #define R300_TXE_ENABLE         1
 290 #define R300_TXE_CMDSIZE        2
 291
 292 #define R300_PS_CMD_0           0
 293 #define R300_PS_POINTSIZE       1
 294 #define R300_PS_CMDSIZE         2
 295
 296 #define R300_ZBS_CMD_0          0
 297 #define R300_ZBS_T_FACTOR       1
 298 #define R300_ZBS_T_CONSTANT     2
 299 #define R300_ZBS_W_FACTOR       3
 300 #define R300_ZBS_W_CONSTANT     4
 301 #define R300_ZBS_CMDSIZE        5
 302
 303 #define R300_CUL_CMD_0          0
 304 #define R300_CUL_CULL           1
 305 #define R300_CUL_CMDSIZE        2
 306
 307 #define R300_RC_CMD_0           0
 308 #define R300_RC_CNTL_0          1
 309 #define R300_RC_CNTL_1          2
 310 #define R300_RC_CMDSIZE         3
 311
 312 #define R300_RI_CMD_0           0
 313 #define R300_RI_INTERP_0        1
 314 #define R300_RI_INTERP_1        2
 315 #define R300_RI_INTERP_2        3
 316 #define R300_RI_INTERP_3        4
 317 #define R300_RI_INTERP_4        5
 318 #define R300_RI_INTERP_5        6
 319 #define R300_RI_INTERP_6        7
 320 #define R300_RI_INTERP_7        8
 321 #define R300_RI_CMDSIZE         9
 322
 323 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 324 #define R300_RR_ROUTE_0         1
 325 #define R300_RR_ROUTE_1         2
 326 #define R300_RR_ROUTE_2         3
 327 #define R300_RR_ROUTE_3         4
 328 #define R300_RR_ROUTE_4         5
 329 #define R300_RR_ROUTE_5         6
 330 #define R300_RR_ROUTE_6         7
 331 #define R300_RR_ROUTE_7         8
 332 #define R300_RR_CMDSIZE         9
 333
 334 #define R300_FP_CMD_0           0
 335 #define R300_FP_CNTL0           1
 336 #define R300_FP_CNTL1           2
 337 #define R300_FP_CNTL2           3
 338 #define R300_FP_CMD_1           4
 339 #define R300_FP_NODE0           5
 340 #define R300_FP_NODE1           6
 341 #define R300_FP_NODE2           7
 342 #define R300_FP_NODE3           8
 343 #define R300_FP_CMDSIZE         9
 344
 345 #define R300_FPT_CMD_0          0
 346 #define R300_FPT_INSTR_0        1
 347 #define R300_FPT_CMDSIZE        65
 348
 349 #define R300_FPI_CMD_0          0
 350 #define R300_FPI_INSTR_0        1
 351 #define R300_FPI_CMDSIZE        65
 352
 353 #define R300_FPP_CMD_0          0
 354 #define R300_FPP_PARAM_0        1
 355 #define R300_FPP_CMDSIZE        (32*4+1)
 356
 357 #define R300_FOGS_CMD_0         0
 358 #define R300_FOGS_STATE         1
 359 #define R300_FOGS_CMDSIZE       2
 360
 361 #define R300_FOGC_CMD_0         0
 362 #define R300_FOGC_R             1
 363 #define R300_FOGC_G             2
 364 #define R300_FOGC_B             3
 365 #define R300_FOGC_CMDSIZE       4
 366
 367 #define R300_FOGP_CMD_0         0
 368 #define R300_FOGP_SCALE         1
 369 #define R300_FOGP_START         2
 370 #define R300_FOGP_CMDSIZE       3
 371
 372 #define R300_AT_CMD_0           0
 373 #define R300_AT_ALPHA_TEST      1
 374 #define R300_AT_UNKNOWN         2
 375 #define R300_AT_CMDSIZE         3
 376
 377 #define R300_BLD_CMD_0          0
 378 #define R300_BLD_CBLEND         1
 379 #define R300_BLD_ABLEND         2
 380 #define R300_BLD_CMDSIZE        3
 381
 382 #define R300_CMK_CMD_0          0
 383 #define R300_CMK_COLORMASK      1
 384 #define R300_CMK_CMDSIZE        2
 385
 386 #define R300_CB_CMD_0           0
 387 #define R300_CB_OFFSET          1
 388 #define R300_CB_CMD_1           2
 389 #define R300_CB_PITCH           3
 390 #define R300_CB_CMDSIZE         4
 391
 392 #define R300_ZS_CMD_0           0
 393 #define R300_ZS_CNTL_0          1
 394 #define R300_ZS_CNTL_1          2
 395 #define R300_ZS_CNTL_2          3
 396 #define R300_ZS_CMDSIZE         4
 397
 398 #define R300_ZB_CMD_0           0
 399 #define R300_ZB_OFFSET          1
 400 #define R300_ZB_PITCH           2
 401 #define R300_ZB_CMDSIZE         3
 402
 403 #define R300_VPI_CMD_0          0
 404 #define R300_VPI_INSTR_0        1
 405 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 406
 407 #define R300_VPP_CMD_0          0
 408 #define R300_VPP_PARAM_0        1
 409 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 410
 411 #define R300_VPS_CMD_0          0
 412 #define R300_VPS_ZERO_0         1
 413 #define R300_VPS_ZERO_1         2
 414 #define R300_VPS_POINTSIZE      3
 415 #define R300_VPS_ZERO_3         4
 416 #define R300_VPS_CMDSIZE        5
 417
 418         /* the layout is common for all fields inside tex */
 419 #define R300_TEX_CMD_0          0
 420 #define R300_TEX_VALUE_0        1
 421 /* We don't really use this, instead specify mtu+1 dynamically
 422 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 423 */
 424
 425 /**
 426  * Cache for hardware register state.
 427  */
 428 struct r300_hw_state {
 429         struct r300_state_atom atomlist;
 430
 431         GLboolean       is_dirty;
 432         GLboolean       all_dirty;
 433         int             max_state_size; /* in dwords */
 434
 435         struct r300_state_atom vpt;     /* viewport (1D98) */
 436         struct r300_state_atom unk2080; /* (2080) */
 437         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 438         struct r300_state_atom vte;     /* (20B0) */
 439         struct r300_state_atom unk2134; /* (2134) */
 440         struct r300_state_atom unk2140; /* (2140) */
 441         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 442         struct r300_state_atom vic;     /* vap input control (2180) */
 443         struct r300_state_atom unk21DC; /* (21DC) */
 444         struct r300_state_atom unk221C; /* (221C) */
 445         struct r300_state_atom unk2220; /* (2220) */
 446         struct r300_state_atom unk2288; /* (2288) */
 447         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 448         struct r300_state_atom gb_enable; /* (4008) */
 449         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 450         struct r300_state_atom unk4200; /* (4200) */
 451         struct r300_state_atom unk4214; /* (4214) */
 452         struct r300_state_atom ps;      /* pointsize (421C) */
 453         struct r300_state_atom unk4230; /* (4230) */
 454         struct r300_state_atom lcntl;   /* line control */
 455         struct r300_state_atom unk4260; /* (4260) */
 456         struct r300_state_atom unk4274; /* (4274) */
 457         struct r300_state_atom unk4288; /* (4288) */
 458         struct r300_state_atom fogp;    /* fog parameters (4294) */
 459         struct r300_state_atom unk429C; /* (429C) */
 460         struct r300_state_atom unk42A0; /* (42A0) */
 461         struct r300_state_atom zbs;     /* zbias (42A4) */
 462         struct r300_state_atom unk42B4; /* (42B4) */
 463         struct r300_state_atom cul;     /* cull cntl (42B8) */
 464         struct r300_state_atom unk42C0; /* (42C0) */
 465         struct r300_state_atom rc;      /* rs control (4300) */
 466         struct r300_state_atom ri;      /* rs interpolators (4310) */
 467         struct r300_state_atom rr;      /* rs route (4330) */
 468         struct r300_state_atom unk43A4; /* (43A4) */
 469         struct r300_state_atom unk43E8; /* (43E8) */
 470         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 471         struct r300_state_atom fpt;     /* texi - (4620) */
 472         struct r300_state_atom unk46A4; /* (46A4) */
 473         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 474         struct r300_state_atom fogs;    /* fog state (4BC0) */
 475         struct r300_state_atom fogc;    /* fog color (4BC8) */
 476         struct r300_state_atom at;      /* alpha test (4BD4) */
 477         struct r300_state_atom unk4BD8; /* (4BD8) */
 478         struct r300_state_atom fpp;     /* 0x4C00 and following */
 479         struct r300_state_atom unk4E00; /* (4E00) */
 480         struct r300_state_atom bld;     /* blending (4E04) */
 481         struct r300_state_atom cmk;     /* colormask (4E0C) */
 482         struct r300_state_atom unk4E10; /* constant blend color + ??? (4E10) */
 483         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 484         struct r300_state_atom unk4E50; /* (4E50) */
 485         struct r300_state_atom unk4E88; /* (4E88) */
 486         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 487         struct r300_state_atom zs;      /* zstencil control (4F00) */
 488         struct r300_state_atom unk4F10; /* (4F10) */
 489         struct r300_state_atom zb;      /* z buffer (4F20) */
 490         struct r300_state_atom unk4F28; /* (4F28) */
 491         struct r300_state_atom unk4F30; /* (4F30) */
 492         struct r300_state_atom unk4F44; /* (4F44) */
 493         struct r300_state_atom unk4F54; /* (4F54) */
 494
 495         struct r300_state_atom vpi;     /* vp instructions */
 496         struct r300_state_atom vpp;     /* vp parameters */
 497         struct r300_state_atom vps;     /* vertex point size (?) */
 498                 /* 8 texture units */
 499                 /* the state is grouped by function and not by
 500                    texture unit. This makes single unit updates
 501                    really awkward - we are much better off
 502                    updating the whole thing at once */
 503         struct {
 504                 struct r300_state_atom filter;
 505                 struct r300_state_atom unknown1;
 506                 struct r300_state_atom size;
 507                 struct r300_state_atom format;
 508                 struct r300_state_atom pitch;
 509                 struct r300_state_atom offset;
 510                 struct r300_state_atom unknown4;
 511                 struct r300_state_atom border_color;
 512                 } tex;
 513         struct r300_state_atom txe;     /* tex enable (4104) */
 514 };
 515
 516
 517 /**
 518  * This structure holds the command buffer while it is being constructed.
 519  *
 520  * The first batch of commands in the buffer is always the state that needs
 521  * to be re-emitted when the context is lost. This batch can be skipped
 522  * otherwise.
 523  */
 524 struct r300_cmdbuf {
 525         int             size;           /* DWORDs allocated for buffer */
 526         uint32_t*       cmd_buf;
 527         int             count_used;     /* DWORDs filled so far */
 528         int             count_reemit;   /* size of re-emission batch */
 529 };
 530
 531
 532 /**
 533  * State cache
 534  */
 535
 536 struct r300_depthbuffer_state {
 537         GLfloat scale;
 538 };
 539
 540 struct r300_stencilbuffer_state {
 541         GLuint clear;
 542         GLboolean hw_stencil;
 543
 544 };
 545
 546 /* Vertex shader state */
 547
 548 /* Perhaps more if we store programs in vmem? */
 549 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 550 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 551
 552 /* Can be tested with colormat currently. */
 553 #define VSF_MAX_FRAGMENT_TEMPS (14)
 554
 555
 556 struct r300_vertex_shader_fragment {
 557         int length;
 558         union {
 559                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 560                 float f[VSF_MAX_FRAGMENT_LENGTH];
 561                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH/4];
 562                 } body;
 563         };
 564
 565 #define VSF_DEST_PROGRAM        0x0
 566 #define VSF_DEST_MATRIX0        0x200
 567 #define VSF_DEST_MATRIX1        0x204
 568 #define VSF_DEST_MATRIX2        0x208
 569 #define VSF_DEST_VECTOR0        0x20c
 570 #define VSF_DEST_VECTOR1        0x20d
 571 #define VSF_DEST_UNKNOWN1       0x400
 572 #define VSF_DEST_UNKNOWN2       0x406
 573
 574 struct r300_vertex_shader_state {
 575         struct r300_vertex_shader_fragment program;
 576
 577         /* a bit of a waste - each uses only a subset of allocated space..
 578             but easier to program */
 579         struct r300_vertex_shader_fragment matrix[3];
 580         struct r300_vertex_shader_fragment vector[2];
 581
 582         struct r300_vertex_shader_fragment unknown1;
 583         struct r300_vertex_shader_fragment unknown2;
 584
 585         int program_start;
 586         int unknown_ptr1;  /* pointer within program space */
 587         int program_end;
 588
 589         int param_offset;
 590         int param_count;
 591
 592         int unknown_ptr2;  /* pointer within program space */
 593         int unknown_ptr3;  /* pointer within program space */
 594         };
 595
 596 extern int hw_tcl_on;
 597
 598 #define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 599
 600 /* Should but doesnt work */
 601 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 602
 603 //#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && (OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit)))) :
 604 //      (r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit))))
 605 //#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit))) :
 606 //      ctx->Texture.Unit[unit]._ReallyEnabled && r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit)))
 607
 608 #define TMU_ENABLED(ctx, unit) (ctx->Texture.Unit[unit]._ReallyEnabled)
 609
 610 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 611  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 612  */
 613 struct r300_vertex_program {
 614         struct gl_vertex_program mesa_program; /* Must be first */
 615         int translated;
 616
 617         struct r300_vertex_shader_fragment program;
 618         struct r300_vertex_shader_fragment params;
 619
 620         int pos_end;
 621         int num_temporaries; /* Number of temp vars used by program */
 622         int inputs[VERT_ATTRIB_MAX];
 623         int outputs[VERT_RESULT_MAX];
 624         int native;
 625         int ref_count;
 626         int use_ref_count;
 627 };
 628
 629 #define PFS_MAX_ALU_INST        64
 630 #define PFS_MAX_TEX_INST        64
 631 #define PFS_MAX_TEX_INDIRECT 4
 632 #define PFS_NUM_TEMP_REGS       32
 633 #define PFS_NUM_CONST_REGS      16
 634
 635 /* Tracking data for Mesa registers */
 636 struct reg_acc {
 637        int reg;        /* Assigned hw temp */
 638        unsigned int refcount; /* Number of uses by mesa program */
 639 };
 640
 641 struct r300_pfs_compile_state {
 642        int v_pos, s_pos;       /* highest ALU slots used */
 643
 644        /* Track some information gathered during opcode
 645         * construction.
 646         *
 647         * NOTE: Data is only set by the code, and isn't used yet.
 648         */
 649        struct {
 650                int vsrc[3];
 651                int ssrc[3];
 652                int umask;
 653        } slot[PFS_MAX_ALU_INST];
 654
 655        /* Used to map Mesa's inputs/temps onto hardware temps */
 656        int temp_in_use;
 657        struct reg_acc temps[PFS_NUM_TEMP_REGS];
 658        struct reg_acc inputs[32]; /* don't actually need 32... */
 659
 660        /* Track usage of hardware temps, for register allocation,
 661         * indirection detection, etc. */
 662        int hwreg_in_use;
 663        GLuint used_in_node;
 664        GLuint dest_in_node;
 665 };
 666
 667 struct r300_fragment_program {
 668         struct gl_fragment_program mesa_program;
 669
 670         GLcontext *ctx;
 671         GLboolean translated;
 672         GLboolean error;
 673         struct r300_pfs_compile_state *cs;
 674
 675         struct {
 676                 int length;
 677                 GLuint inst[PFS_MAX_TEX_INST];
 678         } tex;
 679
 680         struct {
 681                 struct {
 682                         GLuint inst0;
 683                         GLuint inst1;
 684                         GLuint inst2;
 685                         GLuint inst3;
 686                 } inst[PFS_MAX_ALU_INST];
 687         } alu;
 688
 689         struct {
 690                 int tex_offset;
 691                 int tex_end;
 692                 int alu_offset;
 693                 int alu_end;
 694                 int flags;
 695         } node[4];
 696         int cur_node;
 697         int first_node_has_tex;
 698
 699         int alu_offset;
 700         int alu_end;
 701         int tex_offset;
 702         int tex_end;
 703
 704         /* Hardware constants */
 705         GLfloat constant[PFS_NUM_CONST_REGS][4];
 706         int const_nr;
 707
 708         /* Tracked parameters */
 709         struct {
 710                 int idx;                        /* hardware index */
 711                 GLfloat *values;        /* pointer to values */
 712         } param[PFS_NUM_CONST_REGS];
 713         int param_nr;
 714         GLboolean params_uptodate;
 715
 716         int max_temp_idx;
 717 };
 718
 719 #define R300_MAX_AOS_ARRAYS             16
 720
 721 #define AOS_FORMAT_USHORT       0
 722 #define AOS_FORMAT_FLOAT        1
 723 #define AOS_FORMAT_UBYTE        2
 724 #define AOS_FORMAT_FLOAT_COLOR  3
 725
 726 #define REG_COORDS      0
 727 #define REG_COLOR0      1
 728 #define REG_TEX0        2
 729
 730 struct dt {
 731         GLint size;
 732         GLenum type;
 733         GLsizei stride;
 734         void *data;
 735 };
 736
 737 struct radeon_vertex_buffer {
 738         int Count;
 739         void *Elts;
 740         int elt_size;
 741         int elt_min, elt_max; /* debug */
 742
 743         struct dt AttribPtr[VERT_ATTRIB_MAX];
 744
 745         const struct _mesa_prim  *Primitive;
 746         GLuint      PrimitiveCount;
 747         GLint LockFirst;
 748         GLsizei LockCount;
 749         int lock_uptodate;
 750 };
 751
 752 struct r300_aos_rec {
 753         GLuint offset;
 754         int element_size; /* in dwords */
 755         int stride;       /* distance between elements, in dwords */
 756
 757         int format;
 758
 759         int ncomponents; /* number of components - between 1 and 4, inclusive */
 760
 761         int reg; /* which register they are assigned to. */
 762
 763         };
 764
 765 struct r300_state {
 766         struct r300_depthbuffer_state depth;
 767         struct r300_texture_state texture;
 768         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 769         struct r300_vertex_shader_state vertex_shader;
 770         struct r300_pfs_compile_state pfs_compile;
 771         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 772         int aos_count;
 773         struct radeon_vertex_buffer VB;
 774
 775         GLuint *Elts;
 776         struct r300_dma_region elt_dma;
 777
 778         DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for.
 779                                  They are the same as tnl->render_inputs for fixed pipeline */
 780
 781         struct {
 782                 int transform_offset;  /* Transform matrix offset, -1 if none */
 783                 } vap_param;  /* vertex processor parameter allocation - tells where to write parameters */
 784
 785         struct r300_stencilbuffer_state stencil;
 786
 787 };
 788
 789 #define R300_FALLBACK_NONE 0
 790 #define R300_FALLBACK_TCL 1
 791 #define R300_FALLBACK_RAST 2
 792
 793 /**
 794  * R300 context structure.
 795  */
 796 struct r300_context {
 797         struct radeon_context radeon; /* parent class, must be first */
 798
 799         struct r300_hw_state hw;
 800         struct r300_cmdbuf cmdbuf;
 801         struct r300_state state;
 802         struct gl_vertex_program *curr_vp;
 803
 804         /* Vertex buffers
 805          */
 806         struct r300_dma dma;
 807         GLboolean save_on_next_unlock;
 808         GLuint NewGLState;
 809
 810         /* Texture object bookkeeping
 811          */
 812         unsigned nr_heaps;
 813         driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
 814         driTextureObject swapped;
 815         int texture_depth;
 816         float initialMaxAnisotropy;
 817
 818         /* Clientdata textures;
 819          */
 820         GLuint prefer_gart_client_texturing;
 821
 822 #ifdef USER_BUFFERS
 823         struct radeon_memory_manager *rmm;
 824         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 825         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 826 #endif
 827
 828         GLboolean texmicrotile;
 829         GLboolean span_dlocking;
 830         GLboolean disable_lowimpact_fallback;
 831 };
 832
 833 struct r300_buffer_object {
 834         struct gl_buffer_object mesa_obj;
 835         int id;
 836 };
 837
 838 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 839
 840 static __inline GLuint r300PackColor( GLuint cpp,
 841                                         GLubyte r, GLubyte g,
 842                                         GLubyte b, GLubyte a )
 843 {
 844    switch ( cpp ) {
 845    case 2:
 846       return PACK_COLOR_565( r, g, b );
 847    case 4:
 848       return PACK_COLOR_8888( r, g, b, a );
 849    default:
 850       return 0;
 851    }
 852 }
 853 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 854 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 855                                    __DRIcontextPrivate * driContextPriv,
 856                                    void *sharedContextPrivate);
 857
 858 extern int r300_get_num_verts(r300ContextPtr rmesa, int num_verts, int prim);
 859
 860 void r300_translate_vertex_shader(struct r300_vertex_program *vp);
 861 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 862 extern int r300VertexProgUpdateParams(GLcontext *ctx, struct r300_vertex_program *vp, float *dst);
 863 extern int r300Fallback(GLcontext *ctx);
 864
 865 extern void radeon_vb_to_rvb(r300ContextPtr rmesa, struct radeon_vertex_buffer *rvb, struct vertex_buffer *vb);
 866 extern GLboolean r300_run_vb_render(GLcontext *ctx, struct tnl_pipeline_stage *stage);
 867
 868 #ifdef RADEON_VTXFMT_A
 869 extern void radeon_init_vtxfmt_a(r300ContextPtr rmesa);
 870 #endif
 871
 872 #ifdef HW_VBOS
 873 extern void r300_init_vbo_funcs(struct dd_function_table *functions);
 874 extern void r300_evict_vbos(GLcontext *ctx, int amount);
 875 #endif
 876
 877 #define RADEON_D_CAPTURE 0
 878 #define RADEON_D_PLAYBACK 1
 879 #define RADEON_D_PLAYBACK_RAW 2
 880 #define RADEON_D_T 3
 881
 882 #endif                          /* __R300_CONTEXT_H__ */