src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45
  46 #include "macros.h"
  47 #include "mtypes.h"
  48 #include "colormac.h"
  49
  50 #define USER_BUFFERS
  51
  52 struct r300_context;
  53 typedef struct r300_context r300ContextRec;
  54 typedef struct r300_context *r300ContextPtr;
  55
  56 #include "radeon_lock.h"
  57 #include "mm.h"
  58
  59 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  60    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  61    with other compilers ... GLUE!
  62 */
  63 #define WARN_ONCE(a, ...)       { \
  64         static int warn##__LINE__=1; \
  65         if(warn##__LINE__){ \
  66                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  67                 fprintf(stderr, "File %s function %s line %d\n", \
  68                         __FILE__, __FUNCTION__, __LINE__); \
  69                 fprintf(stderr,  a, ## __VA_ARGS__);\
  70                 fprintf(stderr, "***************************************************************************\n"); \
  71                 warn##__LINE__=0;\
  72                 } \
  73         }
  74
  75 #include "r300_vertprog.h"
  76 #include "r300_fragprog.h"
  77
  78 /**
  79  * This function takes a float and packs it into a uint32_t
  80  */
  81 static inline uint32_t r300PackFloat32(float fl)
  82 {
  83         union {
  84                 float fl;
  85                 uint32_t u;
  86         } u;
  87
  88         u.fl = fl;
  89         return u.u;
  90 }
  91
  92 /* This is probably wrong for some values, I need to test this
  93  * some more.  Range checking would be a good idea also..
  94  *
  95  * But it works for most things.  I'll fix it later if someone
  96  * else with a better clue doesn't
  97  */
  98 static inline uint32_t r300PackFloat24(float f)
  99 {
 100         float mantissa;
 101         int exponent;
 102         uint32_t float24 = 0;
 103
 104         if (f == 0.0)
 105                 return 0;
 106
 107         mantissa = frexpf(f, &exponent);
 108
 109         /* Handle -ve */
 110         if (mantissa < 0) {
 111                 float24 |= (1 << 23);
 112                 mantissa = mantissa * -1.0;
 113         }
 114         /* Handle exponent, bias of 63 */
 115         exponent += 62;
 116         float24 |= (exponent << 16);
 117         /* Kill 7 LSB of mantissa */
 118         float24 |= (r300PackFloat32(mantissa) & 0x7FFFFF) >> 7;
 119
 120         return float24;
 121 }
 122
 123 /************ DMA BUFFERS **************/
 124
 125 /* Need refcounting on dma buffers:
 126  */
 127 struct r300_dma_buffer {
 128         int refcount;           /**< the number of retained regions in buf */
 129         drmBufPtr buf;
 130         int id;
 131 };
 132 #undef GET_START
 133 #ifdef USER_BUFFERS
 134 #define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start))
 135 #else
 136 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 137                         (rvb)->address - rmesa->dma.buf0_address +      \
 138                         (rvb)->start)
 139 #endif
 140 /* A retained region, eg vertices for indexed vertices.
 141  */
 142 struct r300_dma_region {
 143         struct r300_dma_buffer *buf;
 144         char *address;          /* == buf->address */
 145         int start, end, ptr;    /* offsets from start of buf */
 146
 147         int aos_offset;         /* address in GART memory */
 148         int aos_stride;         /* distance between elements, in dwords */
 149         int aos_size;           /* number of components (1-4) */
 150 };
 151
 152 struct r300_dma {
 153         /* Active dma region.  Allocations for vertices and retained
 154          * regions come from here.  Also used for emitting random vertices,
 155          * these may be flushed by calling flush_current();
 156          */
 157         struct r300_dma_region current;
 158
 159         void (*flush) (r300ContextPtr);
 160
 161         char *buf0_address;     /* start of buf[0], for index calcs */
 162
 163         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 164          * for which a DISCARD command is currently queued in the command buffer.
 165          */
 166         GLuint nr_released_bufs;
 167 };
 168
 169        /* Texture related */
 170
 171 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 172
 173 /* Texture object in locally shared texture space.
 174  */
 175 struct r300_tex_obj {
 176         driTextureObject base;
 177
 178         GLuint bufAddr;         /* Offset to start of locally
 179                                    shared texture block */
 180
 181         GLuint dirty_state;     /* Flags (1 per texunit) for
 182                                    whether or not this texobj
 183                                    has dirty hardware state
 184                                    (pp_*) that needs to be
 185                                    brought into the
 186                                    texunit. */
 187
 188         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 189         /* Six, for the cube faces */
 190
 191         GLboolean image_override;       /* Image overridden by GLX_EXT_tfp */
 192
 193         GLuint pitch;           /* this isn't sent to hardware just used in calculations */
 194         /* hardware register values */
 195         /* Note that R200 has 8 registers per texture and R300 only 7 */
 196         GLuint filter;
 197         GLuint filter_1;
 198         GLuint pitch_reg;
 199         GLuint size;            /* npot only */
 200         GLuint format;
 201         GLuint offset;          /* Image location in the card's address space.
 202                                    All cube faces follow. */
 203         GLuint unknown4;
 204         GLuint unknown5;
 205         /* end hardware registers */
 206
 207         /* registers computed by r200 code - keep them here to
 208            compare against what is actually written.
 209
 210            to be removed later.. */
 211         GLuint pp_border_color;
 212         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 213         GLuint format_x;
 214
 215         GLboolean border_fallback;
 216
 217         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 218 };
 219
 220 struct r300_texture_env_state {
 221         r300TexObjPtr texobj;
 222         GLenum format;
 223         GLenum envMode;
 224 };
 225
 226 /* The blit width for texture uploads
 227  */
 228 #define R300_BLIT_WIDTH_BYTES 1024
 229 #define R300_MAX_TEXTURE_UNITS 8
 230
 231 struct r300_texture_state {
 232         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 233         int tc_count;           /* number of incoming texture coordinates from VAP */
 234 };
 235
 236 /**
 237  * A block of hardware state.
 238  *
 239  * When check returns non-zero, the returned number of dwords must be
 240  * copied verbatim into the command buffer in order to update a state atom
 241  * when it is dirty.
 242  */
 243 struct r300_state_atom {
 244         struct r300_state_atom *next, *prev;
 245         const char *name;       /* for debug */
 246         int cmd_size;           /* maximum size in dwords */
 247         GLuint idx;             /* index in an array (e.g. textures) */
 248         uint32_t *cmd;
 249         GLboolean dirty;
 250
 251         int (*check) (r300ContextPtr, struct r300_state_atom * atom);
 252 };
 253
 254 #define R300_VPT_CMD_0          0
 255 #define R300_VPT_XSCALE         1
 256 #define R300_VPT_XOFFSET        2
 257 #define R300_VPT_YSCALE         3
 258 #define R300_VPT_YOFFSET        4
 259 #define R300_VPT_ZSCALE         5
 260 #define R300_VPT_ZOFFSET        6
 261 #define R300_VPT_CMDSIZE        7
 262
 263 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
 264 #define R300_VIR_CNTL_0         1
 265 #define R300_VIR_CNTL_1         2
 266 #define R300_VIR_CNTL_2         3
 267 #define R300_VIR_CNTL_3         4
 268 #define R300_VIR_CNTL_4         5
 269 #define R300_VIR_CNTL_5         6
 270 #define R300_VIR_CNTL_6         7
 271 #define R300_VIR_CNTL_7         8
 272 #define R300_VIR_CMDSIZE        9
 273
 274 #define R300_VIC_CMD_0          0
 275 #define R300_VIC_CNTL_0         1
 276 #define R300_VIC_CNTL_1         2
 277 #define R300_VIC_CMDSIZE        3
 278
 279 #define R300_VOF_CMD_0          0
 280 #define R300_VOF_CNTL_0         1
 281 #define R300_VOF_CNTL_1         2
 282 #define R300_VOF_CMDSIZE        3
 283
 284 #define R300_PVS_CMD_0          0
 285 #define R300_PVS_CNTL_1         1
 286 #define R300_PVS_CNTL_2         2
 287 #define R300_PVS_CNTL_3         3
 288 #define R300_PVS_CMDSIZE        4
 289
 290 #define R300_GB_MISC_CMD_0              0
 291 #define R300_GB_MISC_MSPOS_0            1
 292 #define R300_GB_MISC_MSPOS_1            2
 293 #define R300_GB_MISC_TILE_CONFIG        3
 294 #define R300_GB_MISC_SELECT             4
 295 #define R300_GB_MISC_AA_CONFIG          5
 296 #define R300_GB_MISC_CMDSIZE            6
 297
 298 #define R300_TXE_CMD_0          0
 299 #define R300_TXE_ENABLE         1
 300 #define R300_TXE_CMDSIZE        2
 301
 302 #define R300_PS_CMD_0           0
 303 #define R300_PS_POINTSIZE       1
 304 #define R300_PS_CMDSIZE         2
 305
 306 #define R300_ZBS_CMD_0          0
 307 #define R300_ZBS_T_FACTOR       1
 308 #define R300_ZBS_T_CONSTANT     2
 309 #define R300_ZBS_W_FACTOR       3
 310 #define R300_ZBS_W_CONSTANT     4
 311 #define R300_ZBS_CMDSIZE        5
 312
 313 #define R300_CUL_CMD_0          0
 314 #define R300_CUL_CULL           1
 315 #define R300_CUL_CMDSIZE        2
 316
 317 #define R300_RC_CMD_0           0
 318 #define R300_RC_CNTL_0          1
 319 #define R300_RC_CNTL_1          2
 320 #define R300_RC_CMDSIZE         3
 321
 322 #define R300_RI_CMD_0           0
 323 #define R300_RI_INTERP_0        1
 324 #define R300_RI_INTERP_1        2
 325 #define R300_RI_INTERP_2        3
 326 #define R300_RI_INTERP_3        4
 327 #define R300_RI_INTERP_4        5
 328 #define R300_RI_INTERP_5        6
 329 #define R300_RI_INTERP_6        7
 330 #define R300_RI_INTERP_7        8
 331 #define R300_RI_CMDSIZE         9
 332
 333 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 334 #define R300_RR_ROUTE_0         1
 335 #define R300_RR_ROUTE_1         2
 336 #define R300_RR_ROUTE_2         3
 337 #define R300_RR_ROUTE_3         4
 338 #define R300_RR_ROUTE_4         5
 339 #define R300_RR_ROUTE_5         6
 340 #define R300_RR_ROUTE_6         7
 341 #define R300_RR_ROUTE_7         8
 342 #define R300_RR_CMDSIZE         9
 343
 344 #define R300_FP_CMD_0           0
 345 #define R300_FP_CNTL0           1
 346 #define R300_FP_CNTL1           2
 347 #define R300_FP_CNTL2           3
 348 #define R300_FP_CMD_1           4
 349 #define R300_FP_NODE0           5
 350 #define R300_FP_NODE1           6
 351 #define R300_FP_NODE2           7
 352 #define R300_FP_NODE3           8
 353 #define R300_FP_CMDSIZE         9
 354
 355 #define R300_FPT_CMD_0          0
 356 #define R300_FPT_INSTR_0        1
 357 #define R300_FPT_CMDSIZE        65
 358
 359 #define R300_FPI_CMD_0          0
 360 #define R300_FPI_INSTR_0        1
 361 #define R300_FPI_CMDSIZE        65
 362
 363 #define R300_FPP_CMD_0          0
 364 #define R300_FPP_PARAM_0        1
 365 #define R300_FPP_CMDSIZE        (32*4+1)
 366
 367 #define R300_FOGS_CMD_0         0
 368 #define R300_FOGS_STATE         1
 369 #define R300_FOGS_CMDSIZE       2
 370
 371 #define R300_FOGC_CMD_0         0
 372 #define R300_FOGC_R             1
 373 #define R300_FOGC_G             2
 374 #define R300_FOGC_B             3
 375 #define R300_FOGC_CMDSIZE       4
 376
 377 #define R300_FOGP_CMD_0         0
 378 #define R300_FOGP_SCALE         1
 379 #define R300_FOGP_START         2
 380 #define R300_FOGP_CMDSIZE       3
 381
 382 #define R300_AT_CMD_0           0
 383 #define R300_AT_ALPHA_TEST      1
 384 #define R300_AT_UNKNOWN         2
 385 #define R300_AT_CMDSIZE         3
 386
 387 #define R300_BLD_CMD_0          0
 388 #define R300_BLD_CBLEND         1
 389 #define R300_BLD_ABLEND         2
 390 #define R300_BLD_CMDSIZE        3
 391
 392 #define R300_CMK_CMD_0          0
 393 #define R300_CMK_COLORMASK      1
 394 #define R300_CMK_CMDSIZE        2
 395
 396 #define R300_CB_CMD_0           0
 397 #define R300_CB_OFFSET          1
 398 #define R300_CB_CMD_1           2
 399 #define R300_CB_PITCH           3
 400 #define R300_CB_CMDSIZE         4
 401
 402 #define R300_ZS_CMD_0           0
 403 #define R300_ZS_CNTL_0          1
 404 #define R300_ZS_CNTL_1          2
 405 #define R300_ZS_CNTL_2          3
 406 #define R300_ZS_CMDSIZE         4
 407
 408 #define R300_ZB_CMD_0           0
 409 #define R300_ZB_OFFSET          1
 410 #define R300_ZB_PITCH           2
 411 #define R300_ZB_CMDSIZE         3
 412
 413 #define R300_VPI_CMD_0          0
 414 #define R300_VPI_INSTR_0        1
 415 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 416
 417 #define R300_VPP_CMD_0          0
 418 #define R300_VPP_PARAM_0        1
 419 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 420
 421 #define R300_VPS_CMD_0          0
 422 #define R300_VPS_ZERO_0         1
 423 #define R300_VPS_ZERO_1         2
 424 #define R300_VPS_POINTSIZE      3
 425 #define R300_VPS_ZERO_3         4
 426 #define R300_VPS_CMDSIZE        5
 427
 428         /* the layout is common for all fields inside tex */
 429 #define R300_TEX_CMD_0          0
 430 #define R300_TEX_VALUE_0        1
 431 /* We don't really use this, instead specify mtu+1 dynamically
 432 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 433 */
 434
 435 /**
 436  * Cache for hardware register state.
 437  */
 438 struct r300_hw_state {
 439         struct r300_state_atom atomlist;
 440
 441         GLboolean is_dirty;
 442         GLboolean all_dirty;
 443         int max_state_size;     /* in dwords */
 444
 445         struct r300_state_atom vpt;     /* viewport (1D98) */
 446         struct r300_state_atom vap_cntl;
 447         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 448         struct r300_state_atom vte;     /* (20B0) */
 449         struct r300_state_atom unk2134; /* (2134) */
 450         struct r300_state_atom vap_cntl_status;
 451         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 452         struct r300_state_atom vic;     /* vap input control (2180) */
 453         struct r300_state_atom unk21DC; /* (21DC) */
 454         struct r300_state_atom unk221C; /* (221C) */
 455         struct r300_state_atom vap_clip;
 456         struct r300_state_atom unk2288; /* (2288) */
 457         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 458         struct r300_state_atom gb_enable;       /* (4008) */
 459         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 460         struct r300_state_atom unk4200; /* (4200) */
 461         struct r300_state_atom unk4214; /* (4214) */
 462         struct r300_state_atom ps;      /* pointsize (421C) */
 463         struct r300_state_atom unk4230; /* (4230) */
 464         struct r300_state_atom lcntl;   /* line control */
 465         struct r300_state_atom unk4260; /* (4260) */
 466         struct r300_state_atom shade;
 467         struct r300_state_atom polygon_mode;
 468         struct r300_state_atom fogp;    /* fog parameters (4294) */
 469         struct r300_state_atom unk429C; /* (429C) */
 470         struct r300_state_atom zbias_cntl;
 471         struct r300_state_atom zbs;     /* zbias (42A4) */
 472         struct r300_state_atom occlusion_cntl;
 473         struct r300_state_atom cul;     /* cull cntl (42B8) */
 474         struct r300_state_atom unk42C0; /* (42C0) */
 475         struct r300_state_atom rc;      /* rs control (4300) */
 476         struct r300_state_atom ri;      /* rs interpolators (4310) */
 477         struct r300_state_atom rr;      /* rs route (4330) */
 478         struct r300_state_atom unk43A4; /* (43A4) */
 479         struct r300_state_atom unk43E8; /* (43E8) */
 480         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 481         struct r300_state_atom fpt;     /* texi - (4620) */
 482         struct r300_state_atom unk46A4; /* (46A4) */
 483         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 484         struct r300_state_atom fogs;    /* fog state (4BC0) */
 485         struct r300_state_atom fogc;    /* fog color (4BC8) */
 486         struct r300_state_atom at;      /* alpha test (4BD4) */
 487         struct r300_state_atom unk4BD8; /* (4BD8) */
 488         struct r300_state_atom fpp;     /* 0x4C00 and following */
 489         struct r300_state_atom unk4E00; /* (4E00) */
 490         struct r300_state_atom bld;     /* blending (4E04) */
 491         struct r300_state_atom cmk;     /* colormask (4E0C) */
 492         struct r300_state_atom blend_color;     /* constant blend color */
 493         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 494         struct r300_state_atom unk4E50; /* (4E50) */
 495         struct r300_state_atom unk4E88; /* (4E88) */
 496         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 497         struct r300_state_atom zs;      /* zstencil control (4F00) */
 498         struct r300_state_atom zstencil_format;
 499         struct r300_state_atom zb;      /* z buffer (4F20) */
 500         struct r300_state_atom unk4F28; /* (4F28) */
 501         struct r300_state_atom unk4F30; /* (4F30) */
 502         struct r300_state_atom unk4F44; /* (4F44) */
 503         struct r300_state_atom unk4F54; /* (4F54) */
 504
 505         struct r300_state_atom vpi;     /* vp instructions */
 506         struct r300_state_atom vpp;     /* vp parameters */
 507         struct r300_state_atom vps;     /* vertex point size (?) */
 508         /* 8 texture units */
 509         /* the state is grouped by function and not by
 510            texture unit. This makes single unit updates
 511            really awkward - we are much better off
 512            updating the whole thing at once */
 513         struct {
 514                 struct r300_state_atom filter;
 515                 struct r300_state_atom filter_1;
 516                 struct r300_state_atom size;
 517                 struct r300_state_atom format;
 518                 struct r300_state_atom pitch;
 519                 struct r300_state_atom offset;
 520                 struct r300_state_atom chroma_key;
 521                 struct r300_state_atom border_color;
 522         } tex;
 523         struct r300_state_atom txe;     /* tex enable (4104) */
 524 };
 525
 526 /**
 527  * This structure holds the command buffer while it is being constructed.
 528  *
 529  * The first batch of commands in the buffer is always the state that needs
 530  * to be re-emitted when the context is lost. This batch can be skipped
 531  * otherwise.
 532  */
 533 struct r300_cmdbuf {
 534         int size;               /* DWORDs allocated for buffer */
 535         uint32_t *cmd_buf;
 536         int count_used;         /* DWORDs filled so far */
 537         int count_reemit;       /* size of re-emission batch */
 538 };
 539
 540 /**
 541  * State cache
 542  */
 543
 544 struct r300_depthbuffer_state {
 545         GLfloat scale;
 546 };
 547
 548 struct r300_stencilbuffer_state {
 549         GLuint clear;
 550         GLboolean hw_stencil;
 551
 552 };
 553
 554 /* Vertex shader state */
 555
 556 /* Perhaps more if we store programs in vmem? */
 557 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 558 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 559
 560 /* Can be tested with colormat currently. */
 561 #define VSF_MAX_FRAGMENT_TEMPS (14)
 562
 563 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 564 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 565
 566 struct r300_vertex_shader_fragment {
 567         int length;
 568         union {
 569                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 570                 float f[VSF_MAX_FRAGMENT_LENGTH];
 571                 struct r300_vertprog_instruction i[VSF_MAX_FRAGMENT_LENGTH / 4];
 572         } body;
 573 };
 574
 575 struct r300_vertex_shader_state {
 576         struct r300_vertex_shader_fragment program;
 577 };
 578
 579 extern int hw_tcl_on;
 580
 581 #define COLOR_IS_RGBA
 582 #define TAG(x) r300##x
 583 #include "tnl_dd/t_dd_vertex.h"
 584 #undef TAG
 585
 586 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 587 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 588
 589 /* Should but doesnt work */
 590 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 591
 592 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 593  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 594  */
 595
 596 struct r300_vertex_program_key {
 597         GLuint InputsRead;
 598         GLuint OutputsWritten;
 599 };
 600
 601 struct r300_vertex_program {
 602         struct r300_vertex_program *next;
 603         struct r300_vertex_program_key key;
 604         int translated;
 605
 606         struct r300_vertex_shader_fragment program;
 607
 608         int pos_end;
 609         int num_temporaries;    /* Number of temp vars used by program */
 610         int wpos_idx;
 611         int inputs[VERT_ATTRIB_MAX];
 612         int outputs[VERT_RESULT_MAX];
 613         int native;
 614         int ref_count;
 615         int use_ref_count;
 616 };
 617
 618 struct r300_vertex_program_cont {
 619         struct gl_vertex_program mesa_program;  /* Must be first */
 620         struct r300_vertex_shader_fragment params;
 621         struct r300_vertex_program *progs;
 622 };
 623
 624 #define PFS_MAX_ALU_INST        64
 625 #define PFS_MAX_TEX_INST        64
 626 #define PFS_MAX_TEX_INDIRECT 4
 627 #define PFS_NUM_TEMP_REGS       32
 628 #define PFS_NUM_CONST_REGS      16
 629
 630 /* Mapping Mesa registers to R300 temporaries */
 631 struct reg_acc {
 632         int reg;                /* Assigned hw temp */
 633         unsigned int refcount;  /* Number of uses by mesa program */
 634 };
 635
 636 /**
 637  * Describe the current lifetime information for an R300 temporary
 638  */
 639 struct reg_lifetime {
 640         /* Index of the first slot where this register is free in the sense
 641            that it can be used as a new destination register.
 642            This is -1 if the register has been assigned to a Mesa register
 643            and the last access to the register has not yet been emitted */
 644         int free;
 645
 646         /* Index of the first slot where this register is currently reserved.
 647            This is used to stop e.g. a scalar operation from being moved
 648            before the allocation time of a register that was first allocated
 649            for a vector operation. */
 650         int reserved;
 651
 652         /* Index of the first slot in which the register can be used as a
 653            source without losing the value that is written by the last
 654            emitted instruction that writes to the register */
 655         int vector_valid;
 656         int scalar_valid;
 657
 658         /* Index to the slot where the register was last read.
 659            This is also the first slot in which the register may be written again */
 660         int vector_lastread;
 661         int scalar_lastread;
 662 };
 663
 664 /**
 665  * Store usage information about an ALU instruction slot during the
 666  * compilation of a fragment program.
 667  */
 668 #define SLOT_SRC_VECTOR  (1<<0)
 669 #define SLOT_SRC_SCALAR  (1<<3)
 670 #define SLOT_SRC_BOTH    (SLOT_SRC_VECTOR | SLOT_SRC_SCALAR)
 671 #define SLOT_OP_VECTOR   (1<<16)
 672 #define SLOT_OP_SCALAR   (1<<17)
 673 #define SLOT_OP_BOTH     (SLOT_OP_VECTOR | SLOT_OP_SCALAR)
 674
 675 struct r300_pfs_compile_slot {
 676         /* Bitmask indicating which parts of the slot are used, using SLOT_ constants
 677            defined above */
 678         unsigned int used;
 679
 680         /* Selected sources */
 681         int vsrc[3];
 682         int ssrc[3];
 683 };
 684
 685 /**
 686  * Store information during compilation of fragment programs.
 687  */
 688 struct r300_pfs_compile_state {
 689         int nrslots;            /* number of ALU slots used so far */
 690
 691         /* Track which (parts of) slots are already filled with instructions */
 692         struct r300_pfs_compile_slot slot[PFS_MAX_ALU_INST];
 693
 694         /* Track the validity of R300 temporaries */
 695         struct reg_lifetime hwtemps[PFS_NUM_TEMP_REGS];
 696
 697         /* Used to map Mesa's inputs/temps onto hardware temps */
 698         int temp_in_use;
 699         struct reg_acc temps[PFS_NUM_TEMP_REGS];
 700         struct reg_acc inputs[32];      /* don't actually need 32... */
 701
 702         /* Track usage of hardware temps, for register allocation,
 703          * indirection detection, etc. */
 704         GLuint used_in_node;
 705         GLuint dest_in_node;
 706 };
 707
 708 /**
 709  * Store everything about a fragment program that is needed
 710  * to render with that program.
 711  */
 712 struct r300_fragment_program {
 713         struct gl_fragment_program mesa_program;
 714
 715         GLcontext *ctx;
 716         GLboolean translated;
 717         GLboolean error;
 718         struct r300_pfs_compile_state *cs;
 719
 720         struct {
 721                 int length;
 722                 GLuint inst[PFS_MAX_TEX_INST];
 723         } tex;
 724
 725         struct {
 726                 struct {
 727                         GLuint inst0;
 728                         GLuint inst1;
 729                         GLuint inst2;
 730                         GLuint inst3;
 731                 } inst[PFS_MAX_ALU_INST];
 732         } alu;
 733
 734         struct {
 735                 int tex_offset;
 736                 int tex_end;
 737                 int alu_offset;
 738                 int alu_end;
 739                 int flags;
 740         } node[4];
 741         int cur_node;
 742         int first_node_has_tex;
 743
 744         int alu_offset;
 745         int alu_end;
 746         int tex_offset;
 747         int tex_end;
 748
 749         /* Hardware constants.
 750          * Contains a pointer to the value. The destination of the pointer
 751          * is supposed to be updated when GL state changes.
 752          * Typically, this is either a pointer into
 753          * gl_program_parameter_list::ParameterValues, or a pointer to a
 754          * global constant (e.g. for sin/cos-approximation)
 755          */
 756         const GLfloat *constant[PFS_NUM_CONST_REGS];
 757         int const_nr;
 758
 759         int max_temp_idx;
 760
 761         GLuint optimization;
 762 };
 763
 764 #define R300_MAX_AOS_ARRAYS             16
 765
 766 #define REG_COORDS      0
 767 #define REG_COLOR0      1
 768 #define REG_TEX0        2
 769
 770 struct r300_state {
 771         struct r300_depthbuffer_state depth;
 772         struct r300_texture_state texture;
 773         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 774         struct r300_vertex_shader_state vertex_shader;
 775         struct r300_pfs_compile_state pfs_compile;
 776         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 777         int aos_count;
 778
 779         GLuint *Elts;
 780         struct r300_dma_region elt_dma;
 781
 782         struct r300_dma_region swtcl_dma;
 783         DECLARE_RENDERINPUTS(render_inputs_bitset);     /* actual render inputs that R300 was configured for.
 784                                                            They are the same as tnl->render_inputs for fixed pipeline */
 785
 786         struct r300_stencilbuffer_state stencil;
 787
 788 };
 789
 790 #define R300_FALLBACK_NONE 0
 791 #define R300_FALLBACK_TCL 1
 792 #define R300_FALLBACK_RAST 2
 793
 794 /* r300_swtcl.c
 795  */
 796 struct r300_swtcl_info {
 797    GLuint RenderIndex;
 798
 799    /**
 800     * Size of a hardware vertex.  This is calculated when \c ::vertex_attrs is
 801     * installed in the Mesa state vector.
 802     */
 803    GLuint vertex_size;
 804
 805    /**
 806     * Attributes instructing the Mesa TCL pipeline where / how to put vertex
 807     * data in the hardware buffer.
 808     */
 809    struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 810
 811    /**
 812     * Number of elements of \c ::vertex_attrs that are actually used.
 813     */
 814    GLuint vertex_attr_count;
 815
 816    /**
 817     * Cached pointer to the buffer where Mesa will store vertex data.
 818     */
 819    GLubyte *verts;
 820
 821    /* Fallback rasterization functions
 822     */
 823   //   r200_point_func draw_point;
 824   //   r200_line_func draw_line;
 825   //   r200_tri_func draw_tri;
 826
 827    GLuint hw_primitive;
 828    GLenum render_primitive;
 829    GLuint numverts;
 830
 831    /**
 832     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 833     */
 834    GLuint coloroffset;
 835
 836    /**
 837     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 838     */
 839    GLuint specoffset;
 840
 841    /**
 842     * Should Mesa project vertex data or will the hardware do it?
 843     */
 844    GLboolean needproj;
 845
 846    struct r300_dma_region indexed_verts;
 847 };
 848
 849
 850 /**
 851  * \brief R300 context structure.
 852  */
 853 struct r300_context {
 854         struct radeon_context radeon;   /* parent class, must be first */
 855
 856         struct r300_hw_state hw;
 857         struct r300_cmdbuf cmdbuf;
 858         struct r300_state state;
 859         struct gl_vertex_program *curr_vp;
 860         struct r300_vertex_program *selected_vp;
 861
 862         /* Vertex buffers
 863          */
 864         struct r300_dma dma;
 865         GLboolean save_on_next_unlock;
 866         GLuint NewGLState;
 867
 868         /* Texture object bookkeeping
 869          */
 870         unsigned nr_heaps;
 871         driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
 872         driTextureObject swapped;
 873         int texture_depth;
 874         float initialMaxAnisotropy;
 875
 876         /* Clientdata textures;
 877          */
 878         GLuint prefer_gart_client_texturing;
 879
 880 #ifdef USER_BUFFERS
 881         struct r300_memory_manager *rmm;
 882 #endif
 883
 884         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 885         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 886
 887         GLboolean disable_lowimpact_fallback;
 888
 889         DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
 890         struct r300_swtcl_info swtcl;
 891 };
 892
 893 struct r300_buffer_object {
 894         struct gl_buffer_object mesa_obj;
 895         int id;
 896 };
 897
 898 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 899
 900 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 901 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 902                                    __DRIcontextPrivate * driContextPriv,
 903                                    void *sharedContextPrivate);
 904
 905 extern void r300SelectVertexShader(r300ContextPtr r300);
 906 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 907 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 908                                       struct r300_vertex_program_cont *vp,
 909                                       float *dst);
 910
 911 #define RADEON_D_CAPTURE 0
 912 #define RADEON_D_PLAYBACK 1
 913 #define RADEON_D_PLAYBACK_RAW 2
 914 #define RADEON_D_T 3
 915
 916 #endif                          /* __R300_CONTEXT_H__ */