src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "radeon_common.h"
  44
  45 #include "main/mtypes.h"
  46
  47 struct r300_context;
  48 typedef struct r300_context r300ContextRec;
  49 typedef struct r300_context *r300ContextPtr;
  50
  51
  52 /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  53    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  54    with other compilers ... GLUE!
  55 */
  56 #define WARN_ONCE(a, ...)       { \
  57         static int warn##__LINE__=1; \
  58         if(warn##__LINE__){ \
  59                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  60                 fprintf(stderr, "File %s function %s line %d\n", \
  61                         __FILE__, __FUNCTION__, __LINE__); \
  62                 fprintf(stderr,  a, ## __VA_ARGS__);\
  63                 fprintf(stderr, "***************************************************************************\n"); \
  64                 warn##__LINE__=0;\
  65                 } \
  66         }
  67
  68 #include "r300_vertprog.h"
  69 #include "r500_fragprog.h"
  70
  71
  72
  73 /* The blit width for texture uploads
  74  */
  75 #define R300_BLIT_WIDTH_BYTES 1024
  76 #define R300_MAX_TEXTURE_UNITS 8
  77
  78
  79
  80 #define R300_VPT_CMD_0          0
  81 #define R300_VPT_XSCALE         1
  82 #define R300_VPT_XOFFSET        2
  83 #define R300_VPT_YSCALE         3
  84 #define R300_VPT_YOFFSET        4
  85 #define R300_VPT_ZSCALE         5
  86 #define R300_VPT_ZOFFSET        6
  87 #define R300_VPT_CMDSIZE        7
  88
  89 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
  90 #define R300_VIR_CNTL_0         1
  91 #define R300_VIR_CNTL_1         2
  92 #define R300_VIR_CNTL_2         3
  93 #define R300_VIR_CNTL_3         4
  94 #define R300_VIR_CNTL_4         5
  95 #define R300_VIR_CNTL_5         6
  96 #define R300_VIR_CNTL_6         7
  97 #define R300_VIR_CNTL_7         8
  98 #define R300_VIR_CMDSIZE        9
  99
 100 #define R300_VIC_CMD_0          0
 101 #define R300_VIC_CNTL_0         1
 102 #define R300_VIC_CNTL_1         2
 103 #define R300_VIC_CMDSIZE        3
 104
 105 #define R300_VOF_CMD_0          0
 106 #define R300_VOF_CNTL_0         1
 107 #define R300_VOF_CNTL_1         2
 108 #define R300_VOF_CMDSIZE        3
 109
 110 #define R300_PVS_CMD_0          0
 111 #define R300_PVS_CNTL_1         1
 112 #define R300_PVS_CNTL_2         2
 113 #define R300_PVS_CNTL_3         3
 114 #define R300_PVS_CMDSIZE        4
 115
 116 #define R300_GB_MISC_CMD_0              0
 117 #define R300_GB_MISC_MSPOS_0            1
 118 #define R300_GB_MISC_MSPOS_1            2
 119 #define R300_GB_MISC_TILE_CONFIG        3
 120 #define R300_GB_MISC_SELECT             4
 121 #define R300_GB_MISC_AA_CONFIG          5
 122 #define R300_GB_MISC_CMDSIZE            6
 123
 124 #define R300_TXE_CMD_0          0
 125 #define R300_TXE_ENABLE         1
 126 #define R300_TXE_CMDSIZE        2
 127
 128 #define R300_PS_CMD_0           0
 129 #define R300_PS_POINTSIZE       1
 130 #define R300_PS_CMDSIZE         2
 131
 132 #define R300_ZBS_CMD_0          0
 133 #define R300_ZBS_T_FACTOR       1
 134 #define R300_ZBS_T_CONSTANT     2
 135 #define R300_ZBS_W_FACTOR       3
 136 #define R300_ZBS_W_CONSTANT     4
 137 #define R300_ZBS_CMDSIZE        5
 138
 139 #define R300_CUL_CMD_0          0
 140 #define R300_CUL_CULL           1
 141 #define R300_CUL_CMDSIZE        2
 142
 143 #define R300_RC_CMD_0           0
 144 #define R300_RC_CNTL_0          1
 145 #define R300_RC_CNTL_1          2
 146 #define R300_RC_CMDSIZE         3
 147
 148 #define R300_RI_CMD_0           0
 149 #define R300_RI_INTERP_0        1
 150 #define R300_RI_INTERP_1        2
 151 #define R300_RI_INTERP_2        3
 152 #define R300_RI_INTERP_3        4
 153 #define R300_RI_INTERP_4        5
 154 #define R300_RI_INTERP_5        6
 155 #define R300_RI_INTERP_6        7
 156 #define R300_RI_INTERP_7        8
 157 #define R300_RI_CMDSIZE         9
 158
 159 #define R500_RI_CMDSIZE        17
 160
 161 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 162 #define R300_RR_INST_0          1
 163 #define R300_RR_INST_1          2
 164 #define R300_RR_INST_2          3
 165 #define R300_RR_INST_3          4
 166 #define R300_RR_INST_4          5
 167 #define R300_RR_INST_5          6
 168 #define R300_RR_INST_6          7
 169 #define R300_RR_INST_7          8
 170 #define R300_RR_CMDSIZE         9
 171
 172 #define R300_FP_CMD_0           0
 173 #define R300_FP_CNTL0           1
 174 #define R300_FP_CNTL1           2
 175 #define R300_FP_CNTL2           3
 176 #define R300_FP_CMD_1           4
 177 #define R300_FP_NODE0           5
 178 #define R300_FP_NODE1           6
 179 #define R300_FP_NODE2           7
 180 #define R300_FP_NODE3           8
 181 #define R300_FP_CMDSIZE         9
 182
 183 #define R500_FP_CMD_0           0
 184 #define R500_FP_CNTL            1
 185 #define R500_FP_PIXSIZE         2
 186 #define R500_FP_CMD_1           3
 187 #define R500_FP_CODE_ADDR       4
 188 #define R500_FP_CODE_RANGE      5
 189 #define R500_FP_CODE_OFFSET     6
 190 #define R500_FP_CMD_2           7
 191 #define R500_FP_FC_CNTL         8
 192 #define R500_FP_CMDSIZE         9
 193
 194 #define R300_FPT_CMD_0          0
 195 #define R300_FPT_INSTR_0        1
 196 #define R300_FPT_CMDSIZE        65
 197
 198 #define R300_FPI_CMD_0          0
 199 #define R300_FPI_INSTR_0        1
 200 #define R300_FPI_CMDSIZE        65
 201 /* R500 has space for 512 instructions - 6 dwords per instruction */
 202 #define R500_FPI_CMDSIZE        (512*6+1)
 203
 204 #define R300_FPP_CMD_0          0
 205 #define R300_FPP_PARAM_0        1
 206 #define R300_FPP_CMDSIZE        (32*4+1)
 207 /* R500 has spcae for 256 constants - 4 dwords per constant */
 208 #define R500_FPP_CMDSIZE        (256*4+1)
 209
 210 #define R300_FOGS_CMD_0         0
 211 #define R300_FOGS_STATE         1
 212 #define R300_FOGS_CMDSIZE       2
 213
 214 #define R300_FOGC_CMD_0         0
 215 #define R300_FOGC_R             1
 216 #define R300_FOGC_G             2
 217 #define R300_FOGC_B             3
 218 #define R300_FOGC_CMDSIZE       4
 219
 220 #define R300_FOGP_CMD_0         0
 221 #define R300_FOGP_SCALE         1
 222 #define R300_FOGP_START         2
 223 #define R300_FOGP_CMDSIZE       3
 224
 225 #define R300_AT_CMD_0           0
 226 #define R300_AT_ALPHA_TEST      1
 227 #define R300_AT_UNKNOWN         2
 228 #define R300_AT_CMDSIZE         3
 229
 230 #define R300_BLD_CMD_0          0
 231 #define R300_BLD_CBLEND         1
 232 #define R300_BLD_ABLEND         2
 233 #define R300_BLD_CMDSIZE        3
 234
 235 #define R300_CMK_CMD_0          0
 236 #define R300_CMK_COLORMASK      1
 237 #define R300_CMK_CMDSIZE        2
 238
 239 #define R300_CB_CMD_0           0
 240 #define R300_CB_OFFSET          1
 241 #define R300_CB_CMD_1           2
 242 #define R300_CB_PITCH           3
 243 #define R300_CB_CMDSIZE         4
 244
 245 #define R300_ZS_CMD_0           0
 246 #define R300_ZS_CNTL_0          1
 247 #define R300_ZS_CNTL_1          2
 248 #define R300_ZS_CNTL_2          3
 249 #define R300_ZS_CMDSIZE         4
 250
 251 #define R300_ZB_CMD_0           0
 252 #define R300_ZB_OFFSET          1
 253 #define R300_ZB_PITCH           2
 254 #define R300_ZB_CMDSIZE         3
 255
 256 #define R300_VAP_CNTL_FLUSH     0
 257 #define R300_VAP_CNTL_FLUSH_1   1
 258 #define R300_VAP_CNTL_CMD       2
 259 #define R300_VAP_CNTL_INSTR     3
 260 #define R300_VAP_CNTL_SIZE      4
 261
 262 #define R300_VPI_CMD_0          0
 263 #define R300_VPI_INSTR_0        1
 264 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 265
 266 #define R300_VPP_CMD_0          0
 267 #define R300_VPP_PARAM_0        1
 268 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 269
 270 #define R300_VPUCP_CMD_0                0
 271 #define R300_VPUCP_X            1
 272 #define R300_VPUCP_Y            2
 273 #define R300_VPUCP_Z            3
 274 #define R300_VPUCP_W            4
 275 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 276
 277 #define R300_VPS_CMD_0          0
 278 #define R300_VPS_ZERO_0         1
 279 #define R300_VPS_ZERO_1         2
 280 #define R300_VPS_POINTSIZE      3
 281 #define R300_VPS_ZERO_3         4
 282 #define R300_VPS_CMDSIZE        5
 283
 284         /* the layout is common for all fields inside tex */
 285 #define R300_TEX_CMD_0          0
 286 #define R300_TEX_VALUE_0        1
 287 /* We don't really use this, instead specify mtu+1 dynamically
 288 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 289 */
 290
 291 /**
 292  * Cache for hardware register state.
 293  */
 294 struct r300_hw_state {
 295         struct radeon_state_atom vpt;   /* viewport (1D98) */
 296         struct radeon_state_atom vap_cntl;
 297         struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
 298         struct radeon_state_atom vof;   /* VAP output format register 0x2090 */
 299         struct radeon_state_atom vte;   /* (20B0) */
 300         struct radeon_state_atom vap_vf_max_vtx_indx;   /* Maximum Vertex Indx Clamp (2134) */
 301         struct radeon_state_atom vap_cntl_status;
 302         struct radeon_state_atom vir[2];        /* vap input route (2150/21E0) */
 303         struct radeon_state_atom vic;   /* vap input control (2180) */
 304         struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 305         struct radeon_state_atom vap_clip_cntl;
 306         struct radeon_state_atom vap_clip;
 307         struct radeon_state_atom vap_pvs_vtx_timeout_reg;       /* Vertex timeout register (2288) */
 308         struct radeon_state_atom pvs;   /* pvs_cntl (22D0) */
 309         struct radeon_state_atom gb_enable;     /* (4008) */
 310         struct radeon_state_atom gb_misc;       /* Multisampling position shifts ? (4010) */
 311         struct radeon_state_atom ga_point_s0;   /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 312         struct radeon_state_atom ga_triangle_stipple;   /* (4214) */
 313         struct radeon_state_atom ps;    /* pointsize (421C) */
 314         struct radeon_state_atom ga_point_minmax;       /* (4230) */
 315         struct radeon_state_atom lcntl; /* line control */
 316         struct radeon_state_atom ga_line_stipple;       /* (4260) */
 317         struct radeon_state_atom shade;
 318         struct radeon_state_atom polygon_mode;
 319         struct radeon_state_atom fogp;  /* fog parameters (4294) */
 320         struct radeon_state_atom ga_soft_reset; /* (429C) */
 321         struct radeon_state_atom zbias_cntl;
 322         struct radeon_state_atom zbs;   /* zbias (42A4) */
 323         struct radeon_state_atom occlusion_cntl;
 324         struct radeon_state_atom cul;   /* cull cntl (42B8) */
 325         struct radeon_state_atom su_depth_scale;        /* (42C0) */
 326         struct radeon_state_atom rc;    /* rs control (4300) */
 327         struct radeon_state_atom ri;    /* rs interpolators (4310) */
 328         struct radeon_state_atom rr;    /* rs route (4330) */
 329         struct radeon_state_atom sc_hyperz;     /* (43A4) */
 330         struct radeon_state_atom sc_screendoor; /* (43E8) */
 331         struct radeon_state_atom fp;    /* fragment program cntl + nodes (4600) */
 332         struct radeon_state_atom fpt;   /* texi - (4620) */
 333         struct radeon_state_atom us_out_fmt;    /* (46A4) */
 334         struct radeon_state_atom r500fp;        /* r500 fp instructions */
 335         struct radeon_state_atom r500fp_const;  /* r500 fp constants */
 336         struct radeon_state_atom fpi[4];        /* fp instructions (46C0/47C0/48C0/49C0) */
 337         struct radeon_state_atom fogs;  /* fog state (4BC0) */
 338         struct radeon_state_atom fogc;  /* fog color (4BC8) */
 339         struct radeon_state_atom at;    /* alpha test (4BD4) */
 340         struct radeon_state_atom fg_depth_src;  /* (4BD8) */
 341         struct radeon_state_atom fpp;   /* 0x4C00 and following */
 342         struct radeon_state_atom rb3d_cctl;     /* (4E00) */
 343         struct radeon_state_atom bld;   /* blending (4E04) */
 344         struct radeon_state_atom cmk;   /* colormask (4E0C) */
 345         struct radeon_state_atom blend_color;   /* constant blend color */
 346         struct radeon_state_atom rop;   /* ropcntl */
 347         struct radeon_state_atom cb;    /* colorbuffer (4E28) */
 348         struct radeon_state_atom rb3d_dither_ctl;       /* (4E50) */
 349         struct radeon_state_atom rb3d_aaresolve_ctl;    /* (4E88) */
 350         struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold;  /* (4E88) I saw it only written on RV350 hardware..  */
 351         struct radeon_state_atom zs;    /* zstencil control (4F00) */
 352         struct radeon_state_atom zstencil_format;
 353         struct radeon_state_atom zb;    /* z buffer (4F20) */
 354         struct radeon_state_atom zb_depthclearvalue;    /* (4F28) */
 355         struct radeon_state_atom unk4F30;       /* (4F30) */
 356         struct radeon_state_atom zb_hiz_offset; /* (4F44) */
 357         struct radeon_state_atom zb_hiz_pitch;  /* (4F54) */
 358
 359         struct radeon_state_atom vpi;   /* vp instructions */
 360         struct radeon_state_atom vpp;   /* vp parameters */
 361         struct radeon_state_atom vps;   /* vertex point size (?) */
 362         struct radeon_state_atom vpucp[6];      /* vp user clip plane - 6 */
 363         /* 8 texture units */
 364         /* the state is grouped by function and not by
 365            texture unit. This makes single unit updates
 366            really awkward - we are much better off
 367            updating the whole thing at once */
 368         struct {
 369                 struct radeon_state_atom filter;
 370                 struct radeon_state_atom filter_1;
 371                 struct radeon_state_atom size;
 372                 struct radeon_state_atom format;
 373                 struct radeon_state_atom pitch;
 374                 struct radeon_state_atom offset;
 375                 struct radeon_state_atom chroma_key;
 376                 struct radeon_state_atom border_color;
 377         } tex;
 378         struct radeon_state_atom txe;   /* tex enable (4104) */
 379
 380         radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
 381 };
 382
 383 /**
 384  * State cache
 385  */
 386
 387 /* Vertex shader state */
 388
 389 /* Perhaps more if we store programs in vmem? */
 390 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 391 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 392
 393 /* Can be tested with colormat currently. */
 394 #define VSF_MAX_FRAGMENT_TEMPS (14)
 395
 396 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 397 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 398
 399 struct r300_vertex_shader_fragment {
 400         int length;
 401         union {
 402                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 403                 float f[VSF_MAX_FRAGMENT_LENGTH];
 404                 GLuint i[VSF_MAX_FRAGMENT_LENGTH];
 405         } body;
 406 };
 407
 408 struct r300_vertex_shader_state {
 409         struct r300_vertex_shader_fragment program;
 410 };
 411
 412 extern int hw_tcl_on;
 413
 414 #define COLOR_IS_RGBA
 415 #define TAG(x) r300##x
 416 #include "tnl_dd/t_dd_vertex.h"
 417 #undef TAG
 418
 419 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 420
 421 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 422  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 423  */
 424
 425 struct r300_vertex_program_key {
 426         GLuint InputsRead;
 427         GLuint OutputsWritten;
 428         GLuint OutputsAdded;
 429 };
 430
 431 struct r300_vertex_program {
 432         struct r300_vertex_program *next;
 433         struct r300_vertex_program_key key;
 434         int translated;
 435
 436         struct r300_vertex_shader_fragment program;
 437
 438         int pos_end;
 439         int num_temporaries;    /* Number of temp vars used by program */
 440         int wpos_idx;
 441         int inputs[VERT_ATTRIB_MAX];
 442         int outputs[VERT_RESULT_MAX];
 443         int native;
 444         int ref_count;
 445         int use_ref_count;
 446 };
 447
 448 struct r300_vertex_program_cont {
 449         struct gl_vertex_program mesa_program;  /* Must be first */
 450         struct r300_vertex_shader_fragment params;
 451         struct r300_vertex_program *progs;
 452 };
 453
 454 #define PFS_MAX_ALU_INST        64
 455 #define PFS_MAX_TEX_INST        64
 456 #define PFS_MAX_TEX_INDIRECT 4
 457 #define PFS_NUM_TEMP_REGS       32
 458 #define PFS_NUM_CONST_REGS      16
 459
 460 struct r300_pfs_compile_state;
 461 struct r500_pfs_compile_state;
 462
 463 /**
 464  * Stores state that influences the compilation of a fragment program.
 465  */
 466 struct r300_fragment_program_external_state {
 467         struct {
 468                 /**
 469                  * If the sampler is used as a shadow sampler,
 470                  * this field is:
 471                  *  0 - GL_LUMINANCE
 472                  *  1 - GL_INTENSITY
 473                  *  2 - GL_ALPHA
 474                  * depending on the depth texture mode.
 475                  */
 476                 GLuint depth_texture_mode : 2;
 477
 478                 /**
 479                  * If the sampler is used as a shadow sampler,
 480                  * this field is (texture_compare_func - GL_NEVER).
 481                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 482                  *
 483                  * Otherwise, this field is 0.
 484                  */
 485                 GLuint texture_compare_func : 3;
 486         } unit[16];
 487 };
 488
 489
 490 struct r300_fragment_program_node {
 491         int tex_offset; /**< first tex instruction */
 492         int tex_end; /**< last tex instruction, relative to tex_offset */
 493         int alu_offset; /**< first ALU instruction */
 494         int alu_end; /**< last ALU instruction, relative to alu_offset */
 495         int flags;
 496 };
 497
 498 /**
 499  * Stores an R300 fragment program in its compiled-to-hardware form.
 500  */
 501 struct r300_fragment_program_code {
 502         struct {
 503                 int length; /**< total # of texture instructions used */
 504                 GLuint inst[PFS_MAX_TEX_INST];
 505         } tex;
 506
 507         struct {
 508                 int length; /**< total # of ALU instructions used */
 509                 struct {
 510                         GLuint inst0;
 511                         GLuint inst1;
 512                         GLuint inst2;
 513                         GLuint inst3;
 514                 } inst[PFS_MAX_ALU_INST];
 515         } alu;
 516
 517         struct r300_fragment_program_node node[4];
 518         int cur_node;
 519         int first_node_has_tex;
 520
 521         /**
 522          * Remember which program register a given hardware constant
 523          * belongs to.
 524          */
 525         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 526         int const_nr;
 527
 528         int max_temp_idx;
 529 };
 530
 531
 532 struct r500_fragment_program_code {
 533         struct {
 534                 GLuint inst0;
 535                 GLuint inst1;
 536                 GLuint inst2;
 537                 GLuint inst3;
 538                 GLuint inst4;
 539                 GLuint inst5;
 540         } inst[512];
 541
 542         int inst_offset;
 543         int inst_end;
 544
 545         /**
 546          * Remember which program register a given hardware constant
 547          * belongs to.
 548          */
 549         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 550         int const_nr;
 551
 552         int max_temp_idx;
 553 };
 554
 555 /**
 556 * Store everything about a fragment program that is needed
 557 * to render with that program.
 558 */
 559 struct r300_fragment_program {
 560         struct gl_fragment_program Base;
 561
 562         GLboolean translated;
 563         GLboolean error;
 564
 565         struct r300_fragment_program_external_state state;
 566         union {
 567                 struct r300_fragment_program_code r300;
 568                 struct r500_fragment_program_code r500;
 569         } code;
 570
 571         GLboolean writes_depth;
 572         GLuint optimization;
 573 };
 574
 575 #define R300_MAX_AOS_ARRAYS             16
 576
 577
 578 #define R300_FALLBACK_NONE 0
 579 #define R300_FALLBACK_TCL 1
 580 #define R300_FALLBACK_RAST 2
 581
 582 /* r300_swtcl.c
 583  */
 584 struct r300_swtcl_info {
 585   /*
 586     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 587     */
 588    GLuint coloroffset;
 589
 590    /**
 591     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 592     */
 593    GLuint specoffset;
 594
 595    struct vertex_attribute{
 596        GLuint attr;
 597        GLubyte format;
 598        GLubyte dst_loc;
 599        GLuint swizzle;
 600        GLubyte write_mask;
 601    } vert_attrs[VERT_ATTRIB_MAX];
 602
 603    GLubyte vertex_attr_count;
 604
 605    int sw_tcl_inputs[VERT_ATTRIB_MAX];
 606 };
 607
 608 struct r300_vtable {
 609         void (* SetupRSUnit)(GLcontext *ctx);
 610         void (* SetupFragmentShaderTextures)(GLcontext *ctx, int *tmu_mappings);
 611         void ( *TranslateFragmentShader)(GLcontext *ctx, struct gl_fragment_program *fp);
 612         GLboolean (* SetupPixelShader)(GLcontext *ctx);
 613 };
 614
 615
 616 /**
 617  * \brief R300 context structure.
 618  */
 619 struct r300_context {
 620         struct radeon_context radeon;   /* parent class, must be first */
 621
 622         struct r300_vtable vtbl;
 623
 624         struct r300_hw_state hw;
 625
 626         struct r300_vertex_shader_state vertex_shader;
 627         struct r300_vertex_program *selected_vp;
 628
 629         /* Vertex buffers
 630          */
 631         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 632         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 633
 634         GLboolean disable_lowimpact_fallback;
 635
 636         struct r300_swtcl_info swtcl;
 637         GLboolean vap_flush_needed;
 638
 639         DECLARE_RENDERINPUTS(render_inputs_bitset);
 640 };
 641
 642 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 643
 644 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 645 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 646                                    __DRIcontextPrivate * driContextPriv,
 647                                    void *sharedContextPrivate);
 648
 649 extern void r300SelectVertexShader(r300ContextPtr r300);
 650 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 651 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 652                                       struct r300_vertex_program_cont *vp,
 653                                       float *dst);
 654
 655 #define r300PackFloat32 radeonPackFloat32
 656 #define r300PackFloat24 radeonPackFloat24
 657
 658 #endif                          /* __R300_CONTEXT_H__ */