src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "radeon_common.h"
  44
  45 #include "main/mtypes.h"
  46 #include "shader/prog_instruction.h"
  47 #include "compiler/radeon_code.h"
  48
  49 struct r300_context;
  50 typedef struct r300_context r300ContextRec;
  51 typedef struct r300_context *r300ContextPtr;
  52
  53
  54 #include "r300_vertprog.h"
  55
  56
  57 /* The blit width for texture uploads
  58  */
  59 #define R300_BLIT_WIDTH_BYTES 1024
  60 #define R300_MAX_TEXTURE_UNITS 8
  61
  62
  63
  64 #define R300_VPT_CMD_0          0
  65 #define R300_VPT_XSCALE         1
  66 #define R300_VPT_XOFFSET        2
  67 #define R300_VPT_YSCALE         3
  68 #define R300_VPT_YOFFSET        4
  69 #define R300_VPT_ZSCALE         5
  70 #define R300_VPT_ZOFFSET        6
  71 #define R300_VPT_CMDSIZE        7
  72
  73 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
  74 #define R300_VIR_CNTL_0         1
  75 #define R300_VIR_CNTL_1         2
  76 #define R300_VIR_CNTL_2         3
  77 #define R300_VIR_CNTL_3         4
  78 #define R300_VIR_CNTL_4         5
  79 #define R300_VIR_CNTL_5         6
  80 #define R300_VIR_CNTL_6         7
  81 #define R300_VIR_CNTL_7         8
  82 #define R300_VIR_CMDSIZE        9
  83
  84 #define R300_VIC_CMD_0          0
  85 #define R300_VIC_CNTL_0         1
  86 #define R300_VIC_CNTL_1         2
  87 #define R300_VIC_CMDSIZE        3
  88
  89 #define R300_VOF_CMD_0          0
  90 #define R300_VOF_CNTL_0         1
  91 #define R300_VOF_CNTL_1         2
  92 #define R300_VOF_CMDSIZE        3
  93
  94 #define R300_PVS_CMD_0          0
  95 #define R300_PVS_CNTL_1         1
  96 #define R300_PVS_CNTL_2         2
  97 #define R300_PVS_CNTL_3         3
  98 #define R300_PVS_CMDSIZE        4
  99
 100 #define R300_GB_MISC_CMD_0              0
 101 #define R300_GB_MISC_MSPOS_0            1
 102 #define R300_GB_MISC_MSPOS_1            2
 103 #define R300_GB_MISC_TILE_CONFIG        3
 104 #define R300_GB_MISC_CMDSIZE            4
 105 #define R300_GB_MISC2_CMD_0                 0
 106 #define R300_GB_MISC2_SELECT            1
 107 #define R300_GB_MISC2_AA_CONFIG         2
 108 #define R300_GB_MISC2_CMDSIZE           3
 109
 110 #define R300_TXE_CMD_0          0
 111 #define R300_TXE_ENABLE         1
 112 #define R300_TXE_CMDSIZE        2
 113
 114 #define R300_PS_CMD_0           0
 115 #define R300_PS_POINTSIZE       1
 116 #define R300_PS_CMDSIZE         2
 117
 118 #define R300_ZBS_CMD_0          0
 119 #define R300_ZBS_T_FACTOR       1
 120 #define R300_ZBS_T_CONSTANT     2
 121 #define R300_ZBS_W_FACTOR       3
 122 #define R300_ZBS_W_CONSTANT     4
 123 #define R300_ZBS_CMDSIZE        5
 124
 125 #define R300_CUL_CMD_0          0
 126 #define R300_CUL_CULL           1
 127 #define R300_CUL_CMDSIZE        2
 128
 129 #define R300_RC_CMD_0           0
 130 #define R300_RC_CNTL_0          1
 131 #define R300_RC_CNTL_1          2
 132 #define R300_RC_CMDSIZE         3
 133
 134 #define R300_RI_CMD_0           0
 135 #define R300_RI_INTERP_0        1
 136 #define R300_RI_INTERP_1        2
 137 #define R300_RI_INTERP_2        3
 138 #define R300_RI_INTERP_3        4
 139 #define R300_RI_INTERP_4        5
 140 #define R300_RI_INTERP_5        6
 141 #define R300_RI_INTERP_6        7
 142 #define R300_RI_INTERP_7        8
 143 #define R300_RI_CMDSIZE         9
 144
 145 #define R500_RI_CMDSIZE        17
 146
 147 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 148 #define R300_RR_INST_0          1
 149 #define R300_RR_INST_1          2
 150 #define R300_RR_INST_2          3
 151 #define R300_RR_INST_3          4
 152 #define R300_RR_INST_4          5
 153 #define R300_RR_INST_5          6
 154 #define R300_RR_INST_6          7
 155 #define R300_RR_INST_7          8
 156 #define R300_RR_CMDSIZE         9
 157
 158 #define R300_FP_CMD_0           0
 159 #define R300_FP_CNTL0           1
 160 #define R300_FP_CNTL1           2
 161 #define R300_FP_CNTL2           3
 162 #define R300_FP_CMD_1           4
 163 #define R300_FP_NODE0           5
 164 #define R300_FP_NODE1           6
 165 #define R300_FP_NODE2           7
 166 #define R300_FP_NODE3           8
 167 #define R300_FP_CMDSIZE         9
 168
 169 #define R500_FP_CMD_0           0
 170 #define R500_FP_CNTL            1
 171 #define R500_FP_PIXSIZE         2
 172 #define R500_FP_CMD_1           3
 173 #define R500_FP_CODE_ADDR       4
 174 #define R500_FP_CODE_RANGE      5
 175 #define R500_FP_CODE_OFFSET     6
 176 #define R500_FP_CMD_2           7
 177 #define R500_FP_FC_CNTL         8
 178 #define R500_FP_CMDSIZE         9
 179
 180 #define R300_FPT_CMD_0          0
 181 #define R300_FPT_INSTR_0        1
 182 #define R300_FPT_CMDSIZE        65
 183
 184 #define R300_FPI_CMD_0          0
 185 #define R300_FPI_INSTR_0        1
 186 #define R300_FPI_CMDSIZE        65
 187 /* R500 has space for 512 instructions - 6 dwords per instruction */
 188 #define R500_FPI_CMDSIZE        (512*6+1)
 189
 190 #define R300_FPP_CMD_0          0
 191 #define R300_FPP_PARAM_0        1
 192 #define R300_FPP_CMDSIZE        (32*4+1)
 193 /* R500 has spcae for 256 constants - 4 dwords per constant */
 194 #define R500_FPP_CMDSIZE        (256*4+1)
 195
 196 #define R300_FOGS_CMD_0         0
 197 #define R300_FOGS_STATE         1
 198 #define R300_FOGS_CMDSIZE       2
 199
 200 #define R300_FOGC_CMD_0         0
 201 #define R300_FOGC_R             1
 202 #define R300_FOGC_G             2
 203 #define R300_FOGC_B             3
 204 #define R300_FOGC_CMDSIZE       4
 205
 206 #define R300_FOGP_CMD_0         0
 207 #define R300_FOGP_SCALE         1
 208 #define R300_FOGP_START         2
 209 #define R300_FOGP_CMDSIZE       3
 210
 211 #define R300_AT_CMD_0           0
 212 #define R300_AT_ALPHA_TEST      1
 213 #define R300_AT_UNKNOWN         2
 214 #define R300_AT_CMDSIZE         3
 215
 216 #define R300_BLD_CMD_0          0
 217 #define R300_BLD_CBLEND         1
 218 #define R300_BLD_ABLEND         2
 219 #define R300_BLD_CMDSIZE        3
 220
 221 #define R300_CMK_CMD_0          0
 222 #define R300_CMK_COLORMASK      1
 223 #define R300_CMK_CMDSIZE        2
 224
 225 #define R300_CB_CMD_0           0
 226 #define R300_CB_OFFSET          1
 227 #define R300_CB_CMD_1           2
 228 #define R300_CB_PITCH           3
 229 #define R300_CB_CMDSIZE         4
 230
 231 #define R300_ZS_CMD_0           0
 232 #define R300_ZS_CNTL_0          1
 233 #define R300_ZS_CNTL_1          2
 234 #define R300_ZS_CNTL_2          3
 235 #define R300_ZS_CMDSIZE         4
 236
 237 #define R300_ZB_CMD_0           0
 238 #define R300_ZB_OFFSET          1
 239 #define R300_ZB_PITCH           2
 240 #define R300_ZB_CMDSIZE         3
 241
 242 #define R300_VAP_CNTL_FLUSH     0
 243 #define R300_VAP_CNTL_FLUSH_1   1
 244 #define R300_VAP_CNTL_CMD       2
 245 #define R300_VAP_CNTL_INSTR     3
 246 #define R300_VAP_CNTL_SIZE      4
 247
 248 #define R300_VPI_CMD_0          0
 249 #define R300_VPI_INSTR_0        1
 250 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 251
 252 #define R300_VPP_CMD_0          0
 253 #define R300_VPP_PARAM_0        1
 254 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 255
 256 #define R300_VPUCP_CMD_0                0
 257 #define R300_VPUCP_X            1
 258 #define R300_VPUCP_Y            2
 259 #define R300_VPUCP_Z            3
 260 #define R300_VPUCP_W            4
 261 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 262
 263 #define R300_VPS_CMD_0          0
 264 #define R300_VPS_ZERO_0         1
 265 #define R300_VPS_ZERO_1         2
 266 #define R300_VPS_POINTSIZE      3
 267 #define R300_VPS_ZERO_3         4
 268 #define R300_VPS_CMDSIZE        5
 269
 270         /* the layout is common for all fields inside tex */
 271 #define R300_TEX_CMD_0          0
 272 #define R300_TEX_VALUE_0        1
 273 /* We don't really use this, instead specify mtu+1 dynamically
 274 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 275 */
 276
 277 #define R300_QUERYOBJ_CMD_0  0
 278 #define R300_QUERYOBJ_DATA_0 1
 279 #define R300_QUERYOBJ_CMD_1  2
 280 #define R300_QUERYOBJ_DATA_1  3
 281 #define R300_QUERYOBJ_CMDSIZE  4
 282
 283 /**
 284  * Cache for hardware register state.
 285  */
 286 struct r300_hw_state {
 287         struct radeon_state_atom vpt;   /* viewport (1D98) */
 288         struct radeon_state_atom vap_cntl;
 289         struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
 290         struct radeon_state_atom vof;   /* VAP output format register 0x2090 */
 291         struct radeon_state_atom vte;   /* (20B0) */
 292         struct radeon_state_atom vap_vf_max_vtx_indx;   /* Maximum Vertex Indx Clamp (2134) */
 293         struct radeon_state_atom vap_cntl_status;
 294         struct radeon_state_atom vir[2];        /* vap input route (2150/21E0) */
 295         struct radeon_state_atom vic;   /* vap input control (2180) */
 296         struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 297         struct radeon_state_atom vap_clip_cntl;
 298         struct radeon_state_atom vap_clip;
 299         struct radeon_state_atom vap_pvs_vtx_timeout_reg;       /* Vertex timeout register (2288) */
 300         struct radeon_state_atom pvs;   /* pvs_cntl (22D0) */
 301         struct radeon_state_atom gb_enable;     /* (4008) */
 302         struct radeon_state_atom gb_misc;       /* Multisampling position shifts ? (4010) */
 303         struct radeon_state_atom gb_misc2;      /* Multisampling position shifts ? (4010) */
 304         struct radeon_state_atom ga_point_s0;   /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 305         struct radeon_state_atom ga_triangle_stipple;   /* (4214) */
 306         struct radeon_state_atom ps;    /* pointsize (421C) */
 307         struct radeon_state_atom ga_point_minmax;       /* (4230) */
 308         struct radeon_state_atom lcntl; /* line control */
 309         struct radeon_state_atom ga_line_stipple;       /* (4260) */
 310         struct radeon_state_atom shade;
 311         struct radeon_state_atom shade2;
 312         struct radeon_state_atom polygon_mode;
 313         struct radeon_state_atom fogp;  /* fog parameters (4294) */
 314         struct radeon_state_atom ga_soft_reset; /* (429C) */
 315         struct radeon_state_atom zbias_cntl;
 316         struct radeon_state_atom zbs;   /* zbias (42A4) */
 317         struct radeon_state_atom occlusion_cntl;
 318         struct radeon_state_atom cul;   /* cull cntl (42B8) */
 319         struct radeon_state_atom su_depth_scale;        /* (42C0) */
 320         struct radeon_state_atom rc;    /* rs control (4300) */
 321         struct radeon_state_atom ri;    /* rs interpolators (4310) */
 322         struct radeon_state_atom rr;    /* rs route (4330) */
 323         struct radeon_state_atom sc_hyperz;     /* (43A4) */
 324         struct radeon_state_atom sc_screendoor; /* (43E8) */
 325         struct radeon_state_atom fp;    /* fragment program cntl + nodes (4600) */
 326         struct radeon_state_atom fpt;   /* texi - (4620) */
 327         struct radeon_state_atom us_out_fmt;    /* (46A4) */
 328         struct radeon_state_atom r500fp;        /* r500 fp instructions */
 329         struct radeon_state_atom r500fp_const;  /* r500 fp constants */
 330         struct radeon_state_atom fpi[4];        /* fp instructions (46C0/47C0/48C0/49C0) */
 331         struct radeon_state_atom fogs;  /* fog state (4BC0) */
 332         struct radeon_state_atom fogc;  /* fog color (4BC8) */
 333         struct radeon_state_atom at;    /* alpha test (4BD4) */
 334         struct radeon_state_atom fg_depth_src;  /* (4BD8) */
 335         struct radeon_state_atom fpp;   /* 0x4C00 and following */
 336         struct radeon_state_atom rb3d_cctl;     /* (4E00) */
 337         struct radeon_state_atom bld;   /* blending (4E04) */
 338         struct radeon_state_atom cmk;   /* colormask (4E0C) */
 339         struct radeon_state_atom blend_color;   /* constant blend color */
 340         struct radeon_state_atom rop;   /* ropcntl */
 341         struct radeon_state_atom cb;    /* colorbuffer (4E28) */
 342         struct radeon_state_atom rb3d_dither_ctl;       /* (4E50) */
 343         struct radeon_state_atom rb3d_aaresolve_ctl;    /* (4E88) */
 344         struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold;  /* (4E88) I saw it only written on RV350 hardware..  */
 345         struct radeon_state_atom zs;    /* zstencil control (4F00) */
 346         struct radeon_state_atom zstencil_format;
 347         struct radeon_state_atom zb;    /* z buffer (4F20) */
 348         struct radeon_state_atom zb_depthclearvalue;    /* (4F28) */
 349         struct radeon_state_atom zb_zmask;      /* (4F30) */
 350         struct radeon_state_atom zb_hiz_offset; /* (4F44) */
 351         struct radeon_state_atom zb_hiz_pitch;  /* (4F54) */
 352
 353         struct radeon_state_atom vpi;   /* vp instructions */
 354         struct radeon_state_atom vpp;   /* vp parameters */
 355         struct radeon_state_atom vps;   /* vertex point size (?) */
 356         struct radeon_state_atom vpucp[6];      /* vp user clip plane - 6 */
 357         /* 8 texture units */
 358         /* the state is grouped by function and not by
 359            texture unit. This makes single unit updates
 360            really awkward - we are much better off
 361            updating the whole thing at once */
 362         struct {
 363                 struct radeon_state_atom filter;
 364                 struct radeon_state_atom filter_1;
 365                 struct radeon_state_atom size;
 366                 struct radeon_state_atom format;
 367                 struct radeon_state_atom pitch;
 368                 struct radeon_state_atom offset;
 369                 struct radeon_state_atom chroma_key;
 370                 struct radeon_state_atom border_color;
 371         } tex;
 372         struct radeon_state_atom txe;   /* tex enable (4104) */
 373         radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
 374 };
 375
 376 /**
 377  * State cache
 378  */
 379
 380 /* Vertex shader state */
 381
 382 #define COLOR_IS_RGBA
 383 #define TAG(x) r300##x
 384 #include "tnl_dd/t_dd_vertex.h"
 385 #undef TAG
 386
 387 struct r300_vertex_program_key {
 388         GLbitfield FpReads;
 389         GLuint FogAttr;
 390         GLuint WPosAttr;
 391 };
 392
 393 struct r300_vertex_program {
 394         struct gl_vertex_program *Base;
 395         struct r300_vertex_program *next;
 396
 397         struct r300_vertex_program_key key;
 398         struct r300_vertex_program_code code;
 399
 400         GLboolean error;
 401 };
 402
 403 struct r300_vertex_program_cont {
 404         /* This is the unmodified vertex program mesa provided us with.
 405          * We need to keep it unchanged because we may need to create another
 406          * hw specific vertex program based on this.
 407          */
 408         struct gl_vertex_program mesa_program;
 409         /* This is the list of hw specific vertex programs derived from mesa_program */
 410         struct r300_vertex_program *progs;
 411 };
 412
 413
 414 /**
 415 * Store everything about a fragment program that is needed
 416 * to render with that program.
 417 */
 418 struct r300_fragment_program {
 419         GLboolean error;
 420         struct r300_fragment_program *next;
 421         struct r300_fragment_program_external_state state;
 422
 423         struct rX00_fragment_program_code code;
 424         GLbitfield InputsRead;
 425
 426         /* attribute that we are sending the WPOS in */
 427         gl_frag_attrib wpos_attr;
 428         /* attribute that we are sending the fog coordinate in */
 429         gl_frag_attrib fog_attr;
 430 };
 431
 432 struct r300_fragment_program_cont {
 433         /* This is the unmodified fragment program mesa provided us with.
 434          * We need to keep it unchanged because we may need to create another
 435          * hw specific fragment program based on this.
 436          */
 437         struct gl_fragment_program Base;
 438         /* This is the list of hw specific fragment programs derived from Base */
 439         struct r300_fragment_program *progs;
 440 };
 441
 442
 443 #define R300_MAX_AOS_ARRAYS             16
 444
 445
 446 /* r300_swtcl.c
 447  */
 448 struct r300_swtcl_info {
 449   /*
 450     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 451     */
 452    GLuint coloroffset;
 453
 454    /**
 455     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 456     */
 457    GLuint specoffset;
 458 };
 459
 460 struct r300_vtable {
 461         void (* SetupRSUnit)(GLcontext *ctx);
 462         void (* SetupFragmentShaderTextures)(GLcontext *ctx, int *tmu_mappings);
 463         void (* SetupPixelShader)(GLcontext *ctx);
 464 };
 465
 466 struct r300_vertex_buffer {
 467         struct vertex_attribute {
 468                 /* generic */
 469                 GLubyte element;
 470                 GLuint stride;
 471                 GLuint dwords;
 472                 GLubyte size; /* number of components */
 473                 GLboolean is_named_bo;
 474                 struct radeon_bo *bo;
 475                 GLint bo_offset;
 476
 477                 /* hw specific */
 478                 uint32_t data_type:4;
 479                 uint32_t dst_loc:5;
 480                 uint32_t _signed:1;
 481                 uint32_t normalize:1;
 482                 uint32_t swizzle:12;
 483                 uint32_t write_mask:4;
 484         } attribs[VERT_ATTRIB_MAX];
 485
 486         GLubyte num_attribs;
 487 };
 488
 489 struct r300_index_buffer {
 490         struct radeon_bo *bo;
 491         int bo_offset;
 492
 493         GLboolean is_32bit;
 494         GLuint count;
 495 };
 496
 497
 498 /**
 499  * \brief R300 context structure.
 500  */
 501 struct r300_context {
 502         struct radeon_context radeon;   /* parent class, must be first */
 503
 504         struct r300_vtable vtbl;
 505
 506         struct r300_hw_state hw;
 507
 508         struct r300_vertex_program *selected_vp;
 509         struct r300_fragment_program *selected_fp;
 510
 511         /* Vertex buffers
 512          */
 513         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 514         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 515
 516         struct r300_options {
 517                 uint32_t conformance_mode:1;
 518                 uint32_t hw_tcl_enabled:1;
 519                 uint32_t s3tc_force_enabled:1;
 520                 uint32_t s3tc_force_disabled:1;
 521                 uint32_t stencil_two_side_disabled:1;
 522         } options;
 523
 524         struct r300_swtcl_info swtcl;
 525         struct r300_vertex_buffer vbuf;
 526         struct r300_index_buffer ind_buf;
 527         GLboolean vap_flush_needed;
 528
 529         uint32_t fallback;
 530
 531         DECLARE_RENDERINPUTS(render_inputs_bitset);
 532         int num_z_pipes;
 533 };
 534
 535 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 536
 537 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 538 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 539                                    __DRIcontextPrivate * driContextPriv,
 540                                    void *sharedContextPrivate);
 541
 542 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 543
 544 extern void r300InitShaderFunctions(r300ContextPtr r300);
 545
 546 extern void r300InitDraw(GLcontext *ctx);
 547
 548 #define r300PackFloat32 radeonPackFloat32
 549 #define r300PackFloat24 radeonPackFloat24
 550
 551 #endif                          /* __R300_CONTEXT_H__ */