src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "radeon_common.h"
  44
  45 #include "main/mtypes.h"
  46 #include "shader/prog_instruction.h"
  47
  48 struct r300_context;
  49 typedef struct r300_context r300ContextRec;
  50 typedef struct r300_context *r300ContextPtr;
  51
  52
  53 /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  54    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  55    with other compilers ... GLUE!
  56 */
  57 #define WARN_ONCE(a, ...)       { \
  58         static int warn##__LINE__=1; \
  59         if(warn##__LINE__){ \
  60                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  61                 fprintf(stderr, "File %s function %s line %d\n", \
  62                         __FILE__, __FUNCTION__, __LINE__); \
  63                 fprintf(stderr,  a, ## __VA_ARGS__);\
  64                 fprintf(stderr, "***************************************************************************\n"); \
  65                 warn##__LINE__=0;\
  66                 } \
  67         }
  68
  69 #include "r300_vertprog.h"
  70
  71
  72 /* The blit width for texture uploads
  73  */
  74 #define R300_BLIT_WIDTH_BYTES 1024
  75 #define R300_MAX_TEXTURE_UNITS 8
  76
  77
  78
  79 #define R300_VPT_CMD_0          0
  80 #define R300_VPT_XSCALE         1
  81 #define R300_VPT_XOFFSET        2
  82 #define R300_VPT_YSCALE         3
  83 #define R300_VPT_YOFFSET        4
  84 #define R300_VPT_ZSCALE         5
  85 #define R300_VPT_ZOFFSET        6
  86 #define R300_VPT_CMDSIZE        7
  87
  88 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
  89 #define R300_VIR_CNTL_0         1
  90 #define R300_VIR_CNTL_1         2
  91 #define R300_VIR_CNTL_2         3
  92 #define R300_VIR_CNTL_3         4
  93 #define R300_VIR_CNTL_4         5
  94 #define R300_VIR_CNTL_5         6
  95 #define R300_VIR_CNTL_6         7
  96 #define R300_VIR_CNTL_7         8
  97 #define R300_VIR_CMDSIZE        9
  98
  99 #define R300_VIC_CMD_0          0
 100 #define R300_VIC_CNTL_0         1
 101 #define R300_VIC_CNTL_1         2
 102 #define R300_VIC_CMDSIZE        3
 103
 104 #define R300_VOF_CMD_0          0
 105 #define R300_VOF_CNTL_0         1
 106 #define R300_VOF_CNTL_1         2
 107 #define R300_VOF_CMDSIZE        3
 108
 109 #define R300_PVS_CMD_0          0
 110 #define R300_PVS_CNTL_1         1
 111 #define R300_PVS_CNTL_2         2
 112 #define R300_PVS_CNTL_3         3
 113 #define R300_PVS_CMDSIZE        4
 114
 115 #define R300_GB_MISC_CMD_0              0
 116 #define R300_GB_MISC_MSPOS_0            1
 117 #define R300_GB_MISC_MSPOS_1            2
 118 #define R300_GB_MISC_TILE_CONFIG        3
 119 #define R300_GB_MISC_SELECT             4
 120 #define R300_GB_MISC_AA_CONFIG          5
 121 #define R300_GB_MISC_CMDSIZE            6
 122
 123 #define R300_TXE_CMD_0          0
 124 #define R300_TXE_ENABLE         1
 125 #define R300_TXE_CMDSIZE        2
 126
 127 #define R300_PS_CMD_0           0
 128 #define R300_PS_POINTSIZE       1
 129 #define R300_PS_CMDSIZE         2
 130
 131 #define R300_ZBS_CMD_0          0
 132 #define R300_ZBS_T_FACTOR       1
 133 #define R300_ZBS_T_CONSTANT     2
 134 #define R300_ZBS_W_FACTOR       3
 135 #define R300_ZBS_W_CONSTANT     4
 136 #define R300_ZBS_CMDSIZE        5
 137
 138 #define R300_CUL_CMD_0          0
 139 #define R300_CUL_CULL           1
 140 #define R300_CUL_CMDSIZE        2
 141
 142 #define R300_RC_CMD_0           0
 143 #define R300_RC_CNTL_0          1
 144 #define R300_RC_CNTL_1          2
 145 #define R300_RC_CMDSIZE         3
 146
 147 #define R300_RI_CMD_0           0
 148 #define R300_RI_INTERP_0        1
 149 #define R300_RI_INTERP_1        2
 150 #define R300_RI_INTERP_2        3
 151 #define R300_RI_INTERP_3        4
 152 #define R300_RI_INTERP_4        5
 153 #define R300_RI_INTERP_5        6
 154 #define R300_RI_INTERP_6        7
 155 #define R300_RI_INTERP_7        8
 156 #define R300_RI_CMDSIZE         9
 157
 158 #define R500_RI_CMDSIZE        17
 159
 160 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 161 #define R300_RR_INST_0          1
 162 #define R300_RR_INST_1          2
 163 #define R300_RR_INST_2          3
 164 #define R300_RR_INST_3          4
 165 #define R300_RR_INST_4          5
 166 #define R300_RR_INST_5          6
 167 #define R300_RR_INST_6          7
 168 #define R300_RR_INST_7          8
 169 #define R300_RR_CMDSIZE         9
 170
 171 #define R300_FP_CMD_0           0
 172 #define R300_FP_CNTL0           1
 173 #define R300_FP_CNTL1           2
 174 #define R300_FP_CNTL2           3
 175 #define R300_FP_CMD_1           4
 176 #define R300_FP_NODE0           5
 177 #define R300_FP_NODE1           6
 178 #define R300_FP_NODE2           7
 179 #define R300_FP_NODE3           8
 180 #define R300_FP_CMDSIZE         9
 181
 182 #define R500_FP_CMD_0           0
 183 #define R500_FP_CNTL            1
 184 #define R500_FP_PIXSIZE         2
 185 #define R500_FP_CMD_1           3
 186 #define R500_FP_CODE_ADDR       4
 187 #define R500_FP_CODE_RANGE      5
 188 #define R500_FP_CODE_OFFSET     6
 189 #define R500_FP_CMD_2           7
 190 #define R500_FP_FC_CNTL         8
 191 #define R500_FP_CMDSIZE         9
 192
 193 #define R300_FPT_CMD_0          0
 194 #define R300_FPT_INSTR_0        1
 195 #define R300_FPT_CMDSIZE        65
 196
 197 #define R300_FPI_CMD_0          0
 198 #define R300_FPI_INSTR_0        1
 199 #define R300_FPI_CMDSIZE        65
 200 /* R500 has space for 512 instructions - 6 dwords per instruction */
 201 #define R500_FPI_CMDSIZE        (512*6+1)
 202
 203 #define R300_FPP_CMD_0          0
 204 #define R300_FPP_PARAM_0        1
 205 #define R300_FPP_CMDSIZE        (32*4+1)
 206 /* R500 has spcae for 256 constants - 4 dwords per constant */
 207 #define R500_FPP_CMDSIZE        (256*4+1)
 208
 209 #define R300_FOGS_CMD_0         0
 210 #define R300_FOGS_STATE         1
 211 #define R300_FOGS_CMDSIZE       2
 212
 213 #define R300_FOGC_CMD_0         0
 214 #define R300_FOGC_R             1
 215 #define R300_FOGC_G             2
 216 #define R300_FOGC_B             3
 217 #define R300_FOGC_CMDSIZE       4
 218
 219 #define R300_FOGP_CMD_0         0
 220 #define R300_FOGP_SCALE         1
 221 #define R300_FOGP_START         2
 222 #define R300_FOGP_CMDSIZE       3
 223
 224 #define R300_AT_CMD_0           0
 225 #define R300_AT_ALPHA_TEST      1
 226 #define R300_AT_UNKNOWN         2
 227 #define R300_AT_CMDSIZE         3
 228
 229 #define R300_BLD_CMD_0          0
 230 #define R300_BLD_CBLEND         1
 231 #define R300_BLD_ABLEND         2
 232 #define R300_BLD_CMDSIZE        3
 233
 234 #define R300_CMK_CMD_0          0
 235 #define R300_CMK_COLORMASK      1
 236 #define R300_CMK_CMDSIZE        2
 237
 238 #define R300_CB_CMD_0           0
 239 #define R300_CB_OFFSET          1
 240 #define R300_CB_CMD_1           2
 241 #define R300_CB_PITCH           3
 242 #define R300_CB_CMDSIZE         4
 243
 244 #define R300_ZS_CMD_0           0
 245 #define R300_ZS_CNTL_0          1
 246 #define R300_ZS_CNTL_1          2
 247 #define R300_ZS_CNTL_2          3
 248 #define R300_ZS_CMDSIZE         4
 249
 250 #define R300_ZB_CMD_0           0
 251 #define R300_ZB_OFFSET          1
 252 #define R300_ZB_PITCH           2
 253 #define R300_ZB_CMDSIZE         3
 254
 255 #define R300_VAP_CNTL_FLUSH     0
 256 #define R300_VAP_CNTL_FLUSH_1   1
 257 #define R300_VAP_CNTL_CMD       2
 258 #define R300_VAP_CNTL_INSTR     3
 259 #define R300_VAP_CNTL_SIZE      4
 260
 261 #define R300_VPI_CMD_0          0
 262 #define R300_VPI_INSTR_0        1
 263 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 264
 265 #define R300_VPP_CMD_0          0
 266 #define R300_VPP_PARAM_0        1
 267 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 268
 269 #define R300_VPUCP_CMD_0                0
 270 #define R300_VPUCP_X            1
 271 #define R300_VPUCP_Y            2
 272 #define R300_VPUCP_Z            3
 273 #define R300_VPUCP_W            4
 274 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 275
 276 #define R300_VPS_CMD_0          0
 277 #define R300_VPS_ZERO_0         1
 278 #define R300_VPS_ZERO_1         2
 279 #define R300_VPS_POINTSIZE      3
 280 #define R300_VPS_ZERO_3         4
 281 #define R300_VPS_CMDSIZE        5
 282
 283         /* the layout is common for all fields inside tex */
 284 #define R300_TEX_CMD_0          0
 285 #define R300_TEX_VALUE_0        1
 286 /* We don't really use this, instead specify mtu+1 dynamically
 287 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 288 */
 289
 290 /**
 291  * Cache for hardware register state.
 292  */
 293 struct r300_hw_state {
 294         struct radeon_state_atom vpt;   /* viewport (1D98) */
 295         struct radeon_state_atom vap_cntl;
 296         struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
 297         struct radeon_state_atom vof;   /* VAP output format register 0x2090 */
 298         struct radeon_state_atom vte;   /* (20B0) */
 299         struct radeon_state_atom vap_vf_max_vtx_indx;   /* Maximum Vertex Indx Clamp (2134) */
 300         struct radeon_state_atom vap_cntl_status;
 301         struct radeon_state_atom vir[2];        /* vap input route (2150/21E0) */
 302         struct radeon_state_atom vic;   /* vap input control (2180) */
 303         struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 304         struct radeon_state_atom vap_clip_cntl;
 305         struct radeon_state_atom vap_clip;
 306         struct radeon_state_atom vap_pvs_vtx_timeout_reg;       /* Vertex timeout register (2288) */
 307         struct radeon_state_atom pvs;   /* pvs_cntl (22D0) */
 308         struct radeon_state_atom gb_enable;     /* (4008) */
 309         struct radeon_state_atom gb_misc;       /* Multisampling position shifts ? (4010) */
 310         struct radeon_state_atom ga_point_s0;   /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 311         struct radeon_state_atom ga_triangle_stipple;   /* (4214) */
 312         struct radeon_state_atom ps;    /* pointsize (421C) */
 313         struct radeon_state_atom ga_point_minmax;       /* (4230) */
 314         struct radeon_state_atom lcntl; /* line control */
 315         struct radeon_state_atom ga_line_stipple;       /* (4260) */
 316         struct radeon_state_atom shade;
 317         struct radeon_state_atom polygon_mode;
 318         struct radeon_state_atom fogp;  /* fog parameters (4294) */
 319         struct radeon_state_atom ga_soft_reset; /* (429C) */
 320         struct radeon_state_atom zbias_cntl;
 321         struct radeon_state_atom zbs;   /* zbias (42A4) */
 322         struct radeon_state_atom occlusion_cntl;
 323         struct radeon_state_atom cul;   /* cull cntl (42B8) */
 324         struct radeon_state_atom su_depth_scale;        /* (42C0) */
 325         struct radeon_state_atom rc;    /* rs control (4300) */
 326         struct radeon_state_atom ri;    /* rs interpolators (4310) */
 327         struct radeon_state_atom rr;    /* rs route (4330) */
 328         struct radeon_state_atom sc_hyperz;     /* (43A4) */
 329         struct radeon_state_atom sc_screendoor; /* (43E8) */
 330         struct radeon_state_atom fp;    /* fragment program cntl + nodes (4600) */
 331         struct radeon_state_atom fpt;   /* texi - (4620) */
 332         struct radeon_state_atom us_out_fmt;    /* (46A4) */
 333         struct radeon_state_atom r500fp;        /* r500 fp instructions */
 334         struct radeon_state_atom r500fp_const;  /* r500 fp constants */
 335         struct radeon_state_atom fpi[4];        /* fp instructions (46C0/47C0/48C0/49C0) */
 336         struct radeon_state_atom fogs;  /* fog state (4BC0) */
 337         struct radeon_state_atom fogc;  /* fog color (4BC8) */
 338         struct radeon_state_atom at;    /* alpha test (4BD4) */
 339         struct radeon_state_atom fg_depth_src;  /* (4BD8) */
 340         struct radeon_state_atom fpp;   /* 0x4C00 and following */
 341         struct radeon_state_atom rb3d_cctl;     /* (4E00) */
 342         struct radeon_state_atom bld;   /* blending (4E04) */
 343         struct radeon_state_atom cmk;   /* colormask (4E0C) */
 344         struct radeon_state_atom blend_color;   /* constant blend color */
 345         struct radeon_state_atom rop;   /* ropcntl */
 346         struct radeon_state_atom cb;    /* colorbuffer (4E28) */
 347         struct radeon_state_atom rb3d_dither_ctl;       /* (4E50) */
 348         struct radeon_state_atom rb3d_aaresolve_ctl;    /* (4E88) */
 349         struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold;  /* (4E88) I saw it only written on RV350 hardware..  */
 350         struct radeon_state_atom zs;    /* zstencil control (4F00) */
 351         struct radeon_state_atom zstencil_format;
 352         struct radeon_state_atom zb;    /* z buffer (4F20) */
 353         struct radeon_state_atom zb_depthclearvalue;    /* (4F28) */
 354         struct radeon_state_atom zb_zmask;      /* (4F30) */
 355         struct radeon_state_atom zb_hiz_offset; /* (4F44) */
 356         struct radeon_state_atom zb_hiz_pitch;  /* (4F54) */
 357
 358         struct radeon_state_atom vpi;   /* vp instructions */
 359         struct radeon_state_atom vpp;   /* vp parameters */
 360         struct radeon_state_atom vps;   /* vertex point size (?) */
 361         struct radeon_state_atom vpucp[6];      /* vp user clip plane - 6 */
 362         /* 8 texture units */
 363         /* the state is grouped by function and not by
 364            texture unit. This makes single unit updates
 365            really awkward - we are much better off
 366            updating the whole thing at once */
 367         struct {
 368                 struct radeon_state_atom filter;
 369                 struct radeon_state_atom filter_1;
 370                 struct radeon_state_atom size;
 371                 struct radeon_state_atom format;
 372                 struct radeon_state_atom pitch;
 373                 struct radeon_state_atom offset;
 374                 struct radeon_state_atom chroma_key;
 375                 struct radeon_state_atom border_color;
 376         } tex;
 377         struct radeon_state_atom txe;   /* tex enable (4104) */
 378
 379         radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
 380 };
 381
 382 /**
 383  * State cache
 384  */
 385
 386 /* Vertex shader state */
 387
 388 /* Perhaps more if we store programs in vmem? */
 389 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 390 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 391
 392 /* Can be tested with colormat currently. */
 393 #define VSF_MAX_FRAGMENT_TEMPS (14)
 394
 395 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 396 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 397
 398 struct r300_vertex_shader_fragment {
 399         int length;
 400         union {
 401                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 402                 float f[VSF_MAX_FRAGMENT_LENGTH];
 403                 GLuint i[VSF_MAX_FRAGMENT_LENGTH];
 404         } body;
 405 };
 406
 407 struct r300_vertex_shader_state {
 408         struct r300_vertex_shader_fragment program;
 409 };
 410
 411 extern int hw_tcl_on;
 412
 413 #define COLOR_IS_RGBA
 414 #define TAG(x) r300##x
 415 #include "tnl_dd/t_dd_vertex.h"
 416 #undef TAG
 417
 418 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 419
 420 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 421  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 422  */
 423
 424 struct r300_vertex_program_key {
 425         GLuint InputsRead;
 426         GLuint OutputsWritten;
 427         GLuint OutputsAdded;
 428 };
 429
 430 struct r300_vertex_program {
 431         struct r300_vertex_program *next;
 432         struct r300_vertex_program_key key;
 433         int translated;
 434
 435         struct r300_vertex_shader_fragment program;
 436
 437         int pos_end;
 438         int num_temporaries;    /* Number of temp vars used by program */
 439         int wpos_idx;
 440         int inputs[VERT_ATTRIB_MAX];
 441         int outputs[VERT_RESULT_MAX];
 442         int native;
 443         int ref_count;
 444         int use_ref_count;
 445 };
 446
 447 struct r300_vertex_program_cont {
 448         struct gl_vertex_program mesa_program;  /* Must be first */
 449         struct r300_vertex_shader_fragment params;
 450         struct r300_vertex_program *progs;
 451 };
 452
 453 #define R300_PFS_MAX_ALU_INST   64
 454 #define R300_PFS_MAX_TEX_INST   32
 455 #define R300_PFS_MAX_TEX_INDIRECT 4
 456 #define R300_PFS_NUM_TEMP_REGS  32
 457 #define R300_PFS_NUM_CONST_REGS 32
 458
 459 #define R500_PFS_MAX_INST 512
 460 #define R500_PFS_NUM_TEMP_REGS 128
 461 #define R500_PFS_NUM_CONST_REGS 256
 462
 463 struct r300_pfs_compile_state;
 464 struct r500_pfs_compile_state;
 465
 466 /**
 467  * Stores state that influences the compilation of a fragment program.
 468  */
 469 struct r300_fragment_program_external_state {
 470         struct {
 471                 /**
 472                  * If the sampler is used as a shadow sampler,
 473                  * this field is:
 474                  *  0 - GL_LUMINANCE
 475                  *  1 - GL_INTENSITY
 476                  *  2 - GL_ALPHA
 477                  * depending on the depth texture mode.
 478                  */
 479                 GLuint depth_texture_mode : 2;
 480
 481                 /**
 482                  * If the sampler is used as a shadow sampler,
 483                  * this field is (texture_compare_func - GL_NEVER).
 484                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 485                  *
 486                  * Otherwise, this field is 0.
 487                  */
 488                 GLuint texture_compare_func : 3;
 489         } unit[16];
 490 };
 491
 492
 493 struct r300_fragment_program_node {
 494         int tex_offset; /**< first tex instruction */
 495         int tex_end; /**< last tex instruction, relative to tex_offset */
 496         int alu_offset; /**< first ALU instruction */
 497         int alu_end; /**< last ALU instruction, relative to alu_offset */
 498         int flags;
 499 };
 500
 501 /**
 502  * Stores an R300 fragment program in its compiled-to-hardware form.
 503  */
 504 struct r300_fragment_program_code {
 505         struct {
 506                 int length; /**< total # of texture instructions used */
 507                 GLuint inst[R300_PFS_MAX_TEX_INST];
 508         } tex;
 509
 510         struct {
 511                 int length; /**< total # of ALU instructions used */
 512                 struct {
 513                         GLuint inst0;
 514                         GLuint inst1;
 515                         GLuint inst2;
 516                         GLuint inst3;
 517                 } inst[R300_PFS_MAX_ALU_INST];
 518         } alu;
 519
 520         struct r300_fragment_program_node node[4];
 521         int cur_node;
 522         int first_node_has_tex;
 523
 524         /**
 525          * Remember which program register a given hardware constant
 526          * belongs to.
 527          */
 528         struct prog_src_register constant[R300_PFS_NUM_CONST_REGS];
 529         int const_nr;
 530
 531         int max_temp_idx;
 532 };
 533
 534
 535 struct r500_fragment_program_code {
 536         struct {
 537                 GLuint inst0;
 538                 GLuint inst1;
 539                 GLuint inst2;
 540                 GLuint inst3;
 541                 GLuint inst4;
 542                 GLuint inst5;
 543         } inst[R500_PFS_MAX_INST];
 544
 545         int inst_offset;
 546         int inst_end;
 547
 548         /**
 549          * Remember which program register a given hardware constant
 550          * belongs to.
 551          */
 552         struct prog_src_register constant[R500_PFS_NUM_CONST_REGS];
 553         int const_nr;
 554
 555         int max_temp_idx;
 556 };
 557
 558 /**
 559 * Store everything about a fragment program that is needed
 560 * to render with that program.
 561 */
 562 struct r300_fragment_program {
 563         struct gl_fragment_program Base;
 564
 565         GLboolean translated;
 566         GLboolean error;
 567
 568         struct r300_fragment_program_external_state state;
 569         union rX00_fragment_program_code {
 570                 struct r300_fragment_program_code r300;
 571                 struct r500_fragment_program_code r500;
 572         } code;
 573
 574         GLboolean writes_depth;
 575         GLuint optimization;
 576 };
 577
 578 struct r300_fragment_program_compiler {
 579         r300ContextPtr r300;
 580         struct r300_fragment_program *fp;
 581         union rX00_fragment_program_code *code;
 582         struct gl_program *program;
 583 };
 584
 585 #define R300_MAX_AOS_ARRAYS             16
 586
 587
 588 #define R300_FALLBACK_NONE 0
 589 #define R300_FALLBACK_TCL 1
 590 #define R300_FALLBACK_RAST 2
 591
 592 /* r300_swtcl.c
 593  */
 594 struct r300_swtcl_info {
 595   /*
 596     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 597     */
 598    GLuint coloroffset;
 599
 600    /**
 601     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 602     */
 603    GLuint specoffset;
 604
 605    struct vertex_attribute{
 606        GLuint attr;
 607        GLubyte format;
 608        GLubyte dst_loc;
 609        GLuint swizzle;
 610        GLubyte write_mask;
 611    } vert_attrs[VERT_ATTRIB_MAX];
 612
 613    GLubyte vertex_attr_count;
 614
 615    int sw_tcl_inputs[VERT_ATTRIB_MAX];
 616 };
 617
 618 struct r300_vtable {
 619         void (* SetupRSUnit)(GLcontext *ctx);
 620         void (* SetupFragmentShaderTextures)(GLcontext *ctx, int *tmu_mappings);
 621         GLboolean (* FragmentProgramEmit)(struct r300_fragment_program_compiler *compiler);
 622         void (* FragmentProgramDump)(union rX00_fragment_program_code *code);
 623         GLboolean (* SetupPixelShader)(GLcontext *ctx);
 624 };
 625
 626
 627 /**
 628  * \brief R300 context structure.
 629  */
 630 struct r300_context {
 631         struct radeon_context radeon;   /* parent class, must be first */
 632
 633         struct r300_vtable vtbl;
 634
 635         struct r300_hw_state hw;
 636
 637         struct r300_vertex_shader_state vertex_shader;
 638         struct r300_vertex_program *selected_vp;
 639
 640         /* Vertex buffers
 641          */
 642         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 643         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 644
 645         GLboolean disable_lowimpact_fallback;
 646
 647         struct r300_swtcl_info swtcl;
 648         GLboolean vap_flush_needed;
 649
 650         DECLARE_RENDERINPUTS(render_inputs_bitset);
 651 };
 652
 653 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 654
 655 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 656 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 657                                    __DRIcontextPrivate * driContextPriv,
 658                                    void *sharedContextPrivate);
 659
 660 extern void r300SelectVertexShader(r300ContextPtr r300);
 661 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 662 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 663                                       struct r300_vertex_program_cont *vp,
 664                                       float *dst);
 665
 666 extern void r300InitShaderFunctions(r300ContextPtr r300);
 667
 668 #define r300PackFloat32 radeonPackFloat32
 669 #define r300PackFloat24 radeonPackFloat24
 670
 671 #endif                          /* __R300_CONTEXT_H__ */