src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 struct r300_context;
  51 typedef struct r300_context r300ContextRec;
  52 typedef struct r300_context *r300ContextPtr;
  53
  54 #include "radeon_lock.h"
  55 #include "mm.h"
  56
  57 typedef GLuint uint32_t;
  58 typedef GLubyte uint8_t;
  59
  60
  61 static __inline__ uint32_t r300PackFloat32(float fl)
  62 {
  63         union { float fl; uint32_t u; } u;
  64
  65         u.fl = fl;
  66         return u.u;
  67 }
  68
  69
  70 /************ DMA BUFFERS **************/
  71
  72 /* Need refcounting on dma buffers:
  73  */
  74 struct r300_dma_buffer {
  75         int refcount;           /* the number of retained regions in buf */
  76         drmBufPtr buf;
  77 };
  78
  79 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
  80                         (rvb)->address - rmesa->dma.buf0_address +      \
  81                         (rvb)->start)
  82
  83 /* A retained region, eg vertices for indexed vertices.
  84  */
  85 struct r300_dma_region {
  86         struct r300_dma_buffer *buf;
  87         char *address;          /* == buf->address */
  88         int start, end, ptr;    /* offsets from start of buf */
  89         int aos_start;
  90         int aos_stride;
  91         int aos_size;
  92 };
  93
  94 struct r300_dma {
  95         /* Active dma region.  Allocations for vertices and retained
  96          * regions come from here.  Also used for emitting random vertices,
  97          * these may be flushed by calling flush_current();
  98          */
  99         struct r300_dma_region current;
 100
 101         void (*flush) (r300ContextPtr);
 102
 103         char *buf0_address;     /* start of buf[0], for index calcs */
 104         GLuint nr_released_bufs;        /* flush after so many buffers released */
 105 };
 106
 107        /* Texture related */
 108
 109 #define TEX_0   0x1
 110 #define TEX_1   0x2
 111 #define TEX_2   0x4
 112 #define TEX_3   0x8
 113 #define TEX_4   0x10
 114 #define TEX_5   0x20
 115 #define TEX_6   0x40
 116 #define TEX_7   0x80
 117 #define TEX_ALL 0xff
 118
 119 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 120
 121 /* Texture object in locally shared texture space.
 122  */
 123 struct r300_tex_obj {
 124         driTextureObject base;
 125
 126         GLuint bufAddr;         /* Offset to start of locally
 127                                    shared texture block */
 128
 129         GLuint dirty_state;     /* Flags (1 per texunit) for
 130                                    whether or not this texobj
 131                                    has dirty hardware state
 132                                    (pp_*) that needs to be
 133                                    brought into the
 134                                    texunit. */
 135
 136         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 137         /* Six, for the cube faces */
 138
 139
 140         /* hardware register values */
 141         /* Note that R200 has 8 registers per texture and R300 only 7 */
 142         GLuint filter;
 143         GLuint pitch; /* one of the unknown registers.. unknown 1 ?*/
 144         GLuint size;    /* npot only */
 145         GLuint format;
 146         GLuint offset;  /* Image location in texmem.
 147                                    All cube faces follow. */
 148         GLuint unknown4;
 149         GLuint unknown5;
 150         /* end hardware registers */
 151
 152         GLboolean border_fallback;
 153 };
 154
 155 struct r300_texture_env_state {
 156         r300TexObjPtr texobj;
 157         GLenum format;
 158         GLenum envMode;
 159 };
 160
 161 #define R300_MAX_TEXTURE_UNITS 6
 162
 163 struct r300_texture_state {
 164         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 165 };
 166
 167 /**
 168  * A block of hardware state.
 169  *
 170  * When check returns non-zero, the returned number of dwords must be
 171  * copied verbatim into the command buffer in order to update a state atom
 172  * when it is dirty.
 173  */
 174 struct r300_state_atom {
 175         struct r300_state_atom *next, *prev;
 176         const char* name;       /* for debug */
 177         int cmd_size;           /* maximum size in dwords */
 178         GLuint idx;             /* index in an array (e.g. textures) */
 179         uint32_t* cmd;
 180         GLboolean dirty;
 181
 182         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 183 };
 184
 185
 186 #define R300_VPT_CMD_0          0
 187 #define R300_VPT_XSCALE         1
 188 #define R300_VPT_XOFFSET        2
 189 #define R300_VPT_YSCALE         3
 190 #define R300_VPT_YOFFSET        4
 191 #define R300_VPT_ZSCALE         5
 192 #define R300_VPT_ZOFFSET        6
 193 #define R300_VPT_CMDSIZE        7
 194
 195 #define R300_OVF_CMD_0          0
 196 #define R300_OVF_FMT_0          1
 197 #define R300_OVF_FMT_1          2
 198 #define R300_OVF_CMDSIZE        3
 199
 200 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 201 #define R300_VIR_CNTL_0         1
 202 #define R300_VIR_CNTL_1         2
 203 #define R300_VIR_CNTL_2         3
 204 #define R300_VIR_CNTL_3         4
 205 #define R300_VIR_CNTL_4         5
 206 #define R300_VIR_CNTL_5         6
 207 #define R300_VIR_CNTL_6         7
 208 #define R300_VIR_CNTL_7         8
 209 #define R300_VIR_CMDSIZE        9
 210
 211 #define R300_VIC_CMD_0          0
 212 #define R300_VIC_CNTL_0         1
 213 #define R300_VIC_CNTL_1         2
 214 #define R300_VIC_CMDSIZE        3
 215
 216 #define R300_VOF_CMD_0          0
 217 #define R300_VOF_CNTL_0         1
 218 #define R300_VOF_CNTL_1         2
 219 #define R300_VOF_CMDSIZE        3
 220
 221
 222 #define R300_PVS_CMD_0          0
 223 #define R300_PVS_CNTL_1         1
 224 #define R300_PVS_CNTL_2         2
 225 #define R300_PVS_CNTL_3         3
 226 #define R300_PVS_CMDSIZE        4
 227
 228 #define R300_GB_MISC_CMD_0              0
 229 #define R300_GB_MISC_MSPOS_0            1
 230 #define R300_GB_MISC_MSPOS_1            2
 231 #define R300_GB_MISC_TILE_CONFIG        3
 232 #define R300_GB_MISC_SELECT             4
 233 #define R300_GB_MISC_AA_CONFIG          5
 234 #define R300_GB_MISC_CMDSIZE            6
 235
 236 #define R300_TXE_CMD_0          0
 237 #define R300_TXE_ENABLE         1
 238 #define R300_TXE_CMDSIZE        2
 239
 240 #define R300_PS_CMD_0           0
 241 #define R300_PS_POINTSIZE       1
 242 #define R300_PS_CMDSIZE         2
 243
 244 #define R300_CUL_CMD_0          0
 245 #define R300_CUL_CULL           1
 246 #define R300_CUL_CMDSIZE        2
 247
 248 #define R300_RC_CMD_0           0
 249 #define R300_RC_CNTL_0          1
 250 #define R300_RC_CNTL_1          2
 251 #define R300_RC_CMDSIZE         3
 252
 253 #define R300_RI_CMD_0           0
 254 #define R300_RI_INTERP_0        1
 255 #define R300_RI_INTERP_1        2
 256 #define R300_RI_INTERP_2        3
 257 #define R300_RI_INTERP_3        4
 258 #define R300_RI_INTERP_4        5
 259 #define R300_RI_INTERP_5        6
 260 #define R300_RI_INTERP_6        7
 261 #define R300_RI_INTERP_7        8
 262 #define R300_RI_CMDSIZE         9
 263
 264 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 265 #define R300_RR_ROUTE_0         1
 266 #define R300_RR_ROUTE_1         2
 267 #define R300_RR_ROUTE_2         3
 268 #define R300_RR_ROUTE_3         4
 269 #define R300_RR_ROUTE_4         5
 270 #define R300_RR_ROUTE_5         6
 271 #define R300_RR_ROUTE_6         7
 272 #define R300_RR_ROUTE_7         8
 273 #define R300_RR_CMDSIZE         9
 274
 275 #define R300_FP_CMD_0           0
 276 #define R300_FP_CNTL0           1
 277 #define R300_FP_CNTL1           2
 278 #define R300_FP_CNTL2           3
 279 #define R300_FP_CMD_1           4
 280 #define R300_FP_NODE0           5
 281 #define R300_FP_NODE1           6
 282 #define R300_FP_NODE2           7
 283 #define R300_FP_NODE3           8
 284 #define R300_FP_CMDSIZE         9
 285
 286 #define R300_FPI_CMD_0          0
 287 #define R300_FPI_INSTR_0        1
 288 #define R300_FPI_CMDSIZE        65
 289
 290 #define R300_AT_CMD_0           0
 291 #define R300_AT_ALPHA_TEST      1
 292 #define R300_AT_CMDSIZE         2
 293
 294 #define R300_BLD_CMD_0          0
 295 #define R300_BLD_CBLEND         1
 296 #define R300_BLD_ABLEND         2
 297 #define R300_BLD_CMDSIZE        3
 298
 299 #define R300_CMK_CMD_0          0
 300 #define R300_CMK_COLORMASK      1
 301 #define R300_CMK_CMDSIZE        2
 302
 303 #define R300_CB_CMD_0           0
 304 #define R300_CB_OFFSET          1
 305 #define R300_CB_CMD_1           2
 306 #define R300_CB_PITCH           3
 307 #define R300_CB_CMDSIZE         4
 308
 309 #define R300_ZC_CMD_0           0
 310 #define R300_ZC_CNTL_0          1
 311 #define R300_ZC_CNTL_1          2
 312 #define R300_ZC_CMDSIZE         3
 313
 314 #define R300_ZB_CMD_0           0
 315 #define R300_ZB_OFFSET          1
 316 #define R300_ZB_PITCH           2
 317 #define R300_ZB_CMDSIZE         3
 318
 319 #define R300_VPI_CMD_0          0
 320 #define R300_VPI_INSTR_0        1
 321 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 322
 323 #define R300_VPP_CMD_0          0
 324 #define R300_VPP_PARAM_0        1
 325 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 326
 327 #define R300_VPS_CMD_0          0
 328 #define R300_VPS_ZERO_0         1
 329 #define R300_VPS_ZERO_1         2
 330 #define R300_VPS_POINTSIZE      3
 331 #define R300_VPS_ZERO_3         4
 332 #define R300_VPS_CMDSIZE        5
 333
 334         /* the layout is common for all fields inside tex */
 335 #define R300_TEX_CMD_0          0
 336 #define R300_TEX_VALUE_0        1
 337 /* We don't really use this, instead specify mtu+1 dynamically
 338 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 339 */
 340
 341 /**
 342  * Cache for hardware register state.
 343  */
 344 struct r300_hw_state {
 345         struct r300_state_atom atomlist;
 346
 347         GLboolean       is_dirty;
 348         GLboolean       all_dirty;
 349         int             max_state_size; /* in dwords */
 350
 351         struct r300_state_atom vpt;     /* viewport (1D98) */
 352         struct r300_state_atom unk2080; /* (2080) */
 353         struct r300_state_atom ovf;     /* output vertex format (2090) */
 354         struct r300_state_atom vte;     /* (20B0) */
 355         struct r300_state_atom unk2134; /* (2134) */
 356         struct r300_state_atom unk2140; /* (2140) */
 357         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 358         struct r300_state_atom vic;     /* vap input control (2180) */
 359         struct r300_state_atom unk21DC; /* (21DC) */
 360         struct r300_state_atom unk221C; /* (221C) */
 361         struct r300_state_atom unk2220; /* (2220) */
 362         struct r300_state_atom unk2288; /* (2288) */
 363         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 364         struct r300_state_atom vof;     /* VAP output format register 0x4000 */
 365         struct r300_state_atom gb_enable; /* (4008) */
 366         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 367         struct r300_state_atom txe;     /* tex enable (4104) */
 368         struct r300_state_atom unk4200; /* (4200) */
 369         struct r300_state_atom unk4214; /* (4214) */
 370         struct r300_state_atom ps;      /* pointsize (421C) */
 371         struct r300_state_atom unk4230; /* (4230) */
 372         struct r300_state_atom unk4260; /* (4260) */
 373         struct r300_state_atom unk4274; /* (4274) */
 374         struct r300_state_atom unk4288; /* (4288) */
 375         struct r300_state_atom unk42A0; /* (42A0) */
 376         struct r300_state_atom unk42B4; /* (42B4) */
 377         struct r300_state_atom cul;     /* cull cntl (42B8) */
 378         struct r300_state_atom unk42C0; /* (42C0) */
 379         struct r300_state_atom rc;      /* rs control (4300) */
 380         struct r300_state_atom ri;      /* rs interpolators (4310) */
 381         struct r300_state_atom rr;      /* rs route (4330) */
 382         struct r300_state_atom unk43A4; /* (43A4) */
 383         struct r300_state_atom unk43E8; /* (43E8) */
 384         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 385         struct r300_state_atom unk46A4; /* (46A4) */
 386         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 387         struct r300_state_atom unk4BC0; /* (4BC0) */
 388         struct r300_state_atom unk4BC8; /* (4BC8) */
 389         struct r300_state_atom at;      /* alpha test (4BD4) */
 390         struct r300_state_atom unk4BD8; /* (4BD8) */
 391         struct r300_state_atom unk4E00; /* (4E00) */
 392         struct r300_state_atom bld;     /* blending (4E04) */
 393         struct r300_state_atom cmk;     /* colormask (4E0C) */
 394         struct r300_state_atom unk4E10; /* (4E10) */
 395         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 396         struct r300_state_atom unk4E50; /* (4E50) */
 397         struct r300_state_atom unk4E88; /* (4E88) */
 398         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 399         struct r300_state_atom zc;      /* z control (4F00) */
 400         struct r300_state_atom unk4F08; /* (4F08) */
 401         struct r300_state_atom unk4F10; /* (4F10) */
 402         struct r300_state_atom zb;      /* z buffer (4F20) */
 403         struct r300_state_atom unk4F28; /* (4F28) */
 404         struct r300_state_atom unk4F30; /* (4F30) */
 405         struct r300_state_atom unk4F44; /* (4F44) */
 406         struct r300_state_atom unk4F54; /* (4F54) */
 407
 408         struct r300_state_atom vpi;     /* vp instructions */
 409         struct r300_state_atom vpp;     /* vp parameters */
 410         struct r300_state_atom vps;     /* vertex point size (?) */
 411
 412                 /* 8 texture units */
 413                 /* the state is grouped by function and not by
 414                    texture unit. This makes single unit updates
 415                    really awkward - we are much better off
 416                    updating the whole thing at once */
 417         struct {
 418                 struct r300_state_atom filter;
 419                 struct r300_state_atom unknown1;
 420                 struct r300_state_atom size;
 421                 struct r300_state_atom format;
 422                 struct r300_state_atom offset;
 423                 struct r300_state_atom unknown4;
 424                 struct r300_state_atom unknown5;
 425                 } tex;
 426 };
 427
 428
 429 /**
 430  * This structure holds the command buffer while it is being constructed.
 431  *
 432  * The first batch of commands in the buffer is always the state that needs
 433  * to be re-emitted when the context is lost. This batch can be skipped
 434  * otherwise.
 435  */
 436 struct r300_cmdbuf {
 437         int             size;           /* DWORDs allocated for buffer */
 438         uint32_t*       cmd_buf;
 439         int             count_used;     /* DWORDs filled so far */
 440         int             count_reemit;   /* size of re-emission batch */
 441 };
 442
 443
 444 /**
 445  * State cache
 446  */
 447
 448 struct r300_depthbuffer_state {
 449         GLfloat scale;
 450 };
 451
 452 struct r300_state {
 453         struct r300_depthbuffer_state depth;
 454         struct r300_texture_state texture;
 455 };
 456
 457
 458 /**
 459  * R300 context structure.
 460  */
 461 struct r300_context {
 462         struct radeon_context radeon; /* parent class, must be first */
 463
 464         struct r300_hw_state hw;
 465         struct r300_cmdbuf cmdbuf;
 466         struct r300_state state;
 467
 468         /* Vertex buffers */
 469         int elt_count;  /* size of the buffer for vertices */
 470         int attrib_count; /* size of the buffer for vertex attributes.. Somehow it can be different ? */
 471
 472
 473         /* Vertex buffers
 474          */
 475         #if 0 /* we'll need it later, but not now */
 476         struct r300_ioctl ioctl;
 477         #endif
 478         struct r300_dma dma;
 479         GLboolean save_on_next_unlock;
 480
 481         /* Texture object bookkeeping
 482          */
 483         unsigned nr_heaps;
 484         driTexHeap *texture_heaps[R200_NR_TEX_HEAPS];
 485         driTextureObject swapped;
 486         int texture_depth;
 487         float initialMaxAnisotropy;
 488
 489         /* Clientdata textures;
 490          */
 491         GLuint prefer_gart_client_texturing;
 492
 493         /* TCL stuff
 494          */
 495         GLmatrix TexGenMatrix[R300_MAX_TEXTURE_UNITS];
 496         GLboolean recheck_texgen[R300_MAX_TEXTURE_UNITS];
 497         GLboolean TexGenNeedNormals[R300_MAX_TEXTURE_UNITS];
 498         GLuint TexMatEnabled;
 499         GLuint TexMatCompSel;
 500         GLuint TexGenEnabled;
 501         GLuint TexGenInputs;
 502         GLuint TexGenCompSel;
 503         GLmatrix tmpmat;
 504 };
 505
 506 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 507
 508 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 509 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 510                                    __DRIcontextPrivate * driContextPriv,
 511                                    void *sharedContextPrivate);
 512
 513 #endif                          /* __R300_CONTEXT_H__ */