2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
33 * Nicolai Haehnle <prefect_@gmx.net>
36 #ifndef __R300_CONTEXT_H__
37 #define __R300_CONTEXT_H__
39 #include "tnl/t_vertex.h"
41 #include "radeon_drm.h"
48 #include "radeon_context.h"
51 typedef struct r300_context r300ContextRec
;
52 typedef struct r300_context
*r300ContextPtr
;
54 #include "radeon_lock.h"
57 typedef GLuint
uint32_t;
58 typedef GLubyte
uint8_t;
61 static __inline__
uint32_t r300PackFloat32(float fl
)
63 union { float fl
; uint32_t u
; } u
;
70 * A block of hardware state.
72 * When check returns non-zero, the returned number of dwords must be
73 * copied verbatim into the command buffer in order to update a state atom
76 struct r300_state_atom
{
77 struct r300_state_atom
*next
, *prev
;
78 const char* name
; /* for debug */
79 int cmd_size
; /* maximum size in dwords */
80 GLuint idx
; /* index in an array (e.g. textures) */
84 int (*check
)(r300ContextPtr
, struct r300_state_atom
* atom
);
88 #define R300_VPT_CMD_0 0
89 #define R300_VPT_XSCALE 1
90 #define R300_VPT_XOFFSET 2
91 #define R300_VPT_YSCALE 3
92 #define R300_VPT_YOFFSET 4
93 #define R300_VPT_ZSCALE 5
94 #define R300_VPT_ZOFFSET 6
95 #define R300_VPT_CMDSIZE 7
97 #define R300_OVF_CMD_0 0
98 #define R300_OVF_FMT_0 1
99 #define R300_OVF_FMT_1 2
100 #define R300_OVF_CMDSIZE 3
102 #define R300_VIR_CMD_0 0 /* vir is variable size (at least 1) */
103 #define R300_VIR_CNTL_0 1
104 #define R300_VIR_CNTL_1 2
105 #define R300_VIR_CNTL_2 3
106 #define R300_VIR_CNTL_3 4
107 #define R300_VIR_CNTL_4 5
108 #define R300_VIR_CNTL_5 6
109 #define R300_VIR_CNTL_6 7
110 #define R300_VIR_CNTL_7 8
111 #define R300_VIR_CMDSIZE 9
113 #define R300_VIC_CMD_0 0
114 #define R300_VIC_CNTL_0 1
115 #define R300_VIC_CNTL_1 2
116 #define R300_VIC_CMDSIZE 3
118 #define R300_PVS_CMD_0 0
119 #define R300_PVS_CNTL_1 1
120 #define R300_PVS_CNTL_2 2
121 #define R300_PVS_CNTL_3 3
122 #define R300_PVS_CMDSIZE 4
124 #define R300_TXE_CMD_0 0
125 #define R300_TXE_ENABLE 1
126 #define R300_TXE_CMDSIZE 2
128 #define R300_PS_CMD_0 0
129 #define R300_PS_POINTSIZE 1
130 #define R300_PS_CMDSIZE 2
132 #define R300_CUL_CMD_0 0
133 #define R300_CUL_CULL 1
134 #define R300_CUL_CMDSIZE 2
136 #define R300_RC_CMD_0 0
137 #define R300_RC_CNTL_0 1
138 #define R300_RC_CNTL_1 2
139 #define R300_RC_CMDSIZE 3
141 #define R300_RI_CMD_0 0
142 #define R300_RI_INTERP_0 1
143 #define R300_RI_INTERP_1 2
144 #define R300_RI_INTERP_2 3
145 #define R300_RI_INTERP_3 4
146 #define R300_RI_INTERP_4 5
147 #define R300_RI_INTERP_5 6
148 #define R300_RI_INTERP_6 7
149 #define R300_RI_INTERP_7 8
150 #define R300_RI_CMDSIZE 9
152 #define R300_RR_CMD_0 0 /* rr is variable size (at least 1) */
153 #define R300_RR_ROUTE_0 1
154 #define R300_RR_ROUTE_1 2
155 #define R300_RR_ROUTE_2 3
156 #define R300_RR_ROUTE_3 4
157 #define R300_RR_ROUTE_4 5
158 #define R300_RR_ROUTE_5 6
159 #define R300_RR_ROUTE_6 7
160 #define R300_RR_ROUTE_7 8
161 #define R300_RR_CMDSIZE 9
163 #define R300_FP_CMD_0 0
164 #define R300_FP_CNTL0 1
165 #define R300_FP_CNTL1 2
166 #define R300_FP_CNTL2 3
167 #define R300_FP_CMD_1 4
168 #define R300_FP_NODE0 5
169 #define R300_FP_NODE1 6
170 #define R300_FP_NODE2 7
171 #define R300_FP_NODE3 8
172 #define R300_FP_CMDSIZE 9
174 #define R300_FPI_CMD_0 0
175 #define R300_FPI_INSTR_0 1
176 #define R300_FPI_CMDSIZE 65
178 #define R300_AT_CMD_0 0
179 #define R300_AT_ALPHA_TEST 1
180 #define R300_AT_CMDSIZE 2
182 #define R300_BLD_CMD_0 0
183 #define R300_BLD_CBLEND 1
184 #define R300_BLD_ABLEND 2
185 #define R300_BLD_CMDSIZE 3
187 #define R300_CMK_CMD_0 0
188 #define R300_CMK_COLORMASK 1
189 #define R300_CMK_CMDSIZE 2
191 #define R300_CB_CMD_0 0
192 #define R300_CB_OFFSET 1
193 #define R300_CB_CMD_1 2
194 #define R300_CB_PITCH 3
195 #define R300_CB_CMDSIZE 4
197 #define R300_ZC_CMD_0 0
198 #define R300_ZC_CNTL_0 1
199 #define R300_ZC_CNTL_1 2
200 #define R300_ZC_CMDSIZE 3
202 #define R300_ZB_CMD_0 0
203 #define R300_ZB_OFFSET 1
204 #define R300_ZB_PITCH 2
205 #define R300_ZB_CMDSIZE 3
207 #define R300_VPI_CMD_0 0
208 #define R300_VPI_INSTR_0 1
209 #define R300_VPI_CMDSIZE 1025 /* 256 16 byte instructions */
211 #define R300_VPP_CMD_0 0
212 #define R300_VPP_PARAM_0 1
213 #define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */
215 #define R300_VPS_CMD_0 0
216 #define R300_VPS_ZERO_0 1
217 #define R300_VPS_ZERO_1 2
218 #define R300_VPS_POINTSIZE 3
219 #define R300_VPS_ZERO_3 4
220 #define R300_VPS_CMDSIZE 5
223 * Cache for hardware register state.
225 struct r300_hw_state
{
226 struct r300_state_atom atomlist
;
230 int max_state_size
; /* in dwords */
232 struct r300_state_atom vpt
; /* viewport (1D98) */
233 struct r300_state_atom unk2080
; /* (2080) */
234 struct r300_state_atom ovf
; /* output vertex format (2090) */
235 struct r300_state_atom unk20B0
; /* (20B0) */
236 struct r300_state_atom unk2134
; /* (2134) */
237 struct r300_state_atom unk2140
; /* (2140) */
238 struct r300_state_atom vir
[2]; /* vap input route (2150/21E0) */
239 struct r300_state_atom vic
; /* vap input control (2180) */
240 struct r300_state_atom unk21DC
; /* (21DC) */
241 struct r300_state_atom unk221C
; /* (221C) */
242 struct r300_state_atom unk2220
; /* (2220) */
243 struct r300_state_atom unk2288
; /* (2288) */
244 struct r300_state_atom pvs
; /* pvs_cntl (22D0) */
245 struct r300_state_atom unk4008
; /* (4008) */
246 struct r300_state_atom unk4010
; /* (4010) */
247 struct r300_state_atom txe
; /* tex enable (4104) */
248 struct r300_state_atom unk4200
; /* (4200) */
249 struct r300_state_atom unk4214
; /* (4214) */
250 struct r300_state_atom ps
; /* pointsize (421C) */
251 struct r300_state_atom unk4230
; /* (4230) */
252 struct r300_state_atom unk4260
; /* (4260) */
253 struct r300_state_atom unk4274
; /* (4274) */
254 struct r300_state_atom unk4288
; /* (4288) */
255 struct r300_state_atom unk42A0
; /* (42A0) */
256 struct r300_state_atom unk42B4
; /* (42B4) */
257 struct r300_state_atom cul
; /* cull cntl (42B8) */
258 struct r300_state_atom unk42C0
; /* (42C0) */
259 struct r300_state_atom rc
; /* rs control (4300) */
260 struct r300_state_atom ri
; /* rs interpolators (4310) */
261 struct r300_state_atom rr
; /* rs route (4330) */
262 struct r300_state_atom unk43A4
; /* (43A4) */
263 struct r300_state_atom unk43E8
; /* (43E8) */
264 struct r300_state_atom fp
; /* fragment program cntl + nodes (4600) */
265 struct r300_state_atom unk46A4
; /* (46A4) */
266 struct r300_state_atom fpi
[4]; /* fp instructions (46C0/47C0/48C0/49C0) */
267 struct r300_state_atom unk4BC0
; /* (4BC0) */
268 struct r300_state_atom unk4BC8
; /* (4BC8) */
269 struct r300_state_atom at
; /* alpha test (4BD4) */
270 struct r300_state_atom unk4BD8
; /* (4BD8) */
271 struct r300_state_atom unk4E00
; /* (4E00) */
272 struct r300_state_atom bld
; /* blending (4E04) */
273 struct r300_state_atom cmk
; /* colormask (4E0C) */
274 struct r300_state_atom unk4E10
; /* (4E10) */
275 struct r300_state_atom cb
; /* colorbuffer (4E28) */
276 struct r300_state_atom unk4E50
; /* (4E50) */
277 struct r300_state_atom unk4E88
; /* (4E88) */
278 struct r300_state_atom zc
; /* z control (4F00) */
279 struct r300_state_atom unk4F08
; /* (4F08) */
280 struct r300_state_atom unk4F10
; /* (4F10) */
281 struct r300_state_atom zb
; /* z buffer (4F20) */
282 struct r300_state_atom unk4F28
; /* (4F28) */
283 struct r300_state_atom unk4F30
; /* (4F30) */
284 struct r300_state_atom unk4F44
; /* (4F44) */
285 struct r300_state_atom unk4F54
; /* (4F54) */
287 struct r300_state_atom vpi
; /* vp instructions */
288 struct r300_state_atom vpp
; /* vp parameters */
289 struct r300_state_atom vps
; /* vertex point size (?) */
294 * This structure holds the command buffer while it is being constructed.
296 * The first batch of commands in the buffer is always the state that needs
297 * to be re-emitted when the context is lost. This batch can be skipped
301 int size
; /* DWORDs allocated for buffer */
303 int count_used
; /* DWORDs filled so far */
304 int count_reemit
; /* size of re-emission batch */
312 struct r300_depthbuffer_state
{
317 struct r300_depthbuffer_state depth
;
322 * R300 context structure.
324 struct r300_context
{
325 struct radeon_context radeon
; /* parent class, must be first */
327 struct r300_hw_state hw
;
328 struct r300_cmdbuf cmdbuf
;
329 struct r300_state state
;
332 int elt_count
; /* size of the buffer for vertices */
333 int attrib_count
; /* size of the buffer for vertex attributes.. Somehow it can be different ? */
337 #define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx))
339 extern void r300DestroyContext(__DRIcontextPrivate
* driContextPriv
);
340 extern GLboolean
r300CreateContext(const __GLcontextModes
* glVisual
,
341 __DRIcontextPrivate
* driContextPriv
,
342 void *sharedContextPrivate
);
344 #endif /* __R300_CONTEXT_H__ */