src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45 #include "radeon_common.h"
  46
  47 #include "main/macros.h"
  48 #include "main/mtypes.h"
  49 #include "main/colormac.h"
  50
  51 struct r300_context;
  52 typedef struct r300_context r300ContextRec;
  53 typedef struct r300_context *r300ContextPtr;
  54
  55
  56 #include "main/mm.h"
  57
  58 /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  59    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  60    with other compilers ... GLUE!
  61 */
  62 #define WARN_ONCE(a, ...)       { \
  63         static int warn##__LINE__=1; \
  64         if(warn##__LINE__){ \
  65                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  66                 fprintf(stderr, "File %s function %s line %d\n", \
  67                         __FILE__, __FUNCTION__, __LINE__); \
  68                 fprintf(stderr,  a, ## __VA_ARGS__);\
  69                 fprintf(stderr, "***************************************************************************\n"); \
  70                 warn##__LINE__=0;\
  71                 } \
  72         }
  73
  74 #include "r300_vertprog.h"
  75 #include "r500_fragprog.h"
  76
  77
  78
  79 /* The blit width for texture uploads
  80  */
  81 #define R300_BLIT_WIDTH_BYTES 1024
  82 #define R300_MAX_TEXTURE_UNITS 8
  83
  84 struct r300_texture_state {
  85         int tc_count;           /* number of incoming texture coordinates from VAP */
  86 };
  87
  88
  89 #define R300_VPT_CMD_0          0
  90 #define R300_VPT_XSCALE         1
  91 #define R300_VPT_XOFFSET        2
  92 #define R300_VPT_YSCALE         3
  93 #define R300_VPT_YOFFSET        4
  94 #define R300_VPT_ZSCALE         5
  95 #define R300_VPT_ZOFFSET        6
  96 #define R300_VPT_CMDSIZE        7
  97
  98 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
  99 #define R300_VIR_CNTL_0         1
 100 #define R300_VIR_CNTL_1         2
 101 #define R300_VIR_CNTL_2         3
 102 #define R300_VIR_CNTL_3         4
 103 #define R300_VIR_CNTL_4         5
 104 #define R300_VIR_CNTL_5         6
 105 #define R300_VIR_CNTL_6         7
 106 #define R300_VIR_CNTL_7         8
 107 #define R300_VIR_CMDSIZE        9
 108
 109 #define R300_VIC_CMD_0          0
 110 #define R300_VIC_CNTL_0         1
 111 #define R300_VIC_CNTL_1         2
 112 #define R300_VIC_CMDSIZE        3
 113
 114 #define R300_VOF_CMD_0          0
 115 #define R300_VOF_CNTL_0         1
 116 #define R300_VOF_CNTL_1         2
 117 #define R300_VOF_CMDSIZE        3
 118
 119 #define R300_PVS_CMD_0          0
 120 #define R300_PVS_CNTL_1         1
 121 #define R300_PVS_CNTL_2         2
 122 #define R300_PVS_CNTL_3         3
 123 #define R300_PVS_CMDSIZE        4
 124
 125 #define R300_GB_MISC_CMD_0              0
 126 #define R300_GB_MISC_MSPOS_0            1
 127 #define R300_GB_MISC_MSPOS_1            2
 128 #define R300_GB_MISC_TILE_CONFIG        3
 129 #define R300_GB_MISC_SELECT             4
 130 #define R300_GB_MISC_AA_CONFIG          5
 131 #define R300_GB_MISC_CMDSIZE            6
 132
 133 #define R300_TXE_CMD_0          0
 134 #define R300_TXE_ENABLE         1
 135 #define R300_TXE_CMDSIZE        2
 136
 137 #define R300_PS_CMD_0           0
 138 #define R300_PS_POINTSIZE       1
 139 #define R300_PS_CMDSIZE         2
 140
 141 #define R300_ZBS_CMD_0          0
 142 #define R300_ZBS_T_FACTOR       1
 143 #define R300_ZBS_T_CONSTANT     2
 144 #define R300_ZBS_W_FACTOR       3
 145 #define R300_ZBS_W_CONSTANT     4
 146 #define R300_ZBS_CMDSIZE        5
 147
 148 #define R300_CUL_CMD_0          0
 149 #define R300_CUL_CULL           1
 150 #define R300_CUL_CMDSIZE        2
 151
 152 #define R300_RC_CMD_0           0
 153 #define R300_RC_CNTL_0          1
 154 #define R300_RC_CNTL_1          2
 155 #define R300_RC_CMDSIZE         3
 156
 157 #define R300_RI_CMD_0           0
 158 #define R300_RI_INTERP_0        1
 159 #define R300_RI_INTERP_1        2
 160 #define R300_RI_INTERP_2        3
 161 #define R300_RI_INTERP_3        4
 162 #define R300_RI_INTERP_4        5
 163 #define R300_RI_INTERP_5        6
 164 #define R300_RI_INTERP_6        7
 165 #define R300_RI_INTERP_7        8
 166 #define R300_RI_CMDSIZE         9
 167
 168 #define R500_RI_CMDSIZE        17
 169
 170 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 171 #define R300_RR_INST_0          1
 172 #define R300_RR_INST_1          2
 173 #define R300_RR_INST_2          3
 174 #define R300_RR_INST_3          4
 175 #define R300_RR_INST_4          5
 176 #define R300_RR_INST_5          6
 177 #define R300_RR_INST_6          7
 178 #define R300_RR_INST_7          8
 179 #define R300_RR_CMDSIZE         9
 180
 181 #define R300_FP_CMD_0           0
 182 #define R300_FP_CNTL0           1
 183 #define R300_FP_CNTL1           2
 184 #define R300_FP_CNTL2           3
 185 #define R300_FP_CMD_1           4
 186 #define R300_FP_NODE0           5
 187 #define R300_FP_NODE1           6
 188 #define R300_FP_NODE2           7
 189 #define R300_FP_NODE3           8
 190 #define R300_FP_CMDSIZE         9
 191
 192 #define R500_FP_CMD_0           0
 193 #define R500_FP_CNTL            1
 194 #define R500_FP_PIXSIZE         2
 195 #define R500_FP_CMD_1           3
 196 #define R500_FP_CODE_ADDR       4
 197 #define R500_FP_CODE_RANGE      5
 198 #define R500_FP_CODE_OFFSET     6
 199 #define R500_FP_CMD_2           7
 200 #define R500_FP_FC_CNTL         8
 201 #define R500_FP_CMDSIZE         9
 202
 203 #define R300_FPT_CMD_0          0
 204 #define R300_FPT_INSTR_0        1
 205 #define R300_FPT_CMDSIZE        65
 206
 207 #define R300_FPI_CMD_0          0
 208 #define R300_FPI_INSTR_0        1
 209 #define R300_FPI_CMDSIZE        65
 210 /* R500 has space for 512 instructions - 6 dwords per instruction */
 211 #define R500_FPI_CMDSIZE        (512*6+1)
 212
 213 #define R300_FPP_CMD_0          0
 214 #define R300_FPP_PARAM_0        1
 215 #define R300_FPP_CMDSIZE        (32*4+1)
 216 /* R500 has spcae for 256 constants - 4 dwords per constant */
 217 #define R500_FPP_CMDSIZE        (256*4+1)
 218
 219 #define R300_FOGS_CMD_0         0
 220 #define R300_FOGS_STATE         1
 221 #define R300_FOGS_CMDSIZE       2
 222
 223 #define R300_FOGC_CMD_0         0
 224 #define R300_FOGC_R             1
 225 #define R300_FOGC_G             2
 226 #define R300_FOGC_B             3
 227 #define R300_FOGC_CMDSIZE       4
 228
 229 #define R300_FOGP_CMD_0         0
 230 #define R300_FOGP_SCALE         1
 231 #define R300_FOGP_START         2
 232 #define R300_FOGP_CMDSIZE       3
 233
 234 #define R300_AT_CMD_0           0
 235 #define R300_AT_ALPHA_TEST      1
 236 #define R300_AT_UNKNOWN         2
 237 #define R300_AT_CMDSIZE         3
 238
 239 #define R300_BLD_CMD_0          0
 240 #define R300_BLD_CBLEND         1
 241 #define R300_BLD_ABLEND         2
 242 #define R300_BLD_CMDSIZE        3
 243
 244 #define R300_CMK_CMD_0          0
 245 #define R300_CMK_COLORMASK      1
 246 #define R300_CMK_CMDSIZE        2
 247
 248 #define R300_CB_CMD_0           0
 249 #define R300_CB_OFFSET          1
 250 #define R300_CB_CMD_1           2
 251 #define R300_CB_PITCH           3
 252 #define R300_CB_CMDSIZE         4
 253
 254 #define R300_ZS_CMD_0           0
 255 #define R300_ZS_CNTL_0          1
 256 #define R300_ZS_CNTL_1          2
 257 #define R300_ZS_CNTL_2          3
 258 #define R300_ZS_CMDSIZE         4
 259
 260 #define R300_ZB_CMD_0           0
 261 #define R300_ZB_OFFSET          1
 262 #define R300_ZB_PITCH           2
 263 #define R300_ZB_CMDSIZE         3
 264
 265 #define R300_VAP_CNTL_FLUSH     0
 266 #define R300_VAP_CNTL_FLUSH_1   1
 267 #define R300_VAP_CNTL_CMD       2
 268 #define R300_VAP_CNTL_INSTR     3
 269 #define R300_VAP_CNTL_SIZE      4
 270
 271 #define R300_VPI_CMD_0          0
 272 #define R300_VPI_INSTR_0        1
 273 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 274
 275 #define R300_VPP_CMD_0          0
 276 #define R300_VPP_PARAM_0        1
 277 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 278
 279 #define R300_VPUCP_CMD_0                0
 280 #define R300_VPUCP_X            1
 281 #define R300_VPUCP_Y            2
 282 #define R300_VPUCP_Z            3
 283 #define R300_VPUCP_W            4
 284 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 285
 286 #define R300_VPS_CMD_0          0
 287 #define R300_VPS_ZERO_0         1
 288 #define R300_VPS_ZERO_1         2
 289 #define R300_VPS_POINTSIZE      3
 290 #define R300_VPS_ZERO_3         4
 291 #define R300_VPS_CMDSIZE        5
 292
 293         /* the layout is common for all fields inside tex */
 294 #define R300_TEX_CMD_0          0
 295 #define R300_TEX_VALUE_0        1
 296 /* We don't really use this, instead specify mtu+1 dynamically
 297 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 298 */
 299
 300 /**
 301  * Cache for hardware register state.
 302  */
 303 struct r300_hw_state {
 304         struct radeon_state_atom vpt;   /* viewport (1D98) */
 305         struct radeon_state_atom vap_cntl;
 306         struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
 307         struct radeon_state_atom vof;   /* VAP output format register 0x2090 */
 308         struct radeon_state_atom vte;   /* (20B0) */
 309         struct radeon_state_atom vap_vf_max_vtx_indx;   /* Maximum Vertex Indx Clamp (2134) */
 310         struct radeon_state_atom vap_cntl_status;
 311         struct radeon_state_atom vir[2];        /* vap input route (2150/21E0) */
 312         struct radeon_state_atom vic;   /* vap input control (2180) */
 313         struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 314         struct radeon_state_atom vap_clip_cntl;
 315         struct radeon_state_atom vap_clip;
 316         struct radeon_state_atom vap_pvs_vtx_timeout_reg;       /* Vertex timeout register (2288) */
 317         struct radeon_state_atom pvs;   /* pvs_cntl (22D0) */
 318         struct radeon_state_atom gb_enable;     /* (4008) */
 319         struct radeon_state_atom gb_misc;       /* Multisampling position shifts ? (4010) */
 320         struct radeon_state_atom ga_point_s0;   /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 321         struct radeon_state_atom ga_triangle_stipple;   /* (4214) */
 322         struct radeon_state_atom ps;    /* pointsize (421C) */
 323         struct radeon_state_atom ga_point_minmax;       /* (4230) */
 324         struct radeon_state_atom lcntl; /* line control */
 325         struct radeon_state_atom ga_line_stipple;       /* (4260) */
 326         struct radeon_state_atom shade;
 327         struct radeon_state_atom polygon_mode;
 328         struct radeon_state_atom fogp;  /* fog parameters (4294) */
 329         struct radeon_state_atom ga_soft_reset; /* (429C) */
 330         struct radeon_state_atom zbias_cntl;
 331         struct radeon_state_atom zbs;   /* zbias (42A4) */
 332         struct radeon_state_atom occlusion_cntl;
 333         struct radeon_state_atom cul;   /* cull cntl (42B8) */
 334         struct radeon_state_atom su_depth_scale;        /* (42C0) */
 335         struct radeon_state_atom rc;    /* rs control (4300) */
 336         struct radeon_state_atom ri;    /* rs interpolators (4310) */
 337         struct radeon_state_atom rr;    /* rs route (4330) */
 338         struct radeon_state_atom sc_hyperz;     /* (43A4) */
 339         struct radeon_state_atom sc_screendoor; /* (43E8) */
 340         struct radeon_state_atom fp;    /* fragment program cntl + nodes (4600) */
 341         struct radeon_state_atom fpt;   /* texi - (4620) */
 342         struct radeon_state_atom us_out_fmt;    /* (46A4) */
 343         struct radeon_state_atom r500fp;        /* r500 fp instructions */
 344         struct radeon_state_atom r500fp_const;  /* r500 fp constants */
 345         struct radeon_state_atom fpi[4];        /* fp instructions (46C0/47C0/48C0/49C0) */
 346         struct radeon_state_atom fogs;  /* fog state (4BC0) */
 347         struct radeon_state_atom fogc;  /* fog color (4BC8) */
 348         struct radeon_state_atom at;    /* alpha test (4BD4) */
 349         struct radeon_state_atom fg_depth_src;  /* (4BD8) */
 350         struct radeon_state_atom fpp;   /* 0x4C00 and following */
 351         struct radeon_state_atom rb3d_cctl;     /* (4E00) */
 352         struct radeon_state_atom bld;   /* blending (4E04) */
 353         struct radeon_state_atom cmk;   /* colormask (4E0C) */
 354         struct radeon_state_atom blend_color;   /* constant blend color */
 355         struct radeon_state_atom rop;   /* ropcntl */
 356         struct radeon_state_atom cb;    /* colorbuffer (4E28) */
 357         struct radeon_state_atom rb3d_dither_ctl;       /* (4E50) */
 358         struct radeon_state_atom rb3d_aaresolve_ctl;    /* (4E88) */
 359         struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold;  /* (4E88) I saw it only written on RV350 hardware..  */
 360         struct radeon_state_atom zs;    /* zstencil control (4F00) */
 361         struct radeon_state_atom zstencil_format;
 362         struct radeon_state_atom zb;    /* z buffer (4F20) */
 363         struct radeon_state_atom zb_depthclearvalue;    /* (4F28) */
 364         struct radeon_state_atom unk4F30;       /* (4F30) */
 365         struct radeon_state_atom zb_hiz_offset; /* (4F44) */
 366         struct radeon_state_atom zb_hiz_pitch;  /* (4F54) */
 367
 368         struct radeon_state_atom vpi;   /* vp instructions */
 369         struct radeon_state_atom vpp;   /* vp parameters */
 370         struct radeon_state_atom vps;   /* vertex point size (?) */
 371         struct radeon_state_atom vpucp[6];      /* vp user clip plane - 6 */
 372         /* 8 texture units */
 373         /* the state is grouped by function and not by
 374            texture unit. This makes single unit updates
 375            really awkward - we are much better off
 376            updating the whole thing at once */
 377         struct {
 378                 struct radeon_state_atom filter;
 379                 struct radeon_state_atom filter_1;
 380                 struct radeon_state_atom size;
 381                 struct radeon_state_atom format;
 382                 struct radeon_state_atom pitch;
 383                 struct radeon_state_atom offset;
 384                 struct radeon_state_atom chroma_key;
 385                 struct radeon_state_atom border_color;
 386         } tex;
 387         struct radeon_state_atom txe;   /* tex enable (4104) */
 388
 389         radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
 390 };
 391
 392 /**
 393  * State cache
 394  */
 395
 396 /* Vertex shader state */
 397
 398 /* Perhaps more if we store programs in vmem? */
 399 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 400 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 401
 402 /* Can be tested with colormat currently. */
 403 #define VSF_MAX_FRAGMENT_TEMPS (14)
 404
 405 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 406 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 407
 408 struct r300_vertex_shader_fragment {
 409         int length;
 410         union {
 411                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 412                 float f[VSF_MAX_FRAGMENT_LENGTH];
 413                 GLuint i[VSF_MAX_FRAGMENT_LENGTH];
 414         } body;
 415 };
 416
 417 struct r300_vertex_shader_state {
 418         struct r300_vertex_shader_fragment program;
 419 };
 420
 421 extern int hw_tcl_on;
 422
 423 #define COLOR_IS_RGBA
 424 #define TAG(x) r300##x
 425 #include "tnl_dd/t_dd_vertex.h"
 426 #undef TAG
 427
 428 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 429 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 430
 431 /* Should but doesnt work */
 432 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 433
 434 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 435  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 436  */
 437
 438 struct r300_vertex_program_key {
 439         GLuint InputsRead;
 440         GLuint OutputsWritten;
 441         GLuint OutputsAdded;
 442 };
 443
 444 struct r300_vertex_program {
 445         struct r300_vertex_program *next;
 446         struct r300_vertex_program_key key;
 447         int translated;
 448
 449         struct r300_vertex_shader_fragment program;
 450
 451         int pos_end;
 452         int num_temporaries;    /* Number of temp vars used by program */
 453         int wpos_idx;
 454         int inputs[VERT_ATTRIB_MAX];
 455         int outputs[VERT_RESULT_MAX];
 456         int native;
 457         int ref_count;
 458         int use_ref_count;
 459 };
 460
 461 struct r300_vertex_program_cont {
 462         struct gl_vertex_program mesa_program;  /* Must be first */
 463         struct r300_vertex_shader_fragment params;
 464         struct r300_vertex_program *progs;
 465 };
 466
 467 #define PFS_MAX_ALU_INST        64
 468 #define PFS_MAX_TEX_INST        64
 469 #define PFS_MAX_TEX_INDIRECT 4
 470 #define PFS_NUM_TEMP_REGS       32
 471 #define PFS_NUM_CONST_REGS      16
 472
 473 struct r300_pfs_compile_state;
 474
 475
 476 /**
 477  * Stores state that influences the compilation of a fragment program.
 478  */
 479 struct r300_fragment_program_external_state {
 480         struct {
 481                 /**
 482                  * If the sampler is used as a shadow sampler,
 483                  * this field is:
 484                  *  0 - GL_LUMINANCE
 485                  *  1 - GL_INTENSITY
 486                  *  2 - GL_ALPHA
 487                  * depending on the depth texture mode.
 488                  */
 489                 GLuint depth_texture_mode : 2;
 490
 491                 /**
 492                  * If the sampler is used as a shadow sampler,
 493                  * this field is (texture_compare_func - GL_NEVER).
 494                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 495                  *
 496                  * Otherwise, this field is 0.
 497                  */
 498                 GLuint texture_compare_func : 3;
 499         } unit[16];
 500 };
 501
 502
 503 struct r300_fragment_program_node {
 504         int tex_offset; /**< first tex instruction */
 505         int tex_end; /**< last tex instruction, relative to tex_offset */
 506         int alu_offset; /**< first ALU instruction */
 507         int alu_end; /**< last ALU instruction, relative to alu_offset */
 508         int flags;
 509 };
 510
 511 /**
 512  * Stores an R300 fragment program in its compiled-to-hardware form.
 513  */
 514 struct r300_fragment_program_code {
 515         struct {
 516                 int length; /**< total # of texture instructions used */
 517                 GLuint inst[PFS_MAX_TEX_INST];
 518         } tex;
 519
 520         struct {
 521                 int length; /**< total # of ALU instructions used */
 522                 struct {
 523                         GLuint inst0;
 524                         GLuint inst1;
 525                         GLuint inst2;
 526                         GLuint inst3;
 527                 } inst[PFS_MAX_ALU_INST];
 528         } alu;
 529
 530         struct r300_fragment_program_node node[4];
 531         int cur_node;
 532         int first_node_has_tex;
 533
 534         /**
 535          * Remember which program register a given hardware constant
 536          * belongs to.
 537          */
 538         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 539         int const_nr;
 540
 541         int max_temp_idx;
 542 };
 543
 544 /**
 545  * Store everything about a fragment program that is needed
 546  * to render with that program.
 547  */
 548 struct r300_fragment_program {
 549         struct gl_fragment_program mesa_program;
 550
 551         GLboolean translated;
 552         GLboolean error;
 553
 554         struct r300_fragment_program_external_state state;
 555         struct r300_fragment_program_code code;
 556
 557         GLboolean WritesDepth;
 558         GLuint optimization;
 559 };
 560
 561 struct r500_pfs_compile_state;
 562
 563 struct r500_fragment_program_external_state {
 564         struct {
 565                 /**
 566                  * If the sampler is used as a shadow sampler,
 567                  * this field is:
 568                  *  0 - GL_LUMINANCE
 569                  *  1 - GL_INTENSITY
 570                  *  2 - GL_ALPHA
 571                  * depending on the depth texture mode.
 572                  */
 573                 GLuint depth_texture_mode : 2;
 574
 575                 /**
 576                  * If the sampler is used as a shadow sampler,
 577                  * this field is (texture_compare_func - GL_NEVER).
 578                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 579                  *
 580                  * Otherwise, this field is 0.
 581                  */
 582                 GLuint texture_compare_func : 3;
 583         } unit[16];
 584 };
 585
 586 struct r500_fragment_program_code {
 587         struct {
 588                 GLuint inst0;
 589                 GLuint inst1;
 590                 GLuint inst2;
 591                 GLuint inst3;
 592                 GLuint inst4;
 593                 GLuint inst5;
 594         } inst[512];
 595
 596         int inst_offset;
 597         int inst_end;
 598
 599         /**
 600          * Remember which program register a given hardware constant
 601          * belongs to.
 602          */
 603         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 604         int const_nr;
 605
 606         int max_temp_idx;
 607 };
 608
 609 struct r500_fragment_program {
 610         struct gl_fragment_program mesa_program;
 611
 612         GLcontext *ctx;
 613         GLboolean translated;
 614         GLboolean error;
 615
 616         struct r500_fragment_program_external_state state;
 617         struct r500_fragment_program_code code;
 618
 619         GLboolean writes_depth;
 620
 621         GLuint optimization;
 622 };
 623
 624 #define R300_MAX_AOS_ARRAYS             16
 625
 626 #define REG_COORDS      0
 627 #define REG_COLOR0      1
 628 #define REG_TEX0        2
 629
 630 struct r300_state {
 631         struct r300_texture_state texture;
 632         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 633         struct r300_vertex_shader_state vertex_shader;
 634
 635
 636         DECLARE_RENDERINPUTS(render_inputs_bitset);     /* actual render inputs that R300 was configured for.
 637                                                            They are the same as tnl->render_inputs for fixed pipeline */
 638
 639 };
 640
 641 #define R300_FALLBACK_NONE 0
 642 #define R300_FALLBACK_TCL 1
 643 #define R300_FALLBACK_RAST 2
 644
 645 /* r300_swtcl.c
 646  */
 647 struct r300_swtcl_info {
 648   /*
 649     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 650     */
 651    GLuint coloroffset;
 652
 653    /**
 654     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 655     */
 656    GLuint specoffset;
 657
 658    struct vertex_attribute{
 659        GLuint attr;
 660        GLubyte format;
 661        GLubyte dst_loc;
 662        GLuint swizzle;
 663        GLubyte write_mask;
 664    } vert_attrs[VERT_ATTRIB_MAX];
 665
 666    GLubyte vertex_attr_count;
 667 };
 668
 669
 670 /**
 671  * \brief R300 context structure.
 672  */
 673 struct r300_context {
 674         struct radeon_context radeon;   /* parent class, must be first */
 675
 676         struct r300_hw_state hw;
 677
 678         struct r300_state state;
 679         struct gl_vertex_program *curr_vp;
 680         struct r300_vertex_program *selected_vp;
 681
 682         /* Vertex buffers
 683          */
 684         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 685         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 686
 687         GLboolean disable_lowimpact_fallback;
 688
 689         struct r300_swtcl_info swtcl;
 690         GLboolean vap_flush_needed;
 691 };
 692
 693 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 694
 695 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 696 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 697                                    __DRIcontextPrivate * driContextPriv,
 698                                    void *sharedContextPrivate);
 699
 700 extern void r300SelectVertexShader(r300ContextPtr r300);
 701 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 702 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 703                                       struct r300_vertex_program_cont *vp,
 704                                       float *dst);
 705
 706 #define RADEON_D_CAPTURE 0
 707 #define RADEON_D_PLAYBACK 1
 708 #define RADEON_D_PLAYBACK_RAW 2
 709 #define RADEON_D_T 3
 710
 711 #define r300PackFloat32 radeonPackFloat32
 712 #define r300PackFloat24 radeonPackFloat24
 713
 714 #endif                          /* __R300_CONTEXT_H__ */