src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45 #include "radeon_common.h"
  46
  47 #include "main/macros.h"
  48 #include "main/mtypes.h"
  49 #include "main/colormac.h"
  50
  51 struct r300_context;
  52 typedef struct r300_context r300ContextRec;
  53 typedef struct r300_context *r300ContextPtr;
  54
  55
  56 #include "main/mm.h"
  57
  58 /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  59    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  60    with other compilers ... GLUE!
  61 */
  62 #define WARN_ONCE(a, ...)       { \
  63         static int warn##__LINE__=1; \
  64         if(warn##__LINE__){ \
  65                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  66                 fprintf(stderr, "File %s function %s line %d\n", \
  67                         __FILE__, __FUNCTION__, __LINE__); \
  68                 fprintf(stderr,  a, ## __VA_ARGS__);\
  69                 fprintf(stderr, "***************************************************************************\n"); \
  70                 warn##__LINE__=0;\
  71                 } \
  72         }
  73
  74 #include "r300_vertprog.h"
  75 #include "r500_fragprog.h"
  76
  77
  78
  79 /************ DMA BUFFERS **************/
  80
  81 /* The blit width for texture uploads
  82  */
  83 #define R300_BLIT_WIDTH_BYTES 1024
  84 #define R300_MAX_TEXTURE_UNITS 8
  85
  86 struct r300_texture_state {
  87         int tc_count;           /* number of incoming texture coordinates from VAP */
  88 };
  89
  90
  91 #define R300_VPT_CMD_0          0
  92 #define R300_VPT_XSCALE         1
  93 #define R300_VPT_XOFFSET        2
  94 #define R300_VPT_YSCALE         3
  95 #define R300_VPT_YOFFSET        4
  96 #define R300_VPT_ZSCALE         5
  97 #define R300_VPT_ZOFFSET        6
  98 #define R300_VPT_CMDSIZE        7
  99
 100 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
 101 #define R300_VIR_CNTL_0         1
 102 #define R300_VIR_CNTL_1         2
 103 #define R300_VIR_CNTL_2         3
 104 #define R300_VIR_CNTL_3         4
 105 #define R300_VIR_CNTL_4         5
 106 #define R300_VIR_CNTL_5         6
 107 #define R300_VIR_CNTL_6         7
 108 #define R300_VIR_CNTL_7         8
 109 #define R300_VIR_CMDSIZE        9
 110
 111 #define R300_VIC_CMD_0          0
 112 #define R300_VIC_CNTL_0         1
 113 #define R300_VIC_CNTL_1         2
 114 #define R300_VIC_CMDSIZE        3
 115
 116 #define R300_VOF_CMD_0          0
 117 #define R300_VOF_CNTL_0         1
 118 #define R300_VOF_CNTL_1         2
 119 #define R300_VOF_CMDSIZE        3
 120
 121 #define R300_PVS_CMD_0          0
 122 #define R300_PVS_CNTL_1         1
 123 #define R300_PVS_CNTL_2         2
 124 #define R300_PVS_CNTL_3         3
 125 #define R300_PVS_CMDSIZE        4
 126
 127 #define R300_GB_MISC_CMD_0              0
 128 #define R300_GB_MISC_MSPOS_0            1
 129 #define R300_GB_MISC_MSPOS_1            2
 130 #define R300_GB_MISC_TILE_CONFIG        3
 131 #define R300_GB_MISC_SELECT             4
 132 #define R300_GB_MISC_AA_CONFIG          5
 133 #define R300_GB_MISC_CMDSIZE            6
 134
 135 #define R300_TXE_CMD_0          0
 136 #define R300_TXE_ENABLE         1
 137 #define R300_TXE_CMDSIZE        2
 138
 139 #define R300_PS_CMD_0           0
 140 #define R300_PS_POINTSIZE       1
 141 #define R300_PS_CMDSIZE         2
 142
 143 #define R300_ZBS_CMD_0          0
 144 #define R300_ZBS_T_FACTOR       1
 145 #define R300_ZBS_T_CONSTANT     2
 146 #define R300_ZBS_W_FACTOR       3
 147 #define R300_ZBS_W_CONSTANT     4
 148 #define R300_ZBS_CMDSIZE        5
 149
 150 #define R300_CUL_CMD_0          0
 151 #define R300_CUL_CULL           1
 152 #define R300_CUL_CMDSIZE        2
 153
 154 #define R300_RC_CMD_0           0
 155 #define R300_RC_CNTL_0          1
 156 #define R300_RC_CNTL_1          2
 157 #define R300_RC_CMDSIZE         3
 158
 159 #define R300_RI_CMD_0           0
 160 #define R300_RI_INTERP_0        1
 161 #define R300_RI_INTERP_1        2
 162 #define R300_RI_INTERP_2        3
 163 #define R300_RI_INTERP_3        4
 164 #define R300_RI_INTERP_4        5
 165 #define R300_RI_INTERP_5        6
 166 #define R300_RI_INTERP_6        7
 167 #define R300_RI_INTERP_7        8
 168 #define R300_RI_CMDSIZE         9
 169
 170 #define R500_RI_CMDSIZE        17
 171
 172 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 173 #define R300_RR_INST_0          1
 174 #define R300_RR_INST_1          2
 175 #define R300_RR_INST_2          3
 176 #define R300_RR_INST_3          4
 177 #define R300_RR_INST_4          5
 178 #define R300_RR_INST_5          6
 179 #define R300_RR_INST_6          7
 180 #define R300_RR_INST_7          8
 181 #define R300_RR_CMDSIZE         9
 182
 183 #define R300_FP_CMD_0           0
 184 #define R300_FP_CNTL0           1
 185 #define R300_FP_CNTL1           2
 186 #define R300_FP_CNTL2           3
 187 #define R300_FP_CMD_1           4
 188 #define R300_FP_NODE0           5
 189 #define R300_FP_NODE1           6
 190 #define R300_FP_NODE2           7
 191 #define R300_FP_NODE3           8
 192 #define R300_FP_CMDSIZE         9
 193
 194 #define R500_FP_CMD_0           0
 195 #define R500_FP_CNTL            1
 196 #define R500_FP_PIXSIZE         2
 197 #define R500_FP_CMD_1           3
 198 #define R500_FP_CODE_ADDR       4
 199 #define R500_FP_CODE_RANGE      5
 200 #define R500_FP_CODE_OFFSET     6
 201 #define R500_FP_CMD_2           7
 202 #define R500_FP_FC_CNTL         8
 203 #define R500_FP_CMDSIZE         9
 204
 205 #define R300_FPT_CMD_0          0
 206 #define R300_FPT_INSTR_0        1
 207 #define R300_FPT_CMDSIZE        65
 208
 209 #define R300_FPI_CMD_0          0
 210 #define R300_FPI_INSTR_0        1
 211 #define R300_FPI_CMDSIZE        65
 212 /* R500 has space for 512 instructions - 6 dwords per instruction */
 213 #define R500_FPI_CMDSIZE        (512*6+1)
 214
 215 #define R300_FPP_CMD_0          0
 216 #define R300_FPP_PARAM_0        1
 217 #define R300_FPP_CMDSIZE        (32*4+1)
 218 /* R500 has spcae for 256 constants - 4 dwords per constant */
 219 #define R500_FPP_CMDSIZE        (256*4+1)
 220
 221 #define R300_FOGS_CMD_0         0
 222 #define R300_FOGS_STATE         1
 223 #define R300_FOGS_CMDSIZE       2
 224
 225 #define R300_FOGC_CMD_0         0
 226 #define R300_FOGC_R             1
 227 #define R300_FOGC_G             2
 228 #define R300_FOGC_B             3
 229 #define R300_FOGC_CMDSIZE       4
 230
 231 #define R300_FOGP_CMD_0         0
 232 #define R300_FOGP_SCALE         1
 233 #define R300_FOGP_START         2
 234 #define R300_FOGP_CMDSIZE       3
 235
 236 #define R300_AT_CMD_0           0
 237 #define R300_AT_ALPHA_TEST      1
 238 #define R300_AT_UNKNOWN         2
 239 #define R300_AT_CMDSIZE         3
 240
 241 #define R300_BLD_CMD_0          0
 242 #define R300_BLD_CBLEND         1
 243 #define R300_BLD_ABLEND         2
 244 #define R300_BLD_CMDSIZE        3
 245
 246 #define R300_CMK_CMD_0          0
 247 #define R300_CMK_COLORMASK      1
 248 #define R300_CMK_CMDSIZE        2
 249
 250 #define R300_CB_CMD_0           0
 251 #define R300_CB_OFFSET          1
 252 #define R300_CB_CMD_1           2
 253 #define R300_CB_PITCH           3
 254 #define R300_CB_CMDSIZE         4
 255
 256 #define R300_ZS_CMD_0           0
 257 #define R300_ZS_CNTL_0          1
 258 #define R300_ZS_CNTL_1          2
 259 #define R300_ZS_CNTL_2          3
 260 #define R300_ZS_CMDSIZE         4
 261
 262 #define R300_ZB_CMD_0           0
 263 #define R300_ZB_OFFSET          1
 264 #define R300_ZB_PITCH           2
 265 #define R300_ZB_CMDSIZE         3
 266
 267 #define R300_VAP_CNTL_FLUSH     0
 268 #define R300_VAP_CNTL_FLUSH_1   1
 269 #define R300_VAP_CNTL_CMD       2
 270 #define R300_VAP_CNTL_INSTR     3
 271 #define R300_VAP_CNTL_SIZE      4
 272
 273 #define R300_VPI_CMD_0          0
 274 #define R300_VPI_INSTR_0        1
 275 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 276
 277 #define R300_VPP_CMD_0          0
 278 #define R300_VPP_PARAM_0        1
 279 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 280
 281 #define R300_VPUCP_CMD_0                0
 282 #define R300_VPUCP_X            1
 283 #define R300_VPUCP_Y            2
 284 #define R300_VPUCP_Z            3
 285 #define R300_VPUCP_W            4
 286 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 287
 288 #define R300_VPS_CMD_0          0
 289 #define R300_VPS_ZERO_0         1
 290 #define R300_VPS_ZERO_1         2
 291 #define R300_VPS_POINTSIZE      3
 292 #define R300_VPS_ZERO_3         4
 293 #define R300_VPS_CMDSIZE        5
 294
 295         /* the layout is common for all fields inside tex */
 296 #define R300_TEX_CMD_0          0
 297 #define R300_TEX_VALUE_0        1
 298 /* We don't really use this, instead specify mtu+1 dynamically
 299 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 300 */
 301
 302 /**
 303  * Cache for hardware register state.
 304  */
 305 struct r300_hw_state {
 306         struct radeon_state_atom vpt;   /* viewport (1D98) */
 307         struct radeon_state_atom vap_cntl;
 308         struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
 309         struct radeon_state_atom vof;   /* VAP output format register 0x2090 */
 310         struct radeon_state_atom vte;   /* (20B0) */
 311         struct radeon_state_atom vap_vf_max_vtx_indx;   /* Maximum Vertex Indx Clamp (2134) */
 312         struct radeon_state_atom vap_cntl_status;
 313         struct radeon_state_atom vir[2];        /* vap input route (2150/21E0) */
 314         struct radeon_state_atom vic;   /* vap input control (2180) */
 315         struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 316         struct radeon_state_atom vap_clip_cntl;
 317         struct radeon_state_atom vap_clip;
 318         struct radeon_state_atom vap_pvs_vtx_timeout_reg;       /* Vertex timeout register (2288) */
 319         struct radeon_state_atom pvs;   /* pvs_cntl (22D0) */
 320         struct radeon_state_atom gb_enable;     /* (4008) */
 321         struct radeon_state_atom gb_misc;       /* Multisampling position shifts ? (4010) */
 322         struct radeon_state_atom ga_point_s0;   /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 323         struct radeon_state_atom ga_triangle_stipple;   /* (4214) */
 324         struct radeon_state_atom ps;    /* pointsize (421C) */
 325         struct radeon_state_atom ga_point_minmax;       /* (4230) */
 326         struct radeon_state_atom lcntl; /* line control */
 327         struct radeon_state_atom ga_line_stipple;       /* (4260) */
 328         struct radeon_state_atom shade;
 329         struct radeon_state_atom polygon_mode;
 330         struct radeon_state_atom fogp;  /* fog parameters (4294) */
 331         struct radeon_state_atom ga_soft_reset; /* (429C) */
 332         struct radeon_state_atom zbias_cntl;
 333         struct radeon_state_atom zbs;   /* zbias (42A4) */
 334         struct radeon_state_atom occlusion_cntl;
 335         struct radeon_state_atom cul;   /* cull cntl (42B8) */
 336         struct radeon_state_atom su_depth_scale;        /* (42C0) */
 337         struct radeon_state_atom rc;    /* rs control (4300) */
 338         struct radeon_state_atom ri;    /* rs interpolators (4310) */
 339         struct radeon_state_atom rr;    /* rs route (4330) */
 340         struct radeon_state_atom sc_hyperz;     /* (43A4) */
 341         struct radeon_state_atom sc_screendoor; /* (43E8) */
 342         struct radeon_state_atom fp;    /* fragment program cntl + nodes (4600) */
 343         struct radeon_state_atom fpt;   /* texi - (4620) */
 344         struct radeon_state_atom us_out_fmt;    /* (46A4) */
 345         struct radeon_state_atom r500fp;        /* r500 fp instructions */
 346         struct radeon_state_atom r500fp_const;  /* r500 fp constants */
 347         struct radeon_state_atom fpi[4];        /* fp instructions (46C0/47C0/48C0/49C0) */
 348         struct radeon_state_atom fogs;  /* fog state (4BC0) */
 349         struct radeon_state_atom fogc;  /* fog color (4BC8) */
 350         struct radeon_state_atom at;    /* alpha test (4BD4) */
 351         struct radeon_state_atom fg_depth_src;  /* (4BD8) */
 352         struct radeon_state_atom fpp;   /* 0x4C00 and following */
 353         struct radeon_state_atom rb3d_cctl;     /* (4E00) */
 354         struct radeon_state_atom bld;   /* blending (4E04) */
 355         struct radeon_state_atom cmk;   /* colormask (4E0C) */
 356         struct radeon_state_atom blend_color;   /* constant blend color */
 357         struct radeon_state_atom rop;   /* ropcntl */
 358         struct radeon_state_atom cb;    /* colorbuffer (4E28) */
 359         struct radeon_state_atom rb3d_dither_ctl;       /* (4E50) */
 360         struct radeon_state_atom rb3d_aaresolve_ctl;    /* (4E88) */
 361         struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold;  /* (4E88) I saw it only written on RV350 hardware..  */
 362         struct radeon_state_atom zs;    /* zstencil control (4F00) */
 363         struct radeon_state_atom zstencil_format;
 364         struct radeon_state_atom zb;    /* z buffer (4F20) */
 365         struct radeon_state_atom zb_depthclearvalue;    /* (4F28) */
 366         struct radeon_state_atom unk4F30;       /* (4F30) */
 367         struct radeon_state_atom zb_hiz_offset; /* (4F44) */
 368         struct radeon_state_atom zb_hiz_pitch;  /* (4F54) */
 369
 370         struct radeon_state_atom vpi;   /* vp instructions */
 371         struct radeon_state_atom vpp;   /* vp parameters */
 372         struct radeon_state_atom vps;   /* vertex point size (?) */
 373         struct radeon_state_atom vpucp[6];      /* vp user clip plane - 6 */
 374         /* 8 texture units */
 375         /* the state is grouped by function and not by
 376            texture unit. This makes single unit updates
 377            really awkward - we are much better off
 378            updating the whole thing at once */
 379         struct {
 380                 struct radeon_state_atom filter;
 381                 struct radeon_state_atom filter_1;
 382                 struct radeon_state_atom size;
 383                 struct radeon_state_atom format;
 384                 struct radeon_state_atom pitch;
 385                 struct radeon_state_atom offset;
 386                 struct radeon_state_atom chroma_key;
 387                 struct radeon_state_atom border_color;
 388         } tex;
 389         struct radeon_state_atom txe;   /* tex enable (4104) */
 390
 391         radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
 392 };
 393
 394 /**
 395  * State cache
 396  */
 397
 398 /* Vertex shader state */
 399
 400 /* Perhaps more if we store programs in vmem? */
 401 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 402 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 403
 404 /* Can be tested with colormat currently. */
 405 #define VSF_MAX_FRAGMENT_TEMPS (14)
 406
 407 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 408 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 409
 410 struct r300_vertex_shader_fragment {
 411         int length;
 412         union {
 413                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 414                 float f[VSF_MAX_FRAGMENT_LENGTH];
 415                 GLuint i[VSF_MAX_FRAGMENT_LENGTH];
 416         } body;
 417 };
 418
 419 struct r300_vertex_shader_state {
 420         struct r300_vertex_shader_fragment program;
 421 };
 422
 423 extern int hw_tcl_on;
 424
 425 #define COLOR_IS_RGBA
 426 #define TAG(x) r300##x
 427 #include "tnl_dd/t_dd_vertex.h"
 428 #undef TAG
 429
 430 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 431 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 432
 433 /* Should but doesnt work */
 434 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 435
 436 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 437  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 438  */
 439
 440 struct r300_vertex_program_key {
 441         GLuint InputsRead;
 442         GLuint OutputsWritten;
 443         GLuint OutputsAdded;
 444 };
 445
 446 struct r300_vertex_program {
 447         struct r300_vertex_program *next;
 448         struct r300_vertex_program_key key;
 449         int translated;
 450
 451         struct r300_vertex_shader_fragment program;
 452
 453         int pos_end;
 454         int num_temporaries;    /* Number of temp vars used by program */
 455         int wpos_idx;
 456         int inputs[VERT_ATTRIB_MAX];
 457         int outputs[VERT_RESULT_MAX];
 458         int native;
 459         int ref_count;
 460         int use_ref_count;
 461 };
 462
 463 struct r300_vertex_program_cont {
 464         struct gl_vertex_program mesa_program;  /* Must be first */
 465         struct r300_vertex_shader_fragment params;
 466         struct r300_vertex_program *progs;
 467 };
 468
 469 #define PFS_MAX_ALU_INST        64
 470 #define PFS_MAX_TEX_INST        64
 471 #define PFS_MAX_TEX_INDIRECT 4
 472 #define PFS_NUM_TEMP_REGS       32
 473 #define PFS_NUM_CONST_REGS      16
 474
 475 struct r300_pfs_compile_state;
 476
 477
 478 /**
 479  * Stores state that influences the compilation of a fragment program.
 480  */
 481 struct r300_fragment_program_external_state {
 482         struct {
 483                 /**
 484                  * If the sampler is used as a shadow sampler,
 485                  * this field is:
 486                  *  0 - GL_LUMINANCE
 487                  *  1 - GL_INTENSITY
 488                  *  2 - GL_ALPHA
 489                  * depending on the depth texture mode.
 490                  */
 491                 GLuint depth_texture_mode : 2;
 492
 493                 /**
 494                  * If the sampler is used as a shadow sampler,
 495                  * this field is (texture_compare_func - GL_NEVER).
 496                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 497                  *
 498                  * Otherwise, this field is 0.
 499                  */
 500                 GLuint texture_compare_func : 3;
 501         } unit[16];
 502 };
 503
 504
 505 struct r300_fragment_program_node {
 506         int tex_offset; /**< first tex instruction */
 507         int tex_end; /**< last tex instruction, relative to tex_offset */
 508         int alu_offset; /**< first ALU instruction */
 509         int alu_end; /**< last ALU instruction, relative to alu_offset */
 510         int flags;
 511 };
 512
 513 /**
 514  * Stores an R300 fragment program in its compiled-to-hardware form.
 515  */
 516 struct r300_fragment_program_code {
 517         struct {
 518                 int length; /**< total # of texture instructions used */
 519                 GLuint inst[PFS_MAX_TEX_INST];
 520         } tex;
 521
 522         struct {
 523                 int length; /**< total # of ALU instructions used */
 524                 struct {
 525                         GLuint inst0;
 526                         GLuint inst1;
 527                         GLuint inst2;
 528                         GLuint inst3;
 529                 } inst[PFS_MAX_ALU_INST];
 530         } alu;
 531
 532         struct r300_fragment_program_node node[4];
 533         int cur_node;
 534         int first_node_has_tex;
 535
 536         /**
 537          * Remember which program register a given hardware constant
 538          * belongs to.
 539          */
 540         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 541         int const_nr;
 542
 543         int max_temp_idx;
 544 };
 545
 546 /**
 547  * Store everything about a fragment program that is needed
 548  * to render with that program.
 549  */
 550 struct r300_fragment_program {
 551         struct gl_fragment_program mesa_program;
 552
 553         GLboolean translated;
 554         GLboolean error;
 555
 556         struct r300_fragment_program_external_state state;
 557         struct r300_fragment_program_code code;
 558
 559         GLboolean WritesDepth;
 560         GLuint optimization;
 561 };
 562
 563 struct r500_pfs_compile_state;
 564
 565 struct r500_fragment_program_external_state {
 566         struct {
 567                 /**
 568                  * If the sampler is used as a shadow sampler,
 569                  * this field is:
 570                  *  0 - GL_LUMINANCE
 571                  *  1 - GL_INTENSITY
 572                  *  2 - GL_ALPHA
 573                  * depending on the depth texture mode.
 574                  */
 575                 GLuint depth_texture_mode : 2;
 576
 577                 /**
 578                  * If the sampler is used as a shadow sampler,
 579                  * this field is (texture_compare_func - GL_NEVER).
 580                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 581                  *
 582                  * Otherwise, this field is 0.
 583                  */
 584                 GLuint texture_compare_func : 3;
 585         } unit[16];
 586 };
 587
 588 struct r500_fragment_program_code {
 589         struct {
 590                 GLuint inst0;
 591                 GLuint inst1;
 592                 GLuint inst2;
 593                 GLuint inst3;
 594                 GLuint inst4;
 595                 GLuint inst5;
 596         } inst[512];
 597
 598         int inst_offset;
 599         int inst_end;
 600
 601         /**
 602          * Remember which program register a given hardware constant
 603          * belongs to.
 604          */
 605         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 606         int const_nr;
 607
 608         int max_temp_idx;
 609 };
 610
 611 struct r500_fragment_program {
 612         struct gl_fragment_program mesa_program;
 613
 614         GLcontext *ctx;
 615         GLboolean translated;
 616         GLboolean error;
 617
 618         struct r500_fragment_program_external_state state;
 619         struct r500_fragment_program_code code;
 620
 621         GLboolean writes_depth;
 622
 623         GLuint optimization;
 624 };
 625
 626 #define R300_MAX_AOS_ARRAYS             16
 627
 628 #define REG_COORDS      0
 629 #define REG_COLOR0      1
 630 #define REG_TEX0        2
 631
 632 struct r300_state {
 633         struct r300_texture_state texture;
 634         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 635         struct r300_vertex_shader_state vertex_shader;
 636         struct radeon_aos aos[R300_MAX_AOS_ARRAYS];
 637         int aos_count;
 638
 639         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 640         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 641
 642         DECLARE_RENDERINPUTS(render_inputs_bitset);     /* actual render inputs that R300 was configured for.
 643                                                            They are the same as tnl->render_inputs for fixed pipeline */
 644
 645 };
 646
 647 #define R300_FALLBACK_NONE 0
 648 #define R300_FALLBACK_TCL 1
 649 #define R300_FALLBACK_RAST 2
 650
 651 /* r300_swtcl.c
 652  */
 653 struct r300_swtcl_info {
 654   /*
 655     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 656     */
 657    GLuint coloroffset;
 658
 659    /**
 660     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 661     */
 662    GLuint specoffset;
 663 };
 664
 665
 666 /**
 667  * \brief R300 context structure.
 668  */
 669 struct r300_context {
 670         struct radeon_context radeon;   /* parent class, must be first */
 671
 672         struct r300_hw_state hw;
 673
 674         struct r300_state state;
 675         struct gl_vertex_program *curr_vp;
 676         struct r300_vertex_program *selected_vp;
 677
 678         /* Vertex buffers
 679          */
 680         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 681         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 682
 683         GLboolean disable_lowimpact_fallback;
 684
 685         DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
 686         struct r300_swtcl_info swtcl;
 687 };
 688
 689 struct r300_buffer_object {
 690         struct gl_buffer_object mesa_obj;
 691         int id;
 692 };
 693
 694 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 695
 696 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 697 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 698                                    __DRIcontextPrivate * driContextPriv,
 699                                    void *sharedContextPrivate);
 700
 701 extern void r300SelectVertexShader(r300ContextPtr r300);
 702 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 703 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 704                                       struct r300_vertex_program_cont *vp,
 705                                       float *dst);
 706
 707 #define RADEON_D_CAPTURE 0
 708 #define RADEON_D_PLAYBACK 1
 709 #define RADEON_D_PLAYBACK_RAW 2
 710 #define RADEON_D_T 3
 711
 712 #define r300PackFloat32 radeonPackFloat32
 713 #define r300PackFloat24 radeonPackFloat24
 714
 715 #endif                          /* __R300_CONTEXT_H__ */