src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45
  46 #include "macros.h"
  47 #include "mtypes.h"
  48 #include "colormac.h"
  49
  50 #define USER_BUFFERS
  51
  52 /* We don't handle 16 bits elts swapping yet */
  53 #ifdef MESA_BIG_ENDIAN
  54 #define FORCE_32BITS_ELTS
  55 #endif
  56
  57 //#define OPTIMIZE_ELTS
  58
  59 struct r300_context;
  60 typedef struct r300_context r300ContextRec;
  61 typedef struct r300_context *r300ContextPtr;
  62
  63 #include "radeon_lock.h"
  64 #include "mm.h"
  65
  66 /* Checkpoint.. for convenience */
  67 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  68 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  69    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  70    with other compilers ... GLUE!
  71 */
  72 #if 1
  73 #define WARN_ONCE(a, ...)       { \
  74         static int warn##__LINE__=1; \
  75         if(warn##__LINE__){ \
  76                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  77                 fprintf(stderr, "File %s function %s line %d\n", \
  78                         __FILE__, __FUNCTION__, __LINE__); \
  79                 fprintf(stderr,  a, ## __VA_ARGS__);\
  80                 fprintf(stderr, "***************************************************************************\n"); \
  81                 warn##__LINE__=0;\
  82                 } \
  83         }
  84 #else
  85 #define WARN_ONCE(a, ...) {}
  86 #endif
  87
  88 #include "r300_vertprog.h"
  89 #include "r300_fragprog.h"
  90
  91 /**
  92  * This function takes a float and packs it into a uint32_t
  93  */
  94 static __inline__ uint32_t r300PackFloat32(float fl)
  95 {
  96         union {
  97                 float fl;
  98                 uint32_t u;
  99         } u;
 100
 101         u.fl = fl;
 102         return u.u;
 103 }
 104
 105 /************ DMA BUFFERS **************/
 106
 107 /* Need refcounting on dma buffers:
 108  */
 109 struct r300_dma_buffer {
 110         int refcount;           /**< the number of retained regions in buf */
 111         drmBufPtr buf;
 112         int id;
 113 };
 114 #undef GET_START
 115 #ifdef USER_BUFFERS
 116 #define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start))
 117 #else
 118 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 119                         (rvb)->address - rmesa->dma.buf0_address +      \
 120                         (rvb)->start)
 121 #endif
 122 /* A retained region, eg vertices for indexed vertices.
 123  */
 124 struct r300_dma_region {
 125         struct r300_dma_buffer *buf;
 126         char *address;          /* == buf->address */
 127         int start, end, ptr;    /* offsets from start of buf */
 128
 129         int aos_offset;         /* address in GART memory */
 130         int aos_stride;         /* distance between elements, in dwords */
 131         int aos_size;           /* number of components (1-4) */
 132         int aos_reg;            /* VAP register assignment */
 133 };
 134
 135 struct r300_dma {
 136         /* Active dma region.  Allocations for vertices and retained
 137          * regions come from here.  Also used for emitting random vertices,
 138          * these may be flushed by calling flush_current();
 139          */
 140         struct r300_dma_region current;
 141
 142         void (*flush) (r300ContextPtr);
 143
 144         char *buf0_address;     /* start of buf[0], for index calcs */
 145
 146         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 147          * for which a DISCARD command is currently queued in the command buffer.
 148          */
 149         GLuint nr_released_bufs;
 150 };
 151
 152        /* Texture related */
 153
 154 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 155
 156 /* Texture object in locally shared texture space.
 157  */
 158 struct r300_tex_obj {
 159         driTextureObject base;
 160
 161         GLuint bufAddr;         /* Offset to start of locally
 162                                    shared texture block */
 163
 164         GLuint dirty_state;     /* Flags (1 per texunit) for
 165                                    whether or not this texobj
 166                                    has dirty hardware state
 167                                    (pp_*) that needs to be
 168                                    brought into the
 169                                    texunit. */
 170
 171         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 172         /* Six, for the cube faces */
 173
 174         GLuint pitch;           /* this isn't sent to hardware just used in calculations */
 175         /* hardware register values */
 176         /* Note that R200 has 8 registers per texture and R300 only 7 */
 177         GLuint filter;
 178         GLuint filter_1;
 179         GLuint pitch_reg;
 180         GLuint size;            /* npot only */
 181         GLuint format;
 182         GLuint offset;          /* Image location in the card's address space.
 183                                    All cube faces follow. */
 184         GLuint unknown4;
 185         GLuint unknown5;
 186         /* end hardware registers */
 187
 188         /* registers computed by r200 code - keep them here to
 189            compare against what is actually written.
 190
 191            to be removed later.. */
 192         GLuint pp_border_color;
 193         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 194         GLuint format_x;
 195
 196         GLboolean border_fallback;
 197
 198         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 199 };
 200
 201 struct r300_texture_env_state {
 202         r300TexObjPtr texobj;
 203         GLenum format;
 204         GLenum envMode;
 205 };
 206
 207 /* The blit width for texture uploads
 208  */
 209 #define R300_BLIT_WIDTH_BYTES 1024
 210 #define R300_MAX_TEXTURE_UNITS 8
 211
 212 struct r300_texture_state {
 213         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 214         int tc_count;           /* number of incoming texture coordinates from VAP */
 215 };
 216
 217 /**
 218  * A block of hardware state.
 219  *
 220  * When check returns non-zero, the returned number of dwords must be
 221  * copied verbatim into the command buffer in order to update a state atom
 222  * when it is dirty.
 223  */
 224 struct r300_state_atom {
 225         struct r300_state_atom *next, *prev;
 226         const char *name;       /* for debug */
 227         int cmd_size;           /* maximum size in dwords */
 228         GLuint idx;             /* index in an array (e.g. textures) */
 229         uint32_t *cmd;
 230         GLboolean dirty;
 231
 232         int (*check) (r300ContextPtr, struct r300_state_atom * atom);
 233 };
 234
 235 #define R300_VPT_CMD_0          0
 236 #define R300_VPT_XSCALE         1
 237 #define R300_VPT_XOFFSET        2
 238 #define R300_VPT_YSCALE         3
 239 #define R300_VPT_YOFFSET        4
 240 #define R300_VPT_ZSCALE         5
 241 #define R300_VPT_ZOFFSET        6
 242 #define R300_VPT_CMDSIZE        7
 243
 244 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
 245 #define R300_VIR_CNTL_0         1
 246 #define R300_VIR_CNTL_1         2
 247 #define R300_VIR_CNTL_2         3
 248 #define R300_VIR_CNTL_3         4
 249 #define R300_VIR_CNTL_4         5
 250 #define R300_VIR_CNTL_5         6
 251 #define R300_VIR_CNTL_6         7
 252 #define R300_VIR_CNTL_7         8
 253 #define R300_VIR_CMDSIZE        9
 254
 255 #define R300_VIC_CMD_0          0
 256 #define R300_VIC_CNTL_0         1
 257 #define R300_VIC_CNTL_1         2
 258 #define R300_VIC_CMDSIZE        3
 259
 260 #define R300_VOF_CMD_0          0
 261 #define R300_VOF_CNTL_0         1
 262 #define R300_VOF_CNTL_1         2
 263 #define R300_VOF_CMDSIZE        3
 264
 265 #define R300_PVS_CMD_0          0
 266 #define R300_PVS_CNTL_1         1
 267 #define R300_PVS_CNTL_2         2
 268 #define R300_PVS_CNTL_3         3
 269 #define R300_PVS_CMDSIZE        4
 270
 271 #define R300_GB_MISC_CMD_0              0
 272 #define R300_GB_MISC_MSPOS_0            1
 273 #define R300_GB_MISC_MSPOS_1            2
 274 #define R300_GB_MISC_TILE_CONFIG        3
 275 #define R300_GB_MISC_SELECT             4
 276 #define R300_GB_MISC_AA_CONFIG          5
 277 #define R300_GB_MISC_CMDSIZE            6
 278
 279 #define R300_TXE_CMD_0          0
 280 #define R300_TXE_ENABLE         1
 281 #define R300_TXE_CMDSIZE        2
 282
 283 #define R300_PS_CMD_0           0
 284 #define R300_PS_POINTSIZE       1
 285 #define R300_PS_CMDSIZE         2
 286
 287 #define R300_ZBS_CMD_0          0
 288 #define R300_ZBS_T_FACTOR       1
 289 #define R300_ZBS_T_CONSTANT     2
 290 #define R300_ZBS_W_FACTOR       3
 291 #define R300_ZBS_W_CONSTANT     4
 292 #define R300_ZBS_CMDSIZE        5
 293
 294 #define R300_CUL_CMD_0          0
 295 #define R300_CUL_CULL           1
 296 #define R300_CUL_CMDSIZE        2
 297
 298 #define R300_RC_CMD_0           0
 299 #define R300_RC_CNTL_0          1
 300 #define R300_RC_CNTL_1          2
 301 #define R300_RC_CMDSIZE         3
 302
 303 #define R300_RI_CMD_0           0
 304 #define R300_RI_INTERP_0        1
 305 #define R300_RI_INTERP_1        2
 306 #define R300_RI_INTERP_2        3
 307 #define R300_RI_INTERP_3        4
 308 #define R300_RI_INTERP_4        5
 309 #define R300_RI_INTERP_5        6
 310 #define R300_RI_INTERP_6        7
 311 #define R300_RI_INTERP_7        8
 312 #define R300_RI_CMDSIZE         9
 313
 314 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 315 #define R300_RR_ROUTE_0         1
 316 #define R300_RR_ROUTE_1         2
 317 #define R300_RR_ROUTE_2         3
 318 #define R300_RR_ROUTE_3         4
 319 #define R300_RR_ROUTE_4         5
 320 #define R300_RR_ROUTE_5         6
 321 #define R300_RR_ROUTE_6         7
 322 #define R300_RR_ROUTE_7         8
 323 #define R300_RR_CMDSIZE         9
 324
 325 #define R300_FP_CMD_0           0
 326 #define R300_FP_CNTL0           1
 327 #define R300_FP_CNTL1           2
 328 #define R300_FP_CNTL2           3
 329 #define R300_FP_CMD_1           4
 330 #define R300_FP_NODE0           5
 331 #define R300_FP_NODE1           6
 332 #define R300_FP_NODE2           7
 333 #define R300_FP_NODE3           8
 334 #define R300_FP_CMDSIZE         9
 335
 336 #define R300_FPT_CMD_0          0
 337 #define R300_FPT_INSTR_0        1
 338 #define R300_FPT_CMDSIZE        65
 339
 340 #define R300_FPI_CMD_0          0
 341 #define R300_FPI_INSTR_0        1
 342 #define R300_FPI_CMDSIZE        65
 343
 344 #define R300_FPP_CMD_0          0
 345 #define R300_FPP_PARAM_0        1
 346 #define R300_FPP_CMDSIZE        (32*4+1)
 347
 348 #define R300_FOGS_CMD_0         0
 349 #define R300_FOGS_STATE         1
 350 #define R300_FOGS_CMDSIZE       2
 351
 352 #define R300_FOGC_CMD_0         0
 353 #define R300_FOGC_R             1
 354 #define R300_FOGC_G             2
 355 #define R300_FOGC_B             3
 356 #define R300_FOGC_CMDSIZE       4
 357
 358 #define R300_FOGP_CMD_0         0
 359 #define R300_FOGP_SCALE         1
 360 #define R300_FOGP_START         2
 361 #define R300_FOGP_CMDSIZE       3
 362
 363 #define R300_AT_CMD_0           0
 364 #define R300_AT_ALPHA_TEST      1
 365 #define R300_AT_UNKNOWN         2
 366 #define R300_AT_CMDSIZE         3
 367
 368 #define R300_BLD_CMD_0          0
 369 #define R300_BLD_CBLEND         1
 370 #define R300_BLD_ABLEND         2
 371 #define R300_BLD_CMDSIZE        3
 372
 373 #define R300_CMK_CMD_0          0
 374 #define R300_CMK_COLORMASK      1
 375 #define R300_CMK_CMDSIZE        2
 376
 377 #define R300_CB_CMD_0           0
 378 #define R300_CB_OFFSET          1
 379 #define R300_CB_CMD_1           2
 380 #define R300_CB_PITCH           3
 381 #define R300_CB_CMDSIZE         4
 382
 383 #define R300_ZS_CMD_0           0
 384 #define R300_ZS_CNTL_0          1
 385 #define R300_ZS_CNTL_1          2
 386 #define R300_ZS_CNTL_2          3
 387 #define R300_ZS_CMDSIZE         4
 388
 389 #define R300_ZB_CMD_0           0
 390 #define R300_ZB_OFFSET          1
 391 #define R300_ZB_PITCH           2
 392 #define R300_ZB_CMDSIZE         3
 393
 394 #define R300_VPI_CMD_0          0
 395 #define R300_VPI_INSTR_0        1
 396 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 397
 398 #define R300_VPP_CMD_0          0
 399 #define R300_VPP_PARAM_0        1
 400 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 401
 402 #define R300_VPS_CMD_0          0
 403 #define R300_VPS_ZERO_0         1
 404 #define R300_VPS_ZERO_1         2
 405 #define R300_VPS_POINTSIZE      3
 406 #define R300_VPS_ZERO_3         4
 407 #define R300_VPS_CMDSIZE        5
 408
 409         /* the layout is common for all fields inside tex */
 410 #define R300_TEX_CMD_0          0
 411 #define R300_TEX_VALUE_0        1
 412 /* We don't really use this, instead specify mtu+1 dynamically
 413 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 414 */
 415
 416 /**
 417  * Cache for hardware register state.
 418  */
 419 struct r300_hw_state {
 420         struct r300_state_atom atomlist;
 421
 422         GLboolean is_dirty;
 423         GLboolean all_dirty;
 424         int max_state_size;     /* in dwords */
 425
 426         struct r300_state_atom vpt;     /* viewport (1D98) */
 427         struct r300_state_atom vap_cntl;
 428         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 429         struct r300_state_atom vte;     /* (20B0) */
 430         struct r300_state_atom unk2134; /* (2134) */
 431         struct r300_state_atom vap_cntl_status;
 432         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 433         struct r300_state_atom vic;     /* vap input control (2180) */
 434         struct r300_state_atom unk21DC; /* (21DC) */
 435         struct r300_state_atom unk221C; /* (221C) */
 436         struct r300_state_atom unk2220; /* (2220) */
 437         struct r300_state_atom unk2288; /* (2288) */
 438         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 439         struct r300_state_atom gb_enable;       /* (4008) */
 440         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 441         struct r300_state_atom unk4200; /* (4200) */
 442         struct r300_state_atom unk4214; /* (4214) */
 443         struct r300_state_atom ps;      /* pointsize (421C) */
 444         struct r300_state_atom unk4230; /* (4230) */
 445         struct r300_state_atom lcntl;   /* line control */
 446         struct r300_state_atom unk4260; /* (4260) */
 447         struct r300_state_atom shade;
 448         struct r300_state_atom polygon_mode;
 449         struct r300_state_atom fogp;    /* fog parameters (4294) */
 450         struct r300_state_atom unk429C; /* (429C) */
 451         struct r300_state_atom zbias_cntl;
 452         struct r300_state_atom zbs;     /* zbias (42A4) */
 453         struct r300_state_atom occlusion_cntl;
 454         struct r300_state_atom cul;     /* cull cntl (42B8) */
 455         struct r300_state_atom unk42C0; /* (42C0) */
 456         struct r300_state_atom rc;      /* rs control (4300) */
 457         struct r300_state_atom ri;      /* rs interpolators (4310) */
 458         struct r300_state_atom rr;      /* rs route (4330) */
 459         struct r300_state_atom unk43A4; /* (43A4) */
 460         struct r300_state_atom unk43E8; /* (43E8) */
 461         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 462         struct r300_state_atom fpt;     /* texi - (4620) */
 463         struct r300_state_atom unk46A4; /* (46A4) */
 464         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 465         struct r300_state_atom fogs;    /* fog state (4BC0) */
 466         struct r300_state_atom fogc;    /* fog color (4BC8) */
 467         struct r300_state_atom at;      /* alpha test (4BD4) */
 468         struct r300_state_atom unk4BD8; /* (4BD8) */
 469         struct r300_state_atom fpp;     /* 0x4C00 and following */
 470         struct r300_state_atom unk4E00; /* (4E00) */
 471         struct r300_state_atom bld;     /* blending (4E04) */
 472         struct r300_state_atom cmk;     /* colormask (4E0C) */
 473         struct r300_state_atom blend_color;     /* constant blend color */
 474         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 475         struct r300_state_atom unk4E50; /* (4E50) */
 476         struct r300_state_atom unk4E88; /* (4E88) */
 477         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 478         struct r300_state_atom zs;      /* zstencil control (4F00) */
 479         struct r300_state_atom zstencil_format;
 480         struct r300_state_atom zb;      /* z buffer (4F20) */
 481         struct r300_state_atom unk4F28; /* (4F28) */
 482         struct r300_state_atom unk4F30; /* (4F30) */
 483         struct r300_state_atom unk4F44; /* (4F44) */
 484         struct r300_state_atom unk4F54; /* (4F54) */
 485
 486         struct r300_state_atom vpi;     /* vp instructions */
 487         struct r300_state_atom vpp;     /* vp parameters */
 488         struct r300_state_atom vps;     /* vertex point size (?) */
 489         /* 8 texture units */
 490         /* the state is grouped by function and not by
 491            texture unit. This makes single unit updates
 492            really awkward - we are much better off
 493            updating the whole thing at once */
 494         struct {
 495                 struct r300_state_atom filter;
 496                 struct r300_state_atom filter_1;
 497                 struct r300_state_atom size;
 498                 struct r300_state_atom format;
 499                 struct r300_state_atom pitch;
 500                 struct r300_state_atom offset;
 501                 struct r300_state_atom chroma_key;
 502                 struct r300_state_atom border_color;
 503         } tex;
 504         struct r300_state_atom txe;     /* tex enable (4104) */
 505 };
 506
 507 /**
 508  * This structure holds the command buffer while it is being constructed.
 509  *
 510  * The first batch of commands in the buffer is always the state that needs
 511  * to be re-emitted when the context is lost. This batch can be skipped
 512  * otherwise.
 513  */
 514 struct r300_cmdbuf {
 515         int size;               /* DWORDs allocated for buffer */
 516         uint32_t *cmd_buf;
 517         int count_used;         /* DWORDs filled so far */
 518         int count_reemit;       /* size of re-emission batch */
 519 };
 520
 521 /**
 522  * State cache
 523  */
 524
 525 struct r300_depthbuffer_state {
 526         GLfloat scale;
 527 };
 528
 529 struct r300_stencilbuffer_state {
 530         GLuint clear;
 531         GLboolean hw_stencil;
 532
 533 };
 534
 535 /* Vertex shader state */
 536
 537 /* Perhaps more if we store programs in vmem? */
 538 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 539 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 540
 541 /* Can be tested with colormat currently. */
 542 #define VSF_MAX_FRAGMENT_TEMPS (14)
 543
 544 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 545 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 546
 547 struct r300_vertex_shader_fragment {
 548         int length;
 549         union {
 550                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 551                 float f[VSF_MAX_FRAGMENT_LENGTH];
 552                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH / 4];
 553         } body;
 554 };
 555
 556 #define VSF_DEST_PROGRAM        0x0
 557 #define VSF_DEST_MATRIX0        0x200
 558 #define VSF_DEST_MATRIX1        0x204
 559 #define VSF_DEST_MATRIX2        0x208
 560 #define VSF_DEST_VECTOR0        0x20c
 561 #define VSF_DEST_VECTOR1        0x20d
 562 #define VSF_DEST_UNKNOWN1       0x400
 563 #define VSF_DEST_UNKNOWN2       0x406
 564
 565 struct r300_vertex_shader_state {
 566         struct r300_vertex_shader_fragment program;
 567
 568         struct r300_vertex_shader_fragment unknown1;
 569         struct r300_vertex_shader_fragment unknown2;
 570
 571         int program_start;
 572         int unknown_ptr1;       /* pointer within program space */
 573         int program_end;
 574
 575         int param_offset;
 576         int param_count;
 577
 578         int unknown_ptr2;       /* pointer within program space */
 579         int unknown_ptr3;       /* pointer within program space */
 580 };
 581
 582 extern int hw_tcl_on;
 583
 584 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 585 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 586
 587 /* Should but doesnt work */
 588 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 589
 590 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 591  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 592  */
 593
 594 struct r300_vertex_program_key {
 595         GLuint InputsRead;
 596         GLuint OutputsWritten;
 597 };
 598
 599 struct r300_vertex_program {
 600         struct r300_vertex_program *next;
 601         struct r300_vertex_program_key key;
 602         int translated;
 603
 604         struct r300_vertex_shader_fragment program;
 605
 606         int pos_end;
 607         int num_temporaries;    /* Number of temp vars used by program */
 608         int wpos_idx;
 609         int inputs[VERT_ATTRIB_MAX];
 610         int outputs[VERT_RESULT_MAX];
 611         int native;
 612         int ref_count;
 613         int use_ref_count;
 614 };
 615
 616 struct r300_vertex_program_cont {
 617         struct gl_vertex_program mesa_program;  /* Must be first */
 618         struct r300_vertex_shader_fragment params;
 619         struct r300_vertex_program *progs;
 620 };
 621
 622 #define PFS_MAX_ALU_INST        64
 623 #define PFS_MAX_TEX_INST        64
 624 #define PFS_MAX_TEX_INDIRECT 4
 625 #define PFS_NUM_TEMP_REGS       32
 626 #define PFS_NUM_CONST_REGS      16
 627
 628 /* Mapping Mesa registers to R300 temporaries */
 629 struct reg_acc {
 630         int reg;                /* Assigned hw temp */
 631         unsigned int refcount;  /* Number of uses by mesa program */
 632 };
 633
 634 /**
 635  * Describe the current lifetime information for an R300 temporary
 636  */
 637 struct reg_lifetime {
 638         /* Index of the first slot where this register is free in the sense
 639            that it can be used as a new destination register.
 640            This is -1 if the register has been assigned to a Mesa register
 641            and the last access to the register has not yet been emitted */
 642         int free;
 643
 644         /* Index of the first slot where this register is currently reserved.
 645            This is used to stop e.g. a scalar operation from being moved
 646            before the allocation time of a register that was first allocated
 647            for a vector operation. */
 648         int reserved;
 649
 650         /* Index of the first slot in which the register can be used as a
 651            source without losing the value that is written by the last
 652            emitted instruction that writes to the register */
 653         int vector_valid;
 654         int scalar_valid;
 655
 656         /* Index to the slot where the register was last read.
 657            This is also the first slot in which the register may be written again */
 658         int vector_lastread;
 659         int scalar_lastread;
 660 };
 661
 662 /**
 663  * Store usage information about an ALU instruction slot during the
 664  * compilation of a fragment program.
 665  */
 666 #define SLOT_SRC_VECTOR  (1<<0)
 667 #define SLOT_SRC_SCALAR  (1<<3)
 668 #define SLOT_SRC_BOTH    (SLOT_SRC_VECTOR | SLOT_SRC_SCALAR)
 669 #define SLOT_OP_VECTOR   (1<<16)
 670 #define SLOT_OP_SCALAR   (1<<17)
 671 #define SLOT_OP_BOTH     (SLOT_OP_VECTOR | SLOT_OP_SCALAR)
 672
 673 struct r300_pfs_compile_slot {
 674         /* Bitmask indicating which parts of the slot are used, using SLOT_ constants
 675            defined above */
 676         unsigned int used;
 677
 678         /* Selected sources */
 679         int vsrc[3];
 680         int ssrc[3];
 681 };
 682
 683 /**
 684  * Store information during compilation of fragment programs.
 685  */
 686 struct r300_pfs_compile_state {
 687         int nrslots;            /* number of ALU slots used so far */
 688
 689         /* Track which (parts of) slots are already filled with instructions */
 690         struct r300_pfs_compile_slot slot[PFS_MAX_ALU_INST];
 691
 692         /* Track the validity of R300 temporaries */
 693         struct reg_lifetime hwtemps[PFS_NUM_TEMP_REGS];
 694
 695         /* Used to map Mesa's inputs/temps onto hardware temps */
 696         int temp_in_use;
 697         struct reg_acc temps[PFS_NUM_TEMP_REGS];
 698         struct reg_acc inputs[32];      /* don't actually need 32... */
 699
 700         /* Track usage of hardware temps, for register allocation,
 701          * indirection detection, etc. */
 702         GLuint used_in_node;
 703         GLuint dest_in_node;
 704 };
 705
 706 /**
 707  * Store everything about a fragment program that is needed
 708  * to render with that program.
 709  */
 710 struct r300_fragment_program {
 711         struct gl_fragment_program mesa_program;
 712
 713         GLcontext *ctx;
 714         GLboolean translated;
 715         GLboolean error;
 716         struct r300_pfs_compile_state *cs;
 717
 718         struct {
 719                 int length;
 720                 GLuint inst[PFS_MAX_TEX_INST];
 721         } tex;
 722
 723         struct {
 724                 struct {
 725                         GLuint inst0;
 726                         GLuint inst1;
 727                         GLuint inst2;
 728                         GLuint inst3;
 729                 } inst[PFS_MAX_ALU_INST];
 730         } alu;
 731
 732         struct {
 733                 int tex_offset;
 734                 int tex_end;
 735                 int alu_offset;
 736                 int alu_end;
 737                 int flags;
 738         } node[4];
 739         int cur_node;
 740         int first_node_has_tex;
 741
 742         int alu_offset;
 743         int alu_end;
 744         int tex_offset;
 745         int tex_end;
 746
 747         /* Hardware constants.
 748          * Contains a pointer to the value. The destination of the pointer
 749          * is supposed to be updated when GL state changes.
 750          * Typically, this is either a pointer into
 751          * gl_program_parameter_list::ParameterValues, or a pointer to a
 752          * global constant (e.g. for sin/cos-approximation)
 753          */
 754         const GLfloat *constant[PFS_NUM_CONST_REGS];
 755         int const_nr;
 756
 757         int max_temp_idx;
 758
 759         GLuint optimization;
 760 };
 761
 762 #define R300_MAX_AOS_ARRAYS             16
 763
 764 #define AOS_FORMAT_USHORT       0
 765 #define AOS_FORMAT_FLOAT        1
 766 #define AOS_FORMAT_UBYTE        2
 767 #define AOS_FORMAT_FLOAT_COLOR  3
 768
 769 #define REG_COORDS      0
 770 #define REG_COLOR0      1
 771 #define REG_TEX0        2
 772
 773 struct dt {
 774         GLint size;
 775         GLenum type;
 776         GLsizei stride;
 777         void *data;
 778 };
 779
 780 struct radeon_vertex_buffer {
 781         int Count;
 782         void *Elts;
 783         int elt_size;
 784         int elt_min, elt_max;   /* debug */
 785
 786         struct dt AttribPtr[VERT_ATTRIB_MAX];
 787
 788         const struct _mesa_prim *Primitive;
 789         GLuint PrimitiveCount;
 790         GLint LockFirst;
 791         GLsizei LockCount;
 792         int lock_uptodate;
 793 };
 794
 795 struct r300_aos_rec {
 796         GLuint offset;
 797         int element_size;       /* in dwords */
 798         int stride;             /* distance between elements, in dwords */
 799
 800         int format;
 801
 802         int ncomponents;        /* number of components - between 1 and 4, inclusive */
 803
 804         int reg;                /* which register they are assigned to. */
 805
 806 };
 807
 808 struct r300_state {
 809         struct r300_depthbuffer_state depth;
 810         struct r300_texture_state texture;
 811         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 812         struct r300_vertex_shader_state vertex_shader;
 813         struct r300_pfs_compile_state pfs_compile;
 814         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 815         int aos_count;
 816         struct radeon_vertex_buffer VB;
 817
 818         GLuint *Elts;
 819         struct r300_dma_region elt_dma;
 820
 821          DECLARE_RENDERINPUTS(render_inputs_bitset);    /* actual render inputs that R300 was configured for.
 822                                                            They are the same as tnl->render_inputs for fixed pipeline */
 823
 824         struct {
 825                 int transform_offset;   /* Transform matrix offset, -1 if none */
 826         } vap_param;            /* vertex processor parameter allocation - tells where to write parameters */
 827
 828         struct r300_stencilbuffer_state stencil;
 829
 830 };
 831
 832 #define R300_FALLBACK_NONE 0
 833 #define R300_FALLBACK_TCL 1
 834 #define R300_FALLBACK_RAST 2
 835
 836 /**
 837  * \brief R300 context structure.
 838  */
 839 struct r300_context {
 840         struct radeon_context radeon;   /* parent class, must be first */
 841
 842         struct r300_hw_state hw;
 843         struct r300_cmdbuf cmdbuf;
 844         struct r300_state state;
 845         struct gl_vertex_program *curr_vp;
 846         struct r300_vertex_program *selected_vp;
 847
 848         /* Vertex buffers
 849          */
 850         struct r300_dma dma;
 851         GLboolean save_on_next_unlock;
 852         GLuint NewGLState;
 853
 854         /* Texture object bookkeeping
 855          */
 856         unsigned nr_heaps;
 857         driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
 858         driTextureObject swapped;
 859         int texture_depth;
 860         float initialMaxAnisotropy;
 861
 862         /* Clientdata textures;
 863          */
 864         GLuint prefer_gart_client_texturing;
 865
 866 #ifdef USER_BUFFERS
 867         struct r300_memory_manager *rmm;
 868         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 869         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 870 #endif
 871
 872         GLboolean disable_lowimpact_fallback;
 873 };
 874
 875 struct r300_buffer_object {
 876         struct gl_buffer_object mesa_obj;
 877         int id;
 878 };
 879
 880 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 881
 882 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 883 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 884                                    __DRIcontextPrivate * driContextPriv,
 885                                    void *sharedContextPrivate);
 886
 887 extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim);
 888
 889 extern void r300SelectVertexShader(r300ContextPtr r300);
 890 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 891 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 892                                       struct r300_vertex_program_cont *vp,
 893                                       float *dst);
 894 extern int r300Fallback(GLcontext * ctx);
 895
 896 extern GLboolean r300RunRender(GLcontext * ctx,
 897                                struct tnl_pipeline_stage *stage);
 898
 899 #define RADEON_D_CAPTURE 0
 900 #define RADEON_D_PLAYBACK 1
 901 #define RADEON_D_PLAYBACK_RAW 2
 902 #define RADEON_D_T 3
 903
 904 #endif                          /* __R300_CONTEXT_H__ */