src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 #define USE_ARB_F_P 1
  51 //#define USER_BUFFERS
  52 //#define RADEON_VTXFMT_A
  53 //#define HW_VBOS
  54 //#define OPTIMIZE_ELTS
  55 #define CB_DPATH
  56
  57 struct r300_context;
  58 typedef struct r300_context r300ContextRec;
  59 typedef struct r300_context *r300ContextPtr;
  60
  61 #include "radeon_lock.h"
  62 #include "mm.h"
  63
  64 /* Checkpoint.. for convenience */
  65 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  66 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  67    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  68    with other compilers ... GLUE!
  69 */
  70 #if 1
  71 #define WARN_ONCE(a, ...)       { \
  72         static int warn##__LINE__=1; \
  73         if(warn##__LINE__){ \
  74                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  75                 fprintf(stderr, "File %s function %s line %d\n", \
  76                         __FILE__, __FUNCTION__, __LINE__); \
  77                 fprintf(stderr,  a, ## __VA_ARGS__);\
  78                 fprintf(stderr, "***************************************************************************\n"); \
  79                 warn##__LINE__=0;\
  80                 } \
  81         }
  82 #else
  83 #define WARN_ONCE(a, ...) {}
  84 #endif
  85
  86 typedef GLuint uint32_t;
  87 typedef GLubyte uint8_t;
  88 struct r300_fragment_program;
  89
  90   /* We should probably change types within vertex_shader
  91       and pixel_shader structure later on */
  92 #define CARD32 GLuint
  93 #include "vertex_shader.h"
  94 #if USE_ARB_F_P == 1
  95 #include "r300_fragprog.h"
  96 #else
  97 #include "pixel_shader.h"
  98 #endif
  99 #undef CARD32
 100
 101 static __inline__ uint32_t r300PackFloat32(float fl)
 102 {
 103         union { float fl; uint32_t u; } u;
 104
 105         u.fl = fl;
 106         return u.u;
 107 }
 108
 109
 110 /************ DMA BUFFERS **************/
 111
 112 /* Need refcounting on dma buffers:
 113  */
 114 struct r300_dma_buffer {
 115         int refcount;           /* the number of retained regions in buf */
 116         drmBufPtr buf;
 117         int id;
 118 };
 119 #ifdef USER_BUFFERS
 120 #define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start))
 121 #else
 122 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 123                         (rvb)->address - rmesa->dma.buf0_address +      \
 124                         (rvb)->start)
 125 #endif
 126 /* A retained region, eg vertices for indexed vertices.
 127  */
 128 struct r300_dma_region {
 129         struct r300_dma_buffer *buf;
 130         char *address;          /* == buf->address */
 131         int start, end, ptr;    /* offsets from start of buf */
 132
 133     int aos_offset;     /* address in GART memory */
 134     int aos_stride;     /* distance between elements, in dwords */
 135     int aos_size;       /* number of components (1-4) */
 136     int aos_format;     /* format of components */
 137     int aos_reg;        /* VAP register assignment */
 138 };
 139
 140 struct r300_dma {
 141         /* Active dma region.  Allocations for vertices and retained
 142          * regions come from here.  Also used for emitting random vertices,
 143          * these may be flushed by calling flush_current();
 144          */
 145         struct r300_dma_region current;
 146
 147         void (*flush) (r300ContextPtr);
 148
 149         char *buf0_address;     /* start of buf[0], for index calcs */
 150
 151         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 152          * for which a DISCARD command is currently queued in the command buffer.
 153          */
 154         GLuint nr_released_bufs;
 155 };
 156
 157        /* Texture related */
 158
 159 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 160
 161 /* Texture object in locally shared texture space.
 162  */
 163 struct r300_tex_obj {
 164         driTextureObject base;
 165
 166         GLuint bufAddr;         /* Offset to start of locally
 167                                    shared texture block */
 168
 169         GLuint dirty_state;     /* Flags (1 per texunit) for
 170                                    whether or not this texobj
 171                                    has dirty hardware state
 172                                    (pp_*) that needs to be
 173                                    brought into the
 174                                    texunit. */
 175
 176         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 177         /* Six, for the cube faces */
 178
 179
 180         GLuint pitch; /* this isn't sent to hardware just used in calculations */
 181         /* hardware register values */
 182         /* Note that R200 has 8 registers per texture and R300 only 7 */
 183         GLuint filter;
 184         GLuint pitch_reg;
 185         GLuint size;    /* npot only */
 186         GLuint format;
 187         GLuint offset;  /* Image location in the card's address space.
 188                                    All cube faces follow. */
 189         GLuint unknown4;
 190         GLuint unknown5;
 191         /* end hardware registers */
 192
 193         /* registers computed by r200 code - keep them here to
 194            compare against what is actually written.
 195
 196            to be removed later.. */
 197         GLuint pp_border_color;
 198         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 199         GLuint format_x;
 200
 201
 202         GLboolean border_fallback;
 203 };
 204
 205 struct r300_texture_env_state {
 206         r300TexObjPtr texobj;
 207         GLenum format;
 208         GLenum envMode;
 209 };
 210
 211 #define R300_MAX_TEXTURE_UNITS 8
 212
 213 struct r300_texture_state {
 214         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 215         int tc_count; /* number of incoming texture coordinates from VAP */
 216 };
 217
 218 /**
 219  * A block of hardware state.
 220  *
 221  * When check returns non-zero, the returned number of dwords must be
 222  * copied verbatim into the command buffer in order to update a state atom
 223  * when it is dirty.
 224  */
 225 struct r300_state_atom {
 226         struct r300_state_atom *next, *prev;
 227         const char* name;       /* for debug */
 228         int cmd_size;           /* maximum size in dwords */
 229         GLuint idx;             /* index in an array (e.g. textures) */
 230         uint32_t* cmd;
 231         GLboolean dirty;
 232
 233         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 234 };
 235
 236
 237 #define R300_VPT_CMD_0          0
 238 #define R300_VPT_XSCALE         1
 239 #define R300_VPT_XOFFSET        2
 240 #define R300_VPT_YSCALE         3
 241 #define R300_VPT_YOFFSET        4
 242 #define R300_VPT_ZSCALE         5
 243 #define R300_VPT_ZOFFSET        6
 244 #define R300_VPT_CMDSIZE        7
 245
 246 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 247 #define R300_VIR_CNTL_0         1
 248 #define R300_VIR_CNTL_1         2
 249 #define R300_VIR_CNTL_2         3
 250 #define R300_VIR_CNTL_3         4
 251 #define R300_VIR_CNTL_4         5
 252 #define R300_VIR_CNTL_5         6
 253 #define R300_VIR_CNTL_6         7
 254 #define R300_VIR_CNTL_7         8
 255 #define R300_VIR_CMDSIZE        9
 256
 257 #define R300_VIC_CMD_0          0
 258 #define R300_VIC_CNTL_0         1
 259 #define R300_VIC_CNTL_1         2
 260 #define R300_VIC_CMDSIZE        3
 261
 262 #define R300_VOF_CMD_0          0
 263 #define R300_VOF_CNTL_0         1
 264 #define R300_VOF_CNTL_1         2
 265 #define R300_VOF_CMDSIZE        3
 266
 267
 268 #define R300_PVS_CMD_0          0
 269 #define R300_PVS_CNTL_1         1
 270 #define R300_PVS_CNTL_2         2
 271 #define R300_PVS_CNTL_3         3
 272 #define R300_PVS_CMDSIZE        4
 273
 274 #define R300_GB_MISC_CMD_0              0
 275 #define R300_GB_MISC_MSPOS_0            1
 276 #define R300_GB_MISC_MSPOS_1            2
 277 #define R300_GB_MISC_TILE_CONFIG        3
 278 #define R300_GB_MISC_SELECT             4
 279 #define R300_GB_MISC_AA_CONFIG          5
 280 #define R300_GB_MISC_CMDSIZE            6
 281
 282 #define R300_TXE_CMD_0          0
 283 #define R300_TXE_ENABLE         1
 284 #define R300_TXE_CMDSIZE        2
 285
 286 #define R300_PS_CMD_0           0
 287 #define R300_PS_POINTSIZE       1
 288 #define R300_PS_CMDSIZE         2
 289
 290 #define R300_ZBS_CMD_0          0
 291 #define R300_ZBS_T_FACTOR       1
 292 #define R300_ZBS_T_CONSTANT     2
 293 #define R300_ZBS_W_FACTOR       3
 294 #define R300_ZBS_W_CONSTANT     4
 295 #define R300_ZBS_CMDSIZE        5
 296
 297 #define R300_CUL_CMD_0          0
 298 #define R300_CUL_CULL           1
 299 #define R300_CUL_CMDSIZE        2
 300
 301 #define R300_RC_CMD_0           0
 302 #define R300_RC_CNTL_0          1
 303 #define R300_RC_CNTL_1          2
 304 #define R300_RC_CMDSIZE         3
 305
 306 #define R300_RI_CMD_0           0
 307 #define R300_RI_INTERP_0        1
 308 #define R300_RI_INTERP_1        2
 309 #define R300_RI_INTERP_2        3
 310 #define R300_RI_INTERP_3        4
 311 #define R300_RI_INTERP_4        5
 312 #define R300_RI_INTERP_5        6
 313 #define R300_RI_INTERP_6        7
 314 #define R300_RI_INTERP_7        8
 315 #define R300_RI_CMDSIZE         9
 316
 317 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 318 #define R300_RR_ROUTE_0         1
 319 #define R300_RR_ROUTE_1         2
 320 #define R300_RR_ROUTE_2         3
 321 #define R300_RR_ROUTE_3         4
 322 #define R300_RR_ROUTE_4         5
 323 #define R300_RR_ROUTE_5         6
 324 #define R300_RR_ROUTE_6         7
 325 #define R300_RR_ROUTE_7         8
 326 #define R300_RR_CMDSIZE         9
 327
 328 #define R300_FP_CMD_0           0
 329 #define R300_FP_CNTL0           1
 330 #define R300_FP_CNTL1           2
 331 #define R300_FP_CNTL2           3
 332 #define R300_FP_CMD_1           4
 333 #define R300_FP_NODE0           5
 334 #define R300_FP_NODE1           6
 335 #define R300_FP_NODE2           7
 336 #define R300_FP_NODE3           8
 337 #define R300_FP_CMDSIZE         9
 338
 339 #define R300_FPT_CMD_0          0
 340 #define R300_FPT_INSTR_0        1
 341 #define R300_FPT_CMDSIZE        65
 342
 343 #define R300_FPI_CMD_0          0
 344 #define R300_FPI_INSTR_0        1
 345 #define R300_FPI_CMDSIZE        65
 346
 347 #define R300_FPP_CMD_0          0
 348 #define R300_FPP_PARAM_0        1
 349 #define R300_FPP_CMDSIZE        (32*4+1)
 350
 351 #define R300_AT_CMD_0           0
 352 #define R300_AT_ALPHA_TEST      1
 353 #define R300_AT_UNKNOWN         2
 354 #define R300_AT_CMDSIZE         3
 355
 356 #define R300_BLD_CMD_0          0
 357 #define R300_BLD_CBLEND         1
 358 #define R300_BLD_ABLEND         2
 359 #define R300_BLD_CMDSIZE        3
 360
 361 #define R300_CMK_CMD_0          0
 362 #define R300_CMK_COLORMASK      1
 363 #define R300_CMK_CMDSIZE        2
 364
 365 #define R300_CB_CMD_0           0
 366 #define R300_CB_OFFSET          1
 367 #define R300_CB_CMD_1           2
 368 #define R300_CB_PITCH           3
 369 #define R300_CB_CMDSIZE         4
 370
 371 #define R300_ZS_CMD_0           0
 372 #define R300_ZS_CNTL_0          1
 373 #define R300_ZS_CNTL_1          2
 374 #define R300_ZS_CNTL_2          3
 375 #define R300_ZS_CMDSIZE         4
 376
 377 #define R300_ZB_CMD_0           0
 378 #define R300_ZB_OFFSET          1
 379 #define R300_ZB_PITCH           2
 380 #define R300_ZB_CMDSIZE         3
 381
 382 #define R300_VPI_CMD_0          0
 383 #define R300_VPI_INSTR_0        1
 384 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 385
 386 #define R300_VPP_CMD_0          0
 387 #define R300_VPP_PARAM_0        1
 388 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 389
 390 #define R300_VPS_CMD_0          0
 391 #define R300_VPS_ZERO_0         1
 392 #define R300_VPS_ZERO_1         2
 393 #define R300_VPS_POINTSIZE      3
 394 #define R300_VPS_ZERO_3         4
 395 #define R300_VPS_CMDSIZE        5
 396
 397         /* the layout is common for all fields inside tex */
 398 #define R300_TEX_CMD_0          0
 399 #define R300_TEX_VALUE_0        1
 400 /* We don't really use this, instead specify mtu+1 dynamically
 401 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 402 */
 403
 404 /**
 405  * Cache for hardware register state.
 406  */
 407 struct r300_hw_state {
 408         struct r300_state_atom atomlist;
 409
 410         GLboolean       is_dirty;
 411         GLboolean       all_dirty;
 412         int             max_state_size; /* in dwords */
 413
 414         struct r300_state_atom vpt;     /* viewport (1D98) */
 415         struct r300_state_atom unk2080; /* (2080) */
 416         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 417         struct r300_state_atom vte;     /* (20B0) */
 418         struct r300_state_atom unk2134; /* (2134) */
 419         struct r300_state_atom unk2140; /* (2140) */
 420         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 421         struct r300_state_atom vic;     /* vap input control (2180) */
 422         struct r300_state_atom unk21DC; /* (21DC) */
 423         struct r300_state_atom unk221C; /* (221C) */
 424         struct r300_state_atom unk2220; /* (2220) */
 425         struct r300_state_atom unk2288; /* (2288) */
 426         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 427         struct r300_state_atom gb_enable; /* (4008) */
 428         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 429         struct r300_state_atom unk4200; /* (4200) */
 430         struct r300_state_atom unk4214; /* (4214) */
 431         struct r300_state_atom ps;      /* pointsize (421C) */
 432         struct r300_state_atom unk4230; /* (4230) */
 433         struct r300_state_atom lcntl;   /* line control */
 434         struct r300_state_atom unk4260; /* (4260) */
 435         struct r300_state_atom unk4274; /* (4274) */
 436         struct r300_state_atom unk4288; /* (4288) */
 437         struct r300_state_atom unk42A0; /* (42A0) */
 438         struct r300_state_atom zbs;     /* zbias (42A4) */
 439         struct r300_state_atom unk42B4; /* (42B4) */
 440         struct r300_state_atom cul;     /* cull cntl (42B8) */
 441         struct r300_state_atom unk42C0; /* (42C0) */
 442         struct r300_state_atom rc;      /* rs control (4300) */
 443         struct r300_state_atom ri;      /* rs interpolators (4310) */
 444         struct r300_state_atom rr;      /* rs route (4330) */
 445         struct r300_state_atom unk43A4; /* (43A4) */
 446         struct r300_state_atom unk43E8; /* (43E8) */
 447         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 448         struct r300_state_atom fpt;     /* texi - (4620) */
 449         struct r300_state_atom unk46A4; /* (46A4) */
 450         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 451         struct r300_state_atom unk4BC0; /* (4BC0) */
 452         struct r300_state_atom unk4BC8; /* (4BC8) */
 453         struct r300_state_atom at;      /* alpha test (4BD4) */
 454         struct r300_state_atom unk4BD8; /* (4BD8) */
 455         struct r300_state_atom fpp;     /* 0x4C00 and following */
 456         struct r300_state_atom unk4E00; /* (4E00) */
 457         struct r300_state_atom bld;     /* blending (4E04) */
 458         struct r300_state_atom cmk;     /* colormask (4E0C) */
 459         struct r300_state_atom unk4E10; /* constant blend color + ??? (4E10) */
 460         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 461         struct r300_state_atom unk4E50; /* (4E50) */
 462         struct r300_state_atom unk4E88; /* (4E88) */
 463         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 464         struct r300_state_atom zs;      /* zstencil control (4F00) */
 465         struct r300_state_atom unk4F10; /* (4F10) */
 466         struct r300_state_atom zb;      /* z buffer (4F20) */
 467         struct r300_state_atom unk4F28; /* (4F28) */
 468         struct r300_state_atom unk4F30; /* (4F30) */
 469         struct r300_state_atom unk4F44; /* (4F44) */
 470         struct r300_state_atom unk4F54; /* (4F54) */
 471
 472         struct r300_state_atom vpi;     /* vp instructions */
 473         struct r300_state_atom vpp;     /* vp parameters */
 474         struct r300_state_atom vps;     /* vertex point size (?) */
 475                 /* 8 texture units */
 476                 /* the state is grouped by function and not by
 477                    texture unit. This makes single unit updates
 478                    really awkward - we are much better off
 479                    updating the whole thing at once */
 480         struct {
 481                 struct r300_state_atom filter;
 482                 struct r300_state_atom unknown1;
 483                 struct r300_state_atom size;
 484                 struct r300_state_atom format;
 485                 struct r300_state_atom pitch;
 486                 struct r300_state_atom offset;
 487                 struct r300_state_atom unknown4;
 488                 struct r300_state_atom border_color;
 489                 } tex;
 490         struct r300_state_atom txe;     /* tex enable (4104) */
 491 };
 492
 493
 494 /**
 495  * This structure holds the command buffer while it is being constructed.
 496  *
 497  * The first batch of commands in the buffer is always the state that needs
 498  * to be re-emitted when the context is lost. This batch can be skipped
 499  * otherwise.
 500  */
 501 struct r300_cmdbuf {
 502         int             size;           /* DWORDs allocated for buffer */
 503         uint32_t*       cmd_buf;
 504         int             count_used;     /* DWORDs filled so far */
 505         int             count_reemit;   /* size of re-emission batch */
 506 };
 507
 508
 509 /**
 510  * State cache
 511  */
 512
 513 struct r300_depthbuffer_state {
 514         GLfloat scale;
 515 };
 516
 517 struct r300_stencilbuffer_state {
 518         GLuint clear;
 519         GLboolean hw_stencil;
 520
 521 };
 522
 523 struct r300_vap_reg_state {
 524            /* input register assigments */
 525            int i_coords;
 526            int i_normal;
 527            int i_color[2];
 528            int i_fog;
 529            int i_tex[R300_MAX_TEXTURE_UNITS];
 530            int i_index;
 531            int i_pointsize;
 532         };
 533
 534 /* Vertex shader state */
 535
 536 /* Perhaps more if we store programs in vmem? */
 537 #define VSF_MAX_FRAGMENT_LENGTH (256*4)
 538
 539 /* Can be tested with colormat currently. */
 540 #define VSF_MAX_FRAGMENT_TEMPS (14)
 541
 542
 543 struct r300_vertex_shader_fragment {
 544         int length;
 545         union {
 546                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 547                 float f[VSF_MAX_FRAGMENT_LENGTH];
 548                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH/4];
 549                 } body;
 550         };
 551
 552 #define VSF_DEST_PROGRAM        0x0
 553 #define VSF_DEST_MATRIX0        0x200
 554 #define VSF_DEST_MATRIX1        0x204
 555 #define VSF_DEST_MATRIX2        0x208
 556 #define VSF_DEST_VECTOR0        0x20c
 557 #define VSF_DEST_VECTOR1        0x20d
 558 #define VSF_DEST_UNKNOWN1       0x400
 559 #define VSF_DEST_UNKNOWN2       0x406
 560
 561 struct r300_vertex_shader_state {
 562         struct r300_vertex_shader_fragment program;
 563
 564         /* a bit of a waste - each uses only a subset of allocated space..
 565             but easier to program */
 566         struct r300_vertex_shader_fragment matrix[3];
 567         struct r300_vertex_shader_fragment vector[2];
 568
 569         struct r300_vertex_shader_fragment unknown1;
 570         struct r300_vertex_shader_fragment unknown2;
 571
 572         int program_start;
 573         int unknown_ptr1;  /* pointer within program space */
 574         int program_end;
 575
 576         int param_offset;
 577         int param_count;
 578
 579         int unknown_ptr2;  /* pointer within program space */
 580         int unknown_ptr3;  /* pointer within program space */
 581         };
 582
 583 extern int hw_tcl_on;
 584
 585 #define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 586
 587 //#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && (OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit)))) :
 588 //      (r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit))))
 589 //#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit))) :
 590 //      ctx->Texture.Unit[unit]._ReallyEnabled && r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit)))
 591
 592 #define TMU_ENABLED(ctx, unit) (ctx->Texture.Unit[unit]._ReallyEnabled)
 593
 594 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 595  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 596  */
 597 struct r300_vertex_program {
 598         struct vertex_program mesa_program; /* Must be first */
 599         int translated;
 600
 601         struct r300_vertex_shader_fragment program;
 602         struct r300_vertex_shader_fragment params;
 603
 604         int pos_end;
 605         int num_temporaries; /* Number of temp vars used by program */
 606         int inputs[VERT_ATTRIB_MAX];
 607         int outputs[VERT_RESULT_MAX];
 608 };
 609
 610 #if USE_ARB_F_P == 1
 611 #define PFS_MAX_ALU_INST        64
 612 #define PFS_MAX_TEX_INST        64
 613 #define PFS_MAX_TEX_INDIRECT 4
 614 #define PFS_NUM_TEMP_REGS       32
 615 #define PFS_NUM_CONST_REGS      32
 616 struct r300_fragment_program {
 617         struct fragment_program mesa_program;
 618
 619         GLcontext *ctx;
 620         GLboolean translated;
 621         GLboolean error;
 622
 623         struct {
 624                 int length;
 625                 GLuint inst[PFS_MAX_TEX_INST];
 626         } tex;
 627
 628         struct {
 629                 struct {
 630                         GLuint inst0;
 631                         GLuint inst1;
 632                         GLuint inst2;
 633                         GLuint inst3;
 634                 } inst[PFS_MAX_ALU_INST];
 635         } alu;
 636         int v_pos;
 637         int s_pos;
 638
 639         struct {
 640                 int tex_offset;
 641                 int tex_end;
 642                 int alu_offset;
 643                 int alu_end;
 644         } node[4];
 645         int cur_node;
 646         int first_node_has_tex;
 647
 648         int alu_offset;
 649         int alu_end;
 650         int tex_offset;
 651         int tex_end;
 652
 653         /* Hardware constants */
 654         GLfloat constant[PFS_NUM_CONST_REGS][4];
 655         int const_nr;
 656
 657         /* Tracked parameters */
 658         struct {
 659                 int idx;                        /* hardware index */
 660                 GLfloat *values;        /* pointer to values */
 661         } param[PFS_NUM_CONST_REGS];
 662         int param_nr;
 663         GLboolean params_uptodate;
 664
 665         GLuint temps[PFS_NUM_TEMP_REGS];
 666         int temp_in_use;
 667         GLuint used_in_node;
 668         GLuint dest_in_node;
 669         GLuint inputs[32]; /* don't actually need 32... */
 670
 671         int hwreg_in_use;
 672         int max_temp_idx;
 673 };
 674
 675 #else
 676 /* 64 appears to be the maximum */
 677 #define PSF_MAX_PROGRAM_LENGTH 64
 678
 679 struct r300_pixel_shader_program {
 680         struct {
 681                 int length;
 682                 GLuint inst[PSF_MAX_PROGRAM_LENGTH];
 683                 } tex;
 684
 685         /* ALU intructions (logic and integer) */
 686         struct {
 687                 int length;
 688                 struct {
 689                         GLuint inst0;
 690                         GLuint inst1;
 691                         GLuint inst2;
 692                         GLuint inst3;
 693                         } inst[PSF_MAX_PROGRAM_LENGTH];
 694                 } alu;
 695
 696         /* node information */
 697         /* nodes are used to synchronize ALU and TEX streams */
 698         /* There could be up to 4 nodes each consisting of
 699            a number of TEX instructions followed by some ALU
 700            instructions */
 701         /* the last node of a program should always be node3 */
 702         struct {
 703                 int tex_offset;
 704                 int tex_end;
 705                 int alu_offset;
 706                 int alu_end;
 707                 } node[4];
 708
 709         int active_nodes;       /* must be between 1 and 4, inclusive */
 710         int first_node_has_tex;  /* other nodes always have it */
 711
 712         int temp_register_count;  /* magic value goes into PFS_CNTL_1 */
 713
 714         /* entire program */
 715         int tex_offset;
 716         int tex_end;
 717         int alu_offset;
 718         int alu_end;
 719
 720         };
 721
 722 #define MAX_PIXEL_SHADER_PARAMS 32
 723 struct r300_pixel_shader_state {
 724         struct r300_pixel_shader_program program;
 725
 726         int translated;
 727         int have_sample;
 728         GLuint color_reg;
 729         GLuint src_previous;
 730
 731         /* parameters */
 732         int param_length;  /* to limit the number of unnecessary writes */
 733         struct {
 734                 float x;
 735                 float y;
 736                 float z;
 737                 float w;
 738                 } param[MAX_PIXEL_SHADER_PARAMS];
 739         };
 740 #endif // USE_ARB_F_P
 741
 742 /* 8 is somewhat bogus... it is probably something like 24 */
 743 #define R300_MAX_AOS_ARRAYS             16
 744
 745 #define AOS_FORMAT_FLOAT        1
 746 #define AOS_FORMAT_UBYTE        2
 747 #define AOS_FORMAT_FLOAT_COLOR  3
 748
 749 #define REG_COORDS      0
 750 #define REG_COLOR0      1
 751 #define REG_TEX0        2
 752
 753 #ifdef USER_BUFFERS
 754 struct dt {
 755         GLint size;
 756         GLenum type;
 757         GLsizei stride;
 758         void *data;
 759 };
 760
 761 struct radeon_vertex_buffer {
 762         int Count;
 763         void *Elts;
 764         int elt_size;
 765         int elt_min, elt_max; /* debug */
 766
 767         struct dt AttribPtr[VERT_ATTRIB_MAX];
 768
 769         struct tnl_prim  *Primitive;
 770         GLuint      PrimitiveCount;
 771         GLint LockFirst;
 772         GLsizei LockCount;
 773         int lock_uptodate;
 774 };
 775 #endif
 776
 777 struct r300_aos_rec {
 778         GLuint offset;
 779         int element_size; /* in dwords */
 780         int stride;       /* distance between elements, in dwords */
 781
 782         int format;
 783
 784         int ncomponents; /* number of components - between 1 and 4, inclusive */
 785
 786         int reg; /* which register they are assigned to. */
 787
 788         };
 789
 790 struct r300_state {
 791         struct r300_depthbuffer_state depth;
 792         struct r300_texture_state texture;
 793         struct r300_vap_reg_state vap_reg;
 794         struct r300_vertex_shader_state vertex_shader;
 795 #if USE_ARB_F_P == 0
 796         struct r300_pixel_shader_state pixel_shader;
 797 #endif
 798         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 799         int aos_count;
 800 #ifdef USER_BUFFERS
 801         struct radeon_vertex_buffer VB;
 802 #endif
 803
 804         GLuint *Elts;
 805         struct r300_dma_region elt_dma;
 806
 807         GLuint render_inputs; /* actual render inputs that R300 was configured for.
 808                                  They are the same as tnl->render_inputs for fixed pipeline */
 809
 810         struct {
 811                 int transform_offset;  /* Transform matrix offset, -1 if none */
 812                 } vap_param;  /* vertex processor parameter allocation - tells where to write parameters */
 813
 814         struct r300_stencilbuffer_state stencil;
 815
 816 };
 817
 818
 819 /**
 820  * R300 context structure.
 821  */
 822 struct r300_context {
 823         struct radeon_context radeon; /* parent class, must be first */
 824
 825         struct r300_hw_state hw;
 826         struct r300_cmdbuf cmdbuf;
 827         struct r300_state state;
 828
 829         /* Vertex buffers
 830          */
 831         struct r300_dma dma;
 832         GLboolean save_on_next_unlock;
 833         GLuint NewGLState;
 834
 835         /* Texture object bookkeeping
 836          */
 837         unsigned nr_heaps;
 838         driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
 839         driTextureObject swapped;
 840         int texture_depth;
 841         float initialMaxAnisotropy;
 842
 843         /* Clientdata textures;
 844          */
 845         GLuint prefer_gart_client_texturing;
 846
 847 #ifdef USER_BUFFERS
 848         key_t mm_ipc_key;
 849         int mm_shm_id;
 850         int mm_sem_id;
 851         struct radeon_memory_manager *rmm;
 852 #endif
 853 };
 854
 855 struct r300_buffer_object {
 856         struct gl_buffer_object mesa_obj;
 857         int id;
 858 };
 859
 860 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 861
 862 static __inline GLuint r300PackColor( GLuint cpp,
 863                                         GLubyte r, GLubyte g,
 864                                         GLubyte b, GLubyte a )
 865 {
 866    switch ( cpp ) {
 867    case 2:
 868       return PACK_COLOR_565( r, g, b );
 869    case 4:
 870       return PACK_COLOR_8888( r, g, b, a );
 871    default:
 872       return 0;
 873    }
 874 }
 875 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 876 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 877                                    __DRIcontextPrivate * driContextPriv,
 878                                    void *sharedContextPrivate);
 879
 880 void translate_vertex_shader(struct r300_vertex_program *vp);
 881 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 882 extern int r300VertexProgUpdateParams(GLcontext *ctx, struct r300_vertex_program *vp, float *dst);
 883 extern GLboolean r300Fallback(GLcontext *ctx);
 884
 885 #ifdef RADEON_VTXFMT_A
 886 extern void radeon_init_vtxfmt_a(r300ContextPtr rmesa);
 887 #endif
 888
 889 #ifdef HW_VBOS
 890 extern void r300_init_vbo_funcs(struct dd_function_table *functions);
 891 #endif
 892
 893 #endif                          /* __R300_CONTEXT_H__ */