src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45 #include "radeon_context.h"
  46 #include "radeon_bo.h"
  47
  48 #include "main/macros.h"
  49 #include "main/mtypes.h"
  50 #include "main/colormac.h"
  51
  52 struct r300_context;
  53 typedef struct r300_context r300ContextRec;
  54 typedef struct r300_context *r300ContextPtr;
  55
  56 #include "radeon_lock.h"
  57 #include "main/mm.h"
  58
  59 /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  60    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  61    with other compilers ... GLUE!
  62 */
  63 #define WARN_ONCE(a, ...)       { \
  64         static int warn##__LINE__=1; \
  65         if(warn##__LINE__){ \
  66                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  67                 fprintf(stderr, "File %s function %s line %d\n", \
  68                         __FILE__, __FUNCTION__, __LINE__); \
  69                 fprintf(stderr,  a, ## __VA_ARGS__);\
  70                 fprintf(stderr, "***************************************************************************\n"); \
  71                 warn##__LINE__=0;\
  72                 } \
  73         }
  74
  75 #include "r300_vertprog.h"
  76 #include "r500_fragprog.h"
  77
  78
  79
  80 /************ DMA BUFFERS **************/
  81
  82 /* The blit width for texture uploads
  83  */
  84 #define R300_BLIT_WIDTH_BYTES 1024
  85 #define R300_MAX_TEXTURE_UNITS 8
  86
  87 struct r300_texture_state {
  88         int tc_count;           /* number of incoming texture coordinates from VAP */
  89 };
  90
  91
  92 #define R300_VPT_CMD_0          0
  93 #define R300_VPT_XSCALE         1
  94 #define R300_VPT_XOFFSET        2
  95 #define R300_VPT_YSCALE         3
  96 #define R300_VPT_YOFFSET        4
  97 #define R300_VPT_ZSCALE         5
  98 #define R300_VPT_ZOFFSET        6
  99 #define R300_VPT_CMDSIZE        7
 100
 101 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
 102 #define R300_VIR_CNTL_0         1
 103 #define R300_VIR_CNTL_1         2
 104 #define R300_VIR_CNTL_2         3
 105 #define R300_VIR_CNTL_3         4
 106 #define R300_VIR_CNTL_4         5
 107 #define R300_VIR_CNTL_5         6
 108 #define R300_VIR_CNTL_6         7
 109 #define R300_VIR_CNTL_7         8
 110 #define R300_VIR_CMDSIZE        9
 111
 112 #define R300_VIC_CMD_0          0
 113 #define R300_VIC_CNTL_0         1
 114 #define R300_VIC_CNTL_1         2
 115 #define R300_VIC_CMDSIZE        3
 116
 117 #define R300_VOF_CMD_0          0
 118 #define R300_VOF_CNTL_0         1
 119 #define R300_VOF_CNTL_1         2
 120 #define R300_VOF_CMDSIZE        3
 121
 122 #define R300_PVS_CMD_0          0
 123 #define R300_PVS_CNTL_1         1
 124 #define R300_PVS_CNTL_2         2
 125 #define R300_PVS_CNTL_3         3
 126 #define R300_PVS_CMDSIZE        4
 127
 128 #define R300_GB_MISC_CMD_0              0
 129 #define R300_GB_MISC_MSPOS_0            1
 130 #define R300_GB_MISC_MSPOS_1            2
 131 #define R300_GB_MISC_TILE_CONFIG        3
 132 #define R300_GB_MISC_SELECT             4
 133 #define R300_GB_MISC_AA_CONFIG          5
 134 #define R300_GB_MISC_CMDSIZE            6
 135
 136 #define R300_TXE_CMD_0          0
 137 #define R300_TXE_ENABLE         1
 138 #define R300_TXE_CMDSIZE        2
 139
 140 #define R300_PS_CMD_0           0
 141 #define R300_PS_POINTSIZE       1
 142 #define R300_PS_CMDSIZE         2
 143
 144 #define R300_ZBS_CMD_0          0
 145 #define R300_ZBS_T_FACTOR       1
 146 #define R300_ZBS_T_CONSTANT     2
 147 #define R300_ZBS_W_FACTOR       3
 148 #define R300_ZBS_W_CONSTANT     4
 149 #define R300_ZBS_CMDSIZE        5
 150
 151 #define R300_CUL_CMD_0          0
 152 #define R300_CUL_CULL           1
 153 #define R300_CUL_CMDSIZE        2
 154
 155 #define R300_RC_CMD_0           0
 156 #define R300_RC_CNTL_0          1
 157 #define R300_RC_CNTL_1          2
 158 #define R300_RC_CMDSIZE         3
 159
 160 #define R300_RI_CMD_0           0
 161 #define R300_RI_INTERP_0        1
 162 #define R300_RI_INTERP_1        2
 163 #define R300_RI_INTERP_2        3
 164 #define R300_RI_INTERP_3        4
 165 #define R300_RI_INTERP_4        5
 166 #define R300_RI_INTERP_5        6
 167 #define R300_RI_INTERP_6        7
 168 #define R300_RI_INTERP_7        8
 169 #define R300_RI_CMDSIZE         9
 170
 171 #define R500_RI_CMDSIZE        17
 172
 173 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 174 #define R300_RR_INST_0          1
 175 #define R300_RR_INST_1          2
 176 #define R300_RR_INST_2          3
 177 #define R300_RR_INST_3          4
 178 #define R300_RR_INST_4          5
 179 #define R300_RR_INST_5          6
 180 #define R300_RR_INST_6          7
 181 #define R300_RR_INST_7          8
 182 #define R300_RR_CMDSIZE         9
 183
 184 #define R300_FP_CMD_0           0
 185 #define R300_FP_CNTL0           1
 186 #define R300_FP_CNTL1           2
 187 #define R300_FP_CNTL2           3
 188 #define R300_FP_CMD_1           4
 189 #define R300_FP_NODE0           5
 190 #define R300_FP_NODE1           6
 191 #define R300_FP_NODE2           7
 192 #define R300_FP_NODE3           8
 193 #define R300_FP_CMDSIZE         9
 194
 195 #define R500_FP_CMD_0           0
 196 #define R500_FP_CNTL            1
 197 #define R500_FP_PIXSIZE         2
 198 #define R500_FP_CMD_1           3
 199 #define R500_FP_CODE_ADDR       4
 200 #define R500_FP_CODE_RANGE      5
 201 #define R500_FP_CODE_OFFSET     6
 202 #define R500_FP_CMD_2           7
 203 #define R500_FP_FC_CNTL         8
 204 #define R500_FP_CMDSIZE         9
 205
 206 #define R300_FPT_CMD_0          0
 207 #define R300_FPT_INSTR_0        1
 208 #define R300_FPT_CMDSIZE        65
 209
 210 #define R300_FPI_CMD_0          0
 211 #define R300_FPI_INSTR_0        1
 212 #define R300_FPI_CMDSIZE        65
 213 /* R500 has space for 512 instructions - 6 dwords per instruction */
 214 #define R500_FPI_CMDSIZE        (512*6+1)
 215
 216 #define R300_FPP_CMD_0          0
 217 #define R300_FPP_PARAM_0        1
 218 #define R300_FPP_CMDSIZE        (32*4+1)
 219 /* R500 has spcae for 256 constants - 4 dwords per constant */
 220 #define R500_FPP_CMDSIZE        (256*4+1)
 221
 222 #define R300_FOGS_CMD_0         0
 223 #define R300_FOGS_STATE         1
 224 #define R300_FOGS_CMDSIZE       2
 225
 226 #define R300_FOGC_CMD_0         0
 227 #define R300_FOGC_R             1
 228 #define R300_FOGC_G             2
 229 #define R300_FOGC_B             3
 230 #define R300_FOGC_CMDSIZE       4
 231
 232 #define R300_FOGP_CMD_0         0
 233 #define R300_FOGP_SCALE         1
 234 #define R300_FOGP_START         2
 235 #define R300_FOGP_CMDSIZE       3
 236
 237 #define R300_AT_CMD_0           0
 238 #define R300_AT_ALPHA_TEST      1
 239 #define R300_AT_UNKNOWN         2
 240 #define R300_AT_CMDSIZE         3
 241
 242 #define R300_BLD_CMD_0          0
 243 #define R300_BLD_CBLEND         1
 244 #define R300_BLD_ABLEND         2
 245 #define R300_BLD_CMDSIZE        3
 246
 247 #define R300_CMK_CMD_0          0
 248 #define R300_CMK_COLORMASK      1
 249 #define R300_CMK_CMDSIZE        2
 250
 251 #define R300_CB_CMD_0           0
 252 #define R300_CB_OFFSET          1
 253 #define R300_CB_CMD_1           2
 254 #define R300_CB_PITCH           3
 255 #define R300_CB_CMDSIZE         4
 256
 257 #define R300_ZS_CMD_0           0
 258 #define R300_ZS_CNTL_0          1
 259 #define R300_ZS_CNTL_1          2
 260 #define R300_ZS_CNTL_2          3
 261 #define R300_ZS_CMDSIZE         4
 262
 263 #define R300_ZB_CMD_0           0
 264 #define R300_ZB_OFFSET          1
 265 #define R300_ZB_PITCH           2
 266 #define R300_ZB_CMDSIZE         3
 267
 268 #define R300_VAP_CNTL_FLUSH     0
 269 #define R300_VAP_CNTL_FLUSH_1   1
 270 #define R300_VAP_CNTL_CMD       2
 271 #define R300_VAP_CNTL_INSTR     3
 272 #define R300_VAP_CNTL_SIZE      4
 273
 274 #define R300_VPI_CMD_0          0
 275 #define R300_VPI_INSTR_0        1
 276 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 277
 278 #define R300_VPP_CMD_0          0
 279 #define R300_VPP_PARAM_0        1
 280 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 281
 282 #define R300_VPUCP_CMD_0                0
 283 #define R300_VPUCP_X            1
 284 #define R300_VPUCP_Y            2
 285 #define R300_VPUCP_Z            3
 286 #define R300_VPUCP_W            4
 287 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 288
 289 #define R300_VPS_CMD_0          0
 290 #define R300_VPS_ZERO_0         1
 291 #define R300_VPS_ZERO_1         2
 292 #define R300_VPS_POINTSIZE      3
 293 #define R300_VPS_ZERO_3         4
 294 #define R300_VPS_CMDSIZE        5
 295
 296         /* the layout is common for all fields inside tex */
 297 #define R300_TEX_CMD_0          0
 298 #define R300_TEX_VALUE_0        1
 299 /* We don't really use this, instead specify mtu+1 dynamically
 300 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 301 */
 302
 303 /**
 304  * Cache for hardware register state.
 305  */
 306 struct r300_hw_state {
 307         struct radeon_state_atom atomlist;
 308
 309         GLboolean is_dirty;
 310         GLboolean all_dirty;
 311         int max_state_size;     /* in dwords */
 312
 313         struct radeon_state_atom vpt;   /* viewport (1D98) */
 314         struct radeon_state_atom vap_cntl;
 315         struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
 316         struct radeon_state_atom vof;   /* VAP output format register 0x2090 */
 317         struct radeon_state_atom vte;   /* (20B0) */
 318         struct radeon_state_atom vap_vf_max_vtx_indx;   /* Maximum Vertex Indx Clamp (2134) */
 319         struct radeon_state_atom vap_cntl_status;
 320         struct radeon_state_atom vir[2];        /* vap input route (2150/21E0) */
 321         struct radeon_state_atom vic;   /* vap input control (2180) */
 322         struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 323         struct radeon_state_atom vap_clip_cntl;
 324         struct radeon_state_atom vap_clip;
 325         struct radeon_state_atom vap_pvs_vtx_timeout_reg;       /* Vertex timeout register (2288) */
 326         struct radeon_state_atom pvs;   /* pvs_cntl (22D0) */
 327         struct radeon_state_atom gb_enable;     /* (4008) */
 328         struct radeon_state_atom gb_misc;       /* Multisampling position shifts ? (4010) */
 329         struct radeon_state_atom ga_point_s0;   /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 330         struct radeon_state_atom ga_triangle_stipple;   /* (4214) */
 331         struct radeon_state_atom ps;    /* pointsize (421C) */
 332         struct radeon_state_atom ga_point_minmax;       /* (4230) */
 333         struct radeon_state_atom lcntl; /* line control */
 334         struct radeon_state_atom ga_line_stipple;       /* (4260) */
 335         struct radeon_state_atom shade;
 336         struct radeon_state_atom polygon_mode;
 337         struct radeon_state_atom fogp;  /* fog parameters (4294) */
 338         struct radeon_state_atom ga_soft_reset; /* (429C) */
 339         struct radeon_state_atom zbias_cntl;
 340         struct radeon_state_atom zbs;   /* zbias (42A4) */
 341         struct radeon_state_atom occlusion_cntl;
 342         struct radeon_state_atom cul;   /* cull cntl (42B8) */
 343         struct radeon_state_atom su_depth_scale;        /* (42C0) */
 344         struct radeon_state_atom rc;    /* rs control (4300) */
 345         struct radeon_state_atom ri;    /* rs interpolators (4310) */
 346         struct radeon_state_atom rr;    /* rs route (4330) */
 347         struct radeon_state_atom sc_hyperz;     /* (43A4) */
 348         struct radeon_state_atom sc_screendoor; /* (43E8) */
 349         struct radeon_state_atom fp;    /* fragment program cntl + nodes (4600) */
 350         struct radeon_state_atom fpt;   /* texi - (4620) */
 351         struct radeon_state_atom us_out_fmt;    /* (46A4) */
 352         struct radeon_state_atom r500fp;        /* r500 fp instructions */
 353         struct radeon_state_atom r500fp_const;  /* r500 fp constants */
 354         struct radeon_state_atom fpi[4];        /* fp instructions (46C0/47C0/48C0/49C0) */
 355         struct radeon_state_atom fogs;  /* fog state (4BC0) */
 356         struct radeon_state_atom fogc;  /* fog color (4BC8) */
 357         struct radeon_state_atom at;    /* alpha test (4BD4) */
 358         struct radeon_state_atom fg_depth_src;  /* (4BD8) */
 359         struct radeon_state_atom fpp;   /* 0x4C00 and following */
 360         struct radeon_state_atom rb3d_cctl;     /* (4E00) */
 361         struct radeon_state_atom bld;   /* blending (4E04) */
 362         struct radeon_state_atom cmk;   /* colormask (4E0C) */
 363         struct radeon_state_atom blend_color;   /* constant blend color */
 364         struct radeon_state_atom rop;   /* ropcntl */
 365         struct radeon_state_atom cb;    /* colorbuffer (4E28) */
 366         struct radeon_state_atom rb3d_dither_ctl;       /* (4E50) */
 367         struct radeon_state_atom rb3d_aaresolve_ctl;    /* (4E88) */
 368         struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold;  /* (4E88) I saw it only written on RV350 hardware..  */
 369         struct radeon_state_atom zs;    /* zstencil control (4F00) */
 370         struct radeon_state_atom zstencil_format;
 371         struct radeon_state_atom zb;    /* z buffer (4F20) */
 372         struct radeon_state_atom zb_depthclearvalue;    /* (4F28) */
 373         struct radeon_state_atom unk4F30;       /* (4F30) */
 374         struct radeon_state_atom zb_hiz_offset; /* (4F44) */
 375         struct radeon_state_atom zb_hiz_pitch;  /* (4F54) */
 376
 377         struct radeon_state_atom vpi;   /* vp instructions */
 378         struct radeon_state_atom vpp;   /* vp parameters */
 379         struct radeon_state_atom vps;   /* vertex point size (?) */
 380         struct radeon_state_atom vpucp[6];      /* vp user clip plane - 6 */
 381         /* 8 texture units */
 382         /* the state is grouped by function and not by
 383            texture unit. This makes single unit updates
 384            really awkward - we are much better off
 385            updating the whole thing at once */
 386         struct {
 387                 struct radeon_state_atom filter;
 388                 struct radeon_state_atom filter_1;
 389                 struct radeon_state_atom size;
 390                 struct radeon_state_atom format;
 391                 struct radeon_state_atom pitch;
 392                 struct radeon_state_atom offset;
 393                 struct radeon_state_atom chroma_key;
 394                 struct radeon_state_atom border_color;
 395         } tex;
 396         struct radeon_state_atom txe;   /* tex enable (4104) */
 397
 398         radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
 399 };
 400
 401 /**
 402  * State cache
 403  */
 404
 405 /* Vertex shader state */
 406
 407 /* Perhaps more if we store programs in vmem? */
 408 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 409 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 410
 411 /* Can be tested with colormat currently. */
 412 #define VSF_MAX_FRAGMENT_TEMPS (14)
 413
 414 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 415 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 416
 417 struct r300_vertex_shader_fragment {
 418         int length;
 419         union {
 420                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 421                 float f[VSF_MAX_FRAGMENT_LENGTH];
 422                 GLuint i[VSF_MAX_FRAGMENT_LENGTH];
 423         } body;
 424 };
 425
 426 struct r300_vertex_shader_state {
 427         struct r300_vertex_shader_fragment program;
 428 };
 429
 430 extern int hw_tcl_on;
 431
 432 #define COLOR_IS_RGBA
 433 #define TAG(x) r300##x
 434 #include "tnl_dd/t_dd_vertex.h"
 435 #undef TAG
 436
 437 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 438 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 439
 440 /* Should but doesnt work */
 441 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 442
 443 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 444  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 445  */
 446
 447 struct r300_vertex_program_key {
 448         GLuint InputsRead;
 449         GLuint OutputsWritten;
 450         GLuint OutputsAdded;
 451 };
 452
 453 struct r300_vertex_program {
 454         struct r300_vertex_program *next;
 455         struct r300_vertex_program_key key;
 456         int translated;
 457
 458         struct r300_vertex_shader_fragment program;
 459
 460         int pos_end;
 461         int num_temporaries;    /* Number of temp vars used by program */
 462         int wpos_idx;
 463         int inputs[VERT_ATTRIB_MAX];
 464         int outputs[VERT_RESULT_MAX];
 465         int native;
 466         int ref_count;
 467         int use_ref_count;
 468 };
 469
 470 struct r300_vertex_program_cont {
 471         struct gl_vertex_program mesa_program;  /* Must be first */
 472         struct r300_vertex_shader_fragment params;
 473         struct r300_vertex_program *progs;
 474 };
 475
 476 #define PFS_MAX_ALU_INST        64
 477 #define PFS_MAX_TEX_INST        64
 478 #define PFS_MAX_TEX_INDIRECT 4
 479 #define PFS_NUM_TEMP_REGS       32
 480 #define PFS_NUM_CONST_REGS      16
 481
 482 struct r300_pfs_compile_state;
 483
 484
 485 /**
 486  * Stores state that influences the compilation of a fragment program.
 487  */
 488 struct r300_fragment_program_external_state {
 489         struct {
 490                 /**
 491                  * If the sampler is used as a shadow sampler,
 492                  * this field is:
 493                  *  0 - GL_LUMINANCE
 494                  *  1 - GL_INTENSITY
 495                  *  2 - GL_ALPHA
 496                  * depending on the depth texture mode.
 497                  */
 498                 GLuint depth_texture_mode : 2;
 499
 500                 /**
 501                  * If the sampler is used as a shadow sampler,
 502                  * this field is (texture_compare_func - GL_NEVER).
 503                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 504                  *
 505                  * Otherwise, this field is 0.
 506                  */
 507                 GLuint texture_compare_func : 3;
 508         } unit[16];
 509 };
 510
 511
 512 struct r300_fragment_program_node {
 513         int tex_offset; /**< first tex instruction */
 514         int tex_end; /**< last tex instruction, relative to tex_offset */
 515         int alu_offset; /**< first ALU instruction */
 516         int alu_end; /**< last ALU instruction, relative to alu_offset */
 517         int flags;
 518 };
 519
 520 /**
 521  * Stores an R300 fragment program in its compiled-to-hardware form.
 522  */
 523 struct r300_fragment_program_code {
 524         struct {
 525                 int length; /**< total # of texture instructions used */
 526                 GLuint inst[PFS_MAX_TEX_INST];
 527         } tex;
 528
 529         struct {
 530                 int length; /**< total # of ALU instructions used */
 531                 struct {
 532                         GLuint inst0;
 533                         GLuint inst1;
 534                         GLuint inst2;
 535                         GLuint inst3;
 536                 } inst[PFS_MAX_ALU_INST];
 537         } alu;
 538
 539         struct r300_fragment_program_node node[4];
 540         int cur_node;
 541         int first_node_has_tex;
 542
 543         /**
 544          * Remember which program register a given hardware constant
 545          * belongs to.
 546          */
 547         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 548         int const_nr;
 549
 550         int max_temp_idx;
 551 };
 552
 553 /**
 554  * Store everything about a fragment program that is needed
 555  * to render with that program.
 556  */
 557 struct r300_fragment_program {
 558         struct gl_fragment_program mesa_program;
 559
 560         GLboolean translated;
 561         GLboolean error;
 562
 563         struct r300_fragment_program_external_state state;
 564         struct r300_fragment_program_code code;
 565
 566         GLboolean WritesDepth;
 567         GLuint optimization;
 568 };
 569
 570 struct r500_pfs_compile_state;
 571
 572 struct r500_fragment_program_external_state {
 573         struct {
 574                 /**
 575                  * If the sampler is used as a shadow sampler,
 576                  * this field is:
 577                  *  0 - GL_LUMINANCE
 578                  *  1 - GL_INTENSITY
 579                  *  2 - GL_ALPHA
 580                  * depending on the depth texture mode.
 581                  */
 582                 GLuint depth_texture_mode : 2;
 583
 584                 /**
 585                  * If the sampler is used as a shadow sampler,
 586                  * this field is (texture_compare_func - GL_NEVER).
 587                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 588                  *
 589                  * Otherwise, this field is 0.
 590                  */
 591                 GLuint texture_compare_func : 3;
 592         } unit[16];
 593 };
 594
 595 struct r500_fragment_program_code {
 596         struct {
 597                 GLuint inst0;
 598                 GLuint inst1;
 599                 GLuint inst2;
 600                 GLuint inst3;
 601                 GLuint inst4;
 602                 GLuint inst5;
 603         } inst[512];
 604
 605         int inst_offset;
 606         int inst_end;
 607
 608         /**
 609          * Remember which program register a given hardware constant
 610          * belongs to.
 611          */
 612         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 613         int const_nr;
 614
 615         int max_temp_idx;
 616 };
 617
 618 struct r500_fragment_program {
 619         struct gl_fragment_program mesa_program;
 620
 621         GLcontext *ctx;
 622         GLboolean translated;
 623         GLboolean error;
 624
 625         struct r500_fragment_program_external_state state;
 626         struct r500_fragment_program_code code;
 627
 628         GLboolean writes_depth;
 629
 630         GLuint optimization;
 631 };
 632
 633 #define R300_MAX_AOS_ARRAYS             16
 634
 635 #define REG_COORDS      0
 636 #define REG_COLOR0      1
 637 #define REG_TEX0        2
 638
 639 struct r300_state {
 640         struct r300_texture_state texture;
 641         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 642         struct r300_vertex_shader_state vertex_shader;
 643         struct radeon_aos aos[R300_MAX_AOS_ARRAYS];
 644         int aos_count;
 645
 646         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 647         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 648
 649         DECLARE_RENDERINPUTS(render_inputs_bitset);     /* actual render inputs that R300 was configured for.
 650                                                            They are the same as tnl->render_inputs for fixed pipeline */
 651
 652 };
 653
 654 #define R300_FALLBACK_NONE 0
 655 #define R300_FALLBACK_TCL 1
 656 #define R300_FALLBACK_RAST 2
 657
 658 /* r300_swtcl.c
 659  */
 660 struct r300_swtcl_info {
 661   /*
 662     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 663     */
 664    GLuint coloroffset;
 665
 666    /**
 667     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 668     */
 669    GLuint specoffset;
 670 };
 671
 672
 673 /**
 674  * \brief R300 context structure.
 675  */
 676 struct r300_context {
 677         struct radeon_context radeon;   /* parent class, must be first */
 678
 679         struct r300_hw_state hw;
 680
 681         struct r300_state state;
 682         struct gl_vertex_program *curr_vp;
 683         struct r300_vertex_program *selected_vp;
 684
 685         /* Vertex buffers
 686          */
 687         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 688         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 689
 690         GLboolean disable_lowimpact_fallback;
 691
 692         DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
 693         struct r300_swtcl_info swtcl;
 694 };
 695
 696 struct r300_buffer_object {
 697         struct gl_buffer_object mesa_obj;
 698         int id;
 699 };
 700
 701 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 702
 703 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 704 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 705                                    __DRIcontextPrivate * driContextPriv,
 706                                    void *sharedContextPrivate);
 707
 708 extern void r300SelectVertexShader(r300ContextPtr r300);
 709 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 710 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 711                                       struct r300_vertex_program_cont *vp,
 712                                       float *dst);
 713
 714 #define RADEON_D_CAPTURE 0
 715 #define RADEON_D_PLAYBACK 1
 716 #define RADEON_D_PLAYBACK_RAW 2
 717 #define RADEON_D_T 3
 718
 719 #define r300PackFloat32 radeonPackFloat32
 720 #define r300PackFloat24 radeonPackFloat24
 721
 722 #endif                          /* __R300_CONTEXT_H__ */