src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "radeon_common.h"
  44
  45 #include "main/mtypes.h"
  46 #include "shader/prog_instruction.h"
  47
  48 struct r300_context;
  49 typedef struct r300_context r300ContextRec;
  50 typedef struct r300_context *r300ContextPtr;
  51
  52
  53 /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  54    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  55    with other compilers ... GLUE!
  56 */
  57 #define WARN_ONCE(a, ...)       { \
  58         static int warn##__LINE__=1; \
  59         if(warn##__LINE__){ \
  60                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  61                 fprintf(stderr, "File %s function %s line %d\n", \
  62                         __FILE__, __FUNCTION__, __LINE__); \
  63                 fprintf(stderr,  a, ## __VA_ARGS__);\
  64                 fprintf(stderr, "***************************************************************************\n"); \
  65                 warn##__LINE__=0;\
  66                 } \
  67         }
  68
  69 #include "r300_vertprog.h"
  70
  71
  72 /* The blit width for texture uploads
  73  */
  74 #define R300_BLIT_WIDTH_BYTES 1024
  75 #define R300_MAX_TEXTURE_UNITS 8
  76
  77
  78
  79 #define R300_VPT_CMD_0          0
  80 #define R300_VPT_XSCALE         1
  81 #define R300_VPT_XOFFSET        2
  82 #define R300_VPT_YSCALE         3
  83 #define R300_VPT_YOFFSET        4
  84 #define R300_VPT_ZSCALE         5
  85 #define R300_VPT_ZOFFSET        6
  86 #define R300_VPT_CMDSIZE        7
  87
  88 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
  89 #define R300_VIR_CNTL_0         1
  90 #define R300_VIR_CNTL_1         2
  91 #define R300_VIR_CNTL_2         3
  92 #define R300_VIR_CNTL_3         4
  93 #define R300_VIR_CNTL_4         5
  94 #define R300_VIR_CNTL_5         6
  95 #define R300_VIR_CNTL_6         7
  96 #define R300_VIR_CNTL_7         8
  97 #define R300_VIR_CMDSIZE        9
  98
  99 #define R300_VIC_CMD_0          0
 100 #define R300_VIC_CNTL_0         1
 101 #define R300_VIC_CNTL_1         2
 102 #define R300_VIC_CMDSIZE        3
 103
 104 #define R300_VOF_CMD_0          0
 105 #define R300_VOF_CNTL_0         1
 106 #define R300_VOF_CNTL_1         2
 107 #define R300_VOF_CMDSIZE        3
 108
 109 #define R300_PVS_CMD_0          0
 110 #define R300_PVS_CNTL_1         1
 111 #define R300_PVS_CNTL_2         2
 112 #define R300_PVS_CNTL_3         3
 113 #define R300_PVS_CMDSIZE        4
 114
 115 #define R300_GB_MISC_CMD_0              0
 116 #define R300_GB_MISC_MSPOS_0            1
 117 #define R300_GB_MISC_MSPOS_1            2
 118 #define R300_GB_MISC_TILE_CONFIG        3
 119 #define R300_GB_MISC_CMDSIZE            4
 120 #define R300_GB_MISC2_CMD_0                 0
 121 #define R300_GB_MISC2_SELECT            1
 122 #define R300_GB_MISC2_AA_CONFIG         2
 123 #define R300_GB_MISC2_CMDSIZE           3
 124
 125 #define R300_TXE_CMD_0          0
 126 #define R300_TXE_ENABLE         1
 127 #define R300_TXE_CMDSIZE        2
 128
 129 #define R300_PS_CMD_0           0
 130 #define R300_PS_POINTSIZE       1
 131 #define R300_PS_CMDSIZE         2
 132
 133 #define R300_ZBS_CMD_0          0
 134 #define R300_ZBS_T_FACTOR       1
 135 #define R300_ZBS_T_CONSTANT     2
 136 #define R300_ZBS_W_FACTOR       3
 137 #define R300_ZBS_W_CONSTANT     4
 138 #define R300_ZBS_CMDSIZE        5
 139
 140 #define R300_CUL_CMD_0          0
 141 #define R300_CUL_CULL           1
 142 #define R300_CUL_CMDSIZE        2
 143
 144 #define R300_RC_CMD_0           0
 145 #define R300_RC_CNTL_0          1
 146 #define R300_RC_CNTL_1          2
 147 #define R300_RC_CMDSIZE         3
 148
 149 #define R300_RI_CMD_0           0
 150 #define R300_RI_INTERP_0        1
 151 #define R300_RI_INTERP_1        2
 152 #define R300_RI_INTERP_2        3
 153 #define R300_RI_INTERP_3        4
 154 #define R300_RI_INTERP_4        5
 155 #define R300_RI_INTERP_5        6
 156 #define R300_RI_INTERP_6        7
 157 #define R300_RI_INTERP_7        8
 158 #define R300_RI_CMDSIZE         9
 159
 160 #define R500_RI_CMDSIZE        17
 161
 162 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 163 #define R300_RR_INST_0          1
 164 #define R300_RR_INST_1          2
 165 #define R300_RR_INST_2          3
 166 #define R300_RR_INST_3          4
 167 #define R300_RR_INST_4          5
 168 #define R300_RR_INST_5          6
 169 #define R300_RR_INST_6          7
 170 #define R300_RR_INST_7          8
 171 #define R300_RR_CMDSIZE         9
 172
 173 #define R300_FP_CMD_0           0
 174 #define R300_FP_CNTL0           1
 175 #define R300_FP_CNTL1           2
 176 #define R300_FP_CNTL2           3
 177 #define R300_FP_CMD_1           4
 178 #define R300_FP_NODE0           5
 179 #define R300_FP_NODE1           6
 180 #define R300_FP_NODE2           7
 181 #define R300_FP_NODE3           8
 182 #define R300_FP_CMDSIZE         9
 183
 184 #define R500_FP_CMD_0           0
 185 #define R500_FP_CNTL            1
 186 #define R500_FP_PIXSIZE         2
 187 #define R500_FP_CMD_1           3
 188 #define R500_FP_CODE_ADDR       4
 189 #define R500_FP_CODE_RANGE      5
 190 #define R500_FP_CODE_OFFSET     6
 191 #define R500_FP_CMD_2           7
 192 #define R500_FP_FC_CNTL         8
 193 #define R500_FP_CMDSIZE         9
 194
 195 #define R300_FPT_CMD_0          0
 196 #define R300_FPT_INSTR_0        1
 197 #define R300_FPT_CMDSIZE        65
 198
 199 #define R300_FPI_CMD_0          0
 200 #define R300_FPI_INSTR_0        1
 201 #define R300_FPI_CMDSIZE        65
 202 /* R500 has space for 512 instructions - 6 dwords per instruction */
 203 #define R500_FPI_CMDSIZE        (512*6+1)
 204
 205 #define R300_FPP_CMD_0          0
 206 #define R300_FPP_PARAM_0        1
 207 #define R300_FPP_CMDSIZE        (32*4+1)
 208 /* R500 has spcae for 256 constants - 4 dwords per constant */
 209 #define R500_FPP_CMDSIZE        (256*4+1)
 210
 211 #define R300_FOGS_CMD_0         0
 212 #define R300_FOGS_STATE         1
 213 #define R300_FOGS_CMDSIZE       2
 214
 215 #define R300_FOGC_CMD_0         0
 216 #define R300_FOGC_R             1
 217 #define R300_FOGC_G             2
 218 #define R300_FOGC_B             3
 219 #define R300_FOGC_CMDSIZE       4
 220
 221 #define R300_FOGP_CMD_0         0
 222 #define R300_FOGP_SCALE         1
 223 #define R300_FOGP_START         2
 224 #define R300_FOGP_CMDSIZE       3
 225
 226 #define R300_AT_CMD_0           0
 227 #define R300_AT_ALPHA_TEST      1
 228 #define R300_AT_UNKNOWN         2
 229 #define R300_AT_CMDSIZE         3
 230
 231 #define R300_BLD_CMD_0          0
 232 #define R300_BLD_CBLEND         1
 233 #define R300_BLD_ABLEND         2
 234 #define R300_BLD_CMDSIZE        3
 235
 236 #define R300_CMK_CMD_0          0
 237 #define R300_CMK_COLORMASK      1
 238 #define R300_CMK_CMDSIZE        2
 239
 240 #define R300_CB_CMD_0           0
 241 #define R300_CB_OFFSET          1
 242 #define R300_CB_CMD_1           2
 243 #define R300_CB_PITCH           3
 244 #define R300_CB_CMDSIZE         4
 245
 246 #define R300_ZS_CMD_0           0
 247 #define R300_ZS_CNTL_0          1
 248 #define R300_ZS_CNTL_1          2
 249 #define R300_ZS_CNTL_2          3
 250 #define R300_ZS_CMDSIZE         4
 251
 252 #define R300_ZB_CMD_0           0
 253 #define R300_ZB_OFFSET          1
 254 #define R300_ZB_PITCH           2
 255 #define R300_ZB_CMDSIZE         3
 256
 257 #define R300_VAP_CNTL_FLUSH     0
 258 #define R300_VAP_CNTL_FLUSH_1   1
 259 #define R300_VAP_CNTL_CMD       2
 260 #define R300_VAP_CNTL_INSTR     3
 261 #define R300_VAP_CNTL_SIZE      4
 262
 263 #define R300_VPI_CMD_0          0
 264 #define R300_VPI_INSTR_0        1
 265 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 266
 267 #define R300_VPP_CMD_0          0
 268 #define R300_VPP_PARAM_0        1
 269 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 270
 271 #define R300_VPUCP_CMD_0                0
 272 #define R300_VPUCP_X            1
 273 #define R300_VPUCP_Y            2
 274 #define R300_VPUCP_Z            3
 275 #define R300_VPUCP_W            4
 276 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 277
 278 #define R300_VPS_CMD_0          0
 279 #define R300_VPS_ZERO_0         1
 280 #define R300_VPS_ZERO_1         2
 281 #define R300_VPS_POINTSIZE      3
 282 #define R300_VPS_ZERO_3         4
 283 #define R300_VPS_CMDSIZE        5
 284
 285         /* the layout is common for all fields inside tex */
 286 #define R300_TEX_CMD_0          0
 287 #define R300_TEX_VALUE_0        1
 288 /* We don't really use this, instead specify mtu+1 dynamically
 289 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 290 */
 291
 292 /**
 293  * Cache for hardware register state.
 294  */
 295 struct r300_hw_state {
 296         struct radeon_state_atom vpt;   /* viewport (1D98) */
 297         struct radeon_state_atom vap_cntl;
 298         struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
 299         struct radeon_state_atom vof;   /* VAP output format register 0x2090 */
 300         struct radeon_state_atom vte;   /* (20B0) */
 301         struct radeon_state_atom vap_vf_max_vtx_indx;   /* Maximum Vertex Indx Clamp (2134) */
 302         struct radeon_state_atom vap_cntl_status;
 303         struct radeon_state_atom vir[2];        /* vap input route (2150/21E0) */
 304         struct radeon_state_atom vic;   /* vap input control (2180) */
 305         struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 306         struct radeon_state_atom vap_clip_cntl;
 307         struct radeon_state_atom vap_clip;
 308         struct radeon_state_atom vap_pvs_vtx_timeout_reg;       /* Vertex timeout register (2288) */
 309         struct radeon_state_atom pvs;   /* pvs_cntl (22D0) */
 310         struct radeon_state_atom gb_enable;     /* (4008) */
 311         struct radeon_state_atom gb_misc;       /* Multisampling position shifts ? (4010) */
 312         struct radeon_state_atom gb_misc2;      /* Multisampling position shifts ? (4010) */
 313         struct radeon_state_atom ga_point_s0;   /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 314         struct radeon_state_atom ga_triangle_stipple;   /* (4214) */
 315         struct radeon_state_atom ps;    /* pointsize (421C) */
 316         struct radeon_state_atom ga_point_minmax;       /* (4230) */
 317         struct radeon_state_atom lcntl; /* line control */
 318         struct radeon_state_atom ga_line_stipple;       /* (4260) */
 319         struct radeon_state_atom shade;
 320         struct radeon_state_atom shade2;
 321         struct radeon_state_atom polygon_mode;
 322         struct radeon_state_atom fogp;  /* fog parameters (4294) */
 323         struct radeon_state_atom ga_soft_reset; /* (429C) */
 324         struct radeon_state_atom zbias_cntl;
 325         struct radeon_state_atom zbs;   /* zbias (42A4) */
 326         struct radeon_state_atom occlusion_cntl;
 327         struct radeon_state_atom cul;   /* cull cntl (42B8) */
 328         struct radeon_state_atom su_depth_scale;        /* (42C0) */
 329         struct radeon_state_atom rc;    /* rs control (4300) */
 330         struct radeon_state_atom ri;    /* rs interpolators (4310) */
 331         struct radeon_state_atom rr;    /* rs route (4330) */
 332         struct radeon_state_atom sc_hyperz;     /* (43A4) */
 333         struct radeon_state_atom sc_screendoor; /* (43E8) */
 334         struct radeon_state_atom fp;    /* fragment program cntl + nodes (4600) */
 335         struct radeon_state_atom fpt;   /* texi - (4620) */
 336         struct radeon_state_atom us_out_fmt;    /* (46A4) */
 337         struct radeon_state_atom r500fp;        /* r500 fp instructions */
 338         struct radeon_state_atom r500fp_const;  /* r500 fp constants */
 339         struct radeon_state_atom fpi[4];        /* fp instructions (46C0/47C0/48C0/49C0) */
 340         struct radeon_state_atom fogs;  /* fog state (4BC0) */
 341         struct radeon_state_atom fogc;  /* fog color (4BC8) */
 342         struct radeon_state_atom at;    /* alpha test (4BD4) */
 343         struct radeon_state_atom fg_depth_src;  /* (4BD8) */
 344         struct radeon_state_atom fpp;   /* 0x4C00 and following */
 345         struct radeon_state_atom rb3d_cctl;     /* (4E00) */
 346         struct radeon_state_atom bld;   /* blending (4E04) */
 347         struct radeon_state_atom cmk;   /* colormask (4E0C) */
 348         struct radeon_state_atom blend_color;   /* constant blend color */
 349         struct radeon_state_atom rop;   /* ropcntl */
 350         struct radeon_state_atom cb;    /* colorbuffer (4E28) */
 351         struct radeon_state_atom rb3d_dither_ctl;       /* (4E50) */
 352         struct radeon_state_atom rb3d_aaresolve_ctl;    /* (4E88) */
 353         struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold;  /* (4E88) I saw it only written on RV350 hardware..  */
 354         struct radeon_state_atom zs;    /* zstencil control (4F00) */
 355         struct radeon_state_atom zstencil_format;
 356         struct radeon_state_atom zb;    /* z buffer (4F20) */
 357         struct radeon_state_atom zb_depthclearvalue;    /* (4F28) */
 358         struct radeon_state_atom zb_zmask;      /* (4F30) */
 359         struct radeon_state_atom zb_hiz_offset; /* (4F44) */
 360         struct radeon_state_atom zb_hiz_pitch;  /* (4F54) */
 361
 362         struct radeon_state_atom vpi;   /* vp instructions */
 363         struct radeon_state_atom vpp;   /* vp parameters */
 364         struct radeon_state_atom vps;   /* vertex point size (?) */
 365         struct radeon_state_atom vpucp[6];      /* vp user clip plane - 6 */
 366         /* 8 texture units */
 367         /* the state is grouped by function and not by
 368            texture unit. This makes single unit updates
 369            really awkward - we are much better off
 370            updating the whole thing at once */
 371         struct {
 372                 struct radeon_state_atom filter;
 373                 struct radeon_state_atom filter_1;
 374                 struct radeon_state_atom size;
 375                 struct radeon_state_atom format;
 376                 struct radeon_state_atom pitch;
 377                 struct radeon_state_atom offset;
 378                 struct radeon_state_atom chroma_key;
 379                 struct radeon_state_atom border_color;
 380         } tex;
 381         struct radeon_state_atom txe;   /* tex enable (4104) */
 382
 383         radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
 384 };
 385
 386 /**
 387  * State cache
 388  */
 389
 390 /* Vertex shader state */
 391
 392 /* Perhaps more if we store programs in vmem? */
 393 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 394 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 395
 396 /* Can be tested with colormat currently. */
 397 #define VSF_MAX_FRAGMENT_TEMPS (14)
 398
 399 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 400 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 401
 402 struct r300_vertex_shader_fragment {
 403         int length;
 404         union {
 405                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 406                 float f[VSF_MAX_FRAGMENT_LENGTH];
 407                 GLuint i[VSF_MAX_FRAGMENT_LENGTH];
 408         } body;
 409 };
 410
 411 struct r300_vertex_shader_state {
 412         struct r300_vertex_shader_fragment program;
 413 };
 414
 415 #define COLOR_IS_RGBA
 416 #define TAG(x) r300##x
 417 #include "tnl_dd/t_dd_vertex.h"
 418 #undef TAG
 419
 420 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 421
 422 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 423  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 424  */
 425
 426 struct r300_vertex_program_key {
 427         GLuint InputsRead;
 428         GLuint OutputsWritten;
 429         GLuint OutputsAdded;
 430 };
 431
 432 struct r300_vertex_program {
 433         struct r300_vertex_program *next;
 434         struct r300_vertex_program_key key;
 435         int translated;
 436
 437         struct r300_vertex_shader_fragment program;
 438
 439         int pos_end;
 440         int num_temporaries;    /* Number of temp vars used by program */
 441         int wpos_idx;
 442         int inputs[VERT_ATTRIB_MAX];
 443         int outputs[VERT_RESULT_MAX];
 444         int native;
 445         int ref_count;
 446         int use_ref_count;
 447 };
 448
 449 struct r300_vertex_program_cont {
 450         struct gl_vertex_program mesa_program;  /* Must be first */
 451         struct r300_vertex_shader_fragment params;
 452         struct r300_vertex_program *progs;
 453 };
 454
 455 #define R300_PFS_MAX_ALU_INST   64
 456 #define R300_PFS_MAX_TEX_INST   32
 457 #define R300_PFS_MAX_TEX_INDIRECT 4
 458 #define R300_PFS_NUM_TEMP_REGS  32
 459 #define R300_PFS_NUM_CONST_REGS 32
 460
 461 #define R500_PFS_MAX_INST 512
 462 #define R500_PFS_NUM_TEMP_REGS 128
 463 #define R500_PFS_NUM_CONST_REGS 256
 464
 465 struct r300_pfs_compile_state;
 466 struct r500_pfs_compile_state;
 467
 468 /**
 469  * Stores state that influences the compilation of a fragment program.
 470  */
 471 struct r300_fragment_program_external_state {
 472         struct {
 473                 /**
 474                  * If the sampler is used as a shadow sampler,
 475                  * this field is:
 476                  *  0 - GL_LUMINANCE
 477                  *  1 - GL_INTENSITY
 478                  *  2 - GL_ALPHA
 479                  * depending on the depth texture mode.
 480                  */
 481                 GLuint depth_texture_mode : 2;
 482
 483                 /**
 484                  * If the sampler is used as a shadow sampler,
 485                  * this field is (texture_compare_func - GL_NEVER).
 486                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 487                  *
 488                  * Otherwise, this field is 0.
 489                  */
 490                 GLuint texture_compare_func : 3;
 491         } unit[16];
 492 };
 493
 494
 495 struct r300_fragment_program_node {
 496         int tex_offset; /**< first tex instruction */
 497         int tex_end; /**< last tex instruction, relative to tex_offset */
 498         int alu_offset; /**< first ALU instruction */
 499         int alu_end; /**< last ALU instruction, relative to alu_offset */
 500         int flags;
 501 };
 502
 503 /**
 504  * Stores an R300 fragment program in its compiled-to-hardware form.
 505  */
 506 struct r300_fragment_program_code {
 507         struct {
 508                 int length; /**< total # of texture instructions used */
 509                 GLuint inst[R300_PFS_MAX_TEX_INST];
 510         } tex;
 511
 512         struct {
 513                 int length; /**< total # of ALU instructions used */
 514                 struct {
 515                         GLuint inst0;
 516                         GLuint inst1;
 517                         GLuint inst2;
 518                         GLuint inst3;
 519                 } inst[R300_PFS_MAX_ALU_INST];
 520         } alu;
 521
 522         struct r300_fragment_program_node node[4];
 523         int cur_node;
 524         int first_node_has_tex;
 525
 526         /**
 527          * Remember which program register a given hardware constant
 528          * belongs to.
 529          */
 530         struct prog_src_register constant[R300_PFS_NUM_CONST_REGS];
 531         int const_nr;
 532
 533         int max_temp_idx;
 534 };
 535
 536
 537 struct r500_fragment_program_code {
 538         struct {
 539                 GLuint inst0;
 540                 GLuint inst1;
 541                 GLuint inst2;
 542                 GLuint inst3;
 543                 GLuint inst4;
 544                 GLuint inst5;
 545         } inst[R500_PFS_MAX_INST];
 546
 547         int inst_offset;
 548         int inst_end;
 549
 550         /**
 551          * Remember which program register a given hardware constant
 552          * belongs to.
 553          */
 554         struct prog_src_register constant[R500_PFS_NUM_CONST_REGS];
 555         int const_nr;
 556
 557         int max_temp_idx;
 558 };
 559
 560 /**
 561 * Store everything about a fragment program that is needed
 562 * to render with that program.
 563 */
 564 struct r300_fragment_program {
 565         struct gl_fragment_program Base;
 566
 567         GLboolean translated;
 568         GLboolean error;
 569
 570         struct r300_fragment_program_external_state state;
 571         union rX00_fragment_program_code {
 572                 struct r300_fragment_program_code r300;
 573                 struct r500_fragment_program_code r500;
 574         } code;
 575
 576         GLboolean writes_depth;
 577         GLuint optimization;
 578 };
 579
 580 struct r300_fragment_program_compiler {
 581         r300ContextPtr r300;
 582         struct r300_fragment_program *fp;
 583         union rX00_fragment_program_code *code;
 584         struct gl_program *program;
 585 };
 586
 587 #define R300_MAX_AOS_ARRAYS             16
 588
 589
 590 #define R300_FALLBACK_NONE 0
 591 #define R300_FALLBACK_TCL 1
 592 #define R300_FALLBACK_RAST 2
 593
 594 /* r300_swtcl.c
 595  */
 596 struct r300_swtcl_info {
 597   /*
 598     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 599     */
 600    GLuint coloroffset;
 601
 602    /**
 603     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 604     */
 605    GLuint specoffset;
 606
 607    struct vertex_attribute{
 608        GLuint attr;
 609        GLubyte format;
 610        GLubyte dst_loc;
 611        GLuint swizzle;
 612        GLubyte write_mask;
 613    } vert_attrs[VERT_ATTRIB_MAX];
 614
 615    GLubyte vertex_attr_count;
 616
 617    int sw_tcl_inputs[VERT_ATTRIB_MAX];
 618 };
 619
 620 struct r300_vtable {
 621         void (* SetupRSUnit)(GLcontext *ctx);
 622         void (* SetupFragmentShaderTextures)(GLcontext *ctx, int *tmu_mappings);
 623         GLboolean (* FragmentProgramEmit)(struct r300_fragment_program_compiler *compiler);
 624         void (* FragmentProgramDump)(union rX00_fragment_program_code *code);
 625         GLboolean (* SetupPixelShader)(GLcontext *ctx);
 626 };
 627
 628
 629 /**
 630  * \brief R300 context structure.
 631  */
 632 struct r300_context {
 633         struct radeon_context radeon;   /* parent class, must be first */
 634
 635         struct r300_vtable vtbl;
 636
 637         struct r300_hw_state hw;
 638
 639         struct r300_vertex_shader_state vertex_shader;
 640         struct r300_vertex_program *selected_vp;
 641
 642         /* Vertex buffers
 643          */
 644         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 645         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 646
 647         GLboolean disable_lowimpact_fallback;
 648
 649         struct r300_options {
 650                 uint32_t conformance_mode:1;
 651                 uint32_t hw_tcl_enabled:1;
 652                 uint32_t s3tc_force_enabled:1;
 653                 uint32_t s3tc_force_disabled:1;
 654                 uint32_t stencil_two_side_disabled:1;
 655         } options;
 656
 657         struct r300_swtcl_info swtcl;
 658         GLboolean vap_flush_needed;
 659
 660         DECLARE_RENDERINPUTS(render_inputs_bitset);
 661 };
 662
 663 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 664
 665 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 666 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 667                                    __DRIcontextPrivate * driContextPriv,
 668                                    void *sharedContextPrivate);
 669
 670 extern void r300SelectVertexShader(r300ContextPtr r300);
 671 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 672 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 673                                       struct r300_vertex_program_cont *vp,
 674                                       float *dst);
 675
 676 extern void r300InitShaderFunctions(r300ContextPtr r300);
 677
 678 #define r300PackFloat32 radeonPackFloat32
 679 #define r300PackFloat24 radeonPackFloat24
 680
 681 #endif                          /* __R300_CONTEXT_H__ */