src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 struct r300_context;
  51 typedef struct r300_context r300ContextRec;
  52 typedef struct r300_context *r300ContextPtr;
  53
  54 #include "radeon_lock.h"
  55 #include "mm.h"
  56
  57 typedef GLuint uint32_t;
  58 typedef GLubyte uint8_t;
  59
  60
  61 static __inline__ uint32_t r300PackFloat32(float fl)
  62 {
  63         union { float fl; uint32_t u; } u;
  64
  65         u.fl = fl;
  66         return u.u;
  67 }
  68
  69
  70 /************ DMA BUFFERS **************/
  71
  72 /* Need refcounting on dma buffers:
  73  */
  74 struct r300_dma_buffer {
  75         int refcount;           /* the number of retained regions in buf */
  76         drmBufPtr buf;
  77 };
  78
  79 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
  80                         (rvb)->address - rmesa->dma.buf0_address +      \
  81                         (rvb)->start)
  82
  83 /* A retained region, eg vertices for indexed vertices.
  84  */
  85 struct r300_dma_region {
  86         struct r300_dma_buffer *buf;
  87         char *address;          /* == buf->address */
  88         int start, end, ptr;    /* offsets from start of buf */
  89         int aos_start;
  90         int aos_stride;
  91         int aos_size;
  92 };
  93
  94 struct r300_dma {
  95         /* Active dma region.  Allocations for vertices and retained
  96          * regions come from here.  Also used for emitting random vertices,
  97          * these may be flushed by calling flush_current();
  98          */
  99         struct r300_dma_region current;
 100
 101         void (*flush) (r300ContextPtr);
 102
 103         char *buf0_address;     /* start of buf[0], for index calcs */
 104         GLuint nr_released_bufs;        /* flush after so many buffers released */
 105 };
 106
 107        /* Texture related */
 108
 109 #define TEX_0   0x1
 110 #define TEX_1   0x2
 111 #define TEX_2   0x4
 112 #define TEX_3   0x8
 113 #define TEX_4   0x10
 114 #define TEX_5   0x20
 115 #define TEX_6   0x40
 116 #define TEX_7   0x80
 117 #define TEX_ALL 0xff
 118
 119 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 120
 121 /* Texture object in locally shared texture space.
 122  */
 123 struct r300_tex_obj {
 124         driTextureObject base;
 125
 126         GLuint bufAddr;         /* Offset to start of locally
 127                                    shared texture block */
 128
 129         GLuint dirty_state;     /* Flags (1 per texunit) for
 130                                    whether or not this texobj
 131                                    has dirty hardware state
 132                                    (pp_*) that needs to be
 133                                    brought into the
 134                                    texunit. */
 135
 136         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 137         /* Six, for the cube faces */
 138
 139
 140         /* hardware register values */
 141         /* Note that R200 has 8 registers per texture and R300 only 7 */
 142         GLuint filter;
 143         GLuint pitch; /* one of the unknown registers.. unknown 1 ?*/
 144         GLuint size;    /* npot only */
 145         GLuint format;
 146         GLuint offset;  /* Image location in texmem.
 147                                    All cube faces follow. */
 148         GLuint unknown4;
 149         GLuint unknown5;
 150         /* end hardware registers */
 151
 152         /* registers computed by r200 code - keep them here to
 153            compare against what is actually written.
 154
 155            to be removed later.. */
 156         GLuint pp_border_color;
 157         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 158         GLuint format_x;
 159
 160
 161         GLboolean border_fallback;
 162 };
 163
 164 struct r300_texture_env_state {
 165         r300TexObjPtr texobj;
 166         GLenum format;
 167         GLenum envMode;
 168 };
 169
 170 #define R300_MAX_TEXTURE_UNITS 6
 171
 172 struct r300_texture_state {
 173         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 174 };
 175
 176 /**
 177  * A block of hardware state.
 178  *
 179  * When check returns non-zero, the returned number of dwords must be
 180  * copied verbatim into the command buffer in order to update a state atom
 181  * when it is dirty.
 182  */
 183 struct r300_state_atom {
 184         struct r300_state_atom *next, *prev;
 185         const char* name;       /* for debug */
 186         int cmd_size;           /* maximum size in dwords */
 187         GLuint idx;             /* index in an array (e.g. textures) */
 188         uint32_t* cmd;
 189         GLboolean dirty;
 190
 191         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 192 };
 193
 194
 195 #define R300_VPT_CMD_0          0
 196 #define R300_VPT_XSCALE         1
 197 #define R300_VPT_XOFFSET        2
 198 #define R300_VPT_YSCALE         3
 199 #define R300_VPT_YOFFSET        4
 200 #define R300_VPT_ZSCALE         5
 201 #define R300_VPT_ZOFFSET        6
 202 #define R300_VPT_CMDSIZE        7
 203
 204 #define R300_OVF_CMD_0          0
 205 #define R300_OVF_FMT_0          1
 206 #define R300_OVF_FMT_1          2
 207 #define R300_OVF_CMDSIZE        3
 208
 209 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 210 #define R300_VIR_CNTL_0         1
 211 #define R300_VIR_CNTL_1         2
 212 #define R300_VIR_CNTL_2         3
 213 #define R300_VIR_CNTL_3         4
 214 #define R300_VIR_CNTL_4         5
 215 #define R300_VIR_CNTL_5         6
 216 #define R300_VIR_CNTL_6         7
 217 #define R300_VIR_CNTL_7         8
 218 #define R300_VIR_CMDSIZE        9
 219
 220 #define R300_VIC_CMD_0          0
 221 #define R300_VIC_CNTL_0         1
 222 #define R300_VIC_CNTL_1         2
 223 #define R300_VIC_CMDSIZE        3
 224
 225 #define R300_VOF_CMD_0          0
 226 #define R300_VOF_CNTL_0         1
 227 #define R300_VOF_CNTL_1         2
 228 #define R300_VOF_CMDSIZE        3
 229
 230
 231 #define R300_PVS_CMD_0          0
 232 #define R300_PVS_CNTL_1         1
 233 #define R300_PVS_CNTL_2         2
 234 #define R300_PVS_CNTL_3         3
 235 #define R300_PVS_CMDSIZE        4
 236
 237 #define R300_GB_MISC_CMD_0              0
 238 #define R300_GB_MISC_MSPOS_0            1
 239 #define R300_GB_MISC_MSPOS_1            2
 240 #define R300_GB_MISC_TILE_CONFIG        3
 241 #define R300_GB_MISC_SELECT             4
 242 #define R300_GB_MISC_AA_CONFIG          5
 243 #define R300_GB_MISC_CMDSIZE            6
 244
 245 #define R300_TXE_CMD_0          0
 246 #define R300_TXE_ENABLE         1
 247 #define R300_TXE_CMDSIZE        2
 248
 249 #define R300_PS_CMD_0           0
 250 #define R300_PS_POINTSIZE       1
 251 #define R300_PS_CMDSIZE         2
 252
 253 #define R300_CUL_CMD_0          0
 254 #define R300_CUL_CULL           1
 255 #define R300_CUL_CMDSIZE        2
 256
 257 #define R300_RC_CMD_0           0
 258 #define R300_RC_CNTL_0          1
 259 #define R300_RC_CNTL_1          2
 260 #define R300_RC_CMDSIZE         3
 261
 262 #define R300_RI_CMD_0           0
 263 #define R300_RI_INTERP_0        1
 264 #define R300_RI_INTERP_1        2
 265 #define R300_RI_INTERP_2        3
 266 #define R300_RI_INTERP_3        4
 267 #define R300_RI_INTERP_4        5
 268 #define R300_RI_INTERP_5        6
 269 #define R300_RI_INTERP_6        7
 270 #define R300_RI_INTERP_7        8
 271 #define R300_RI_CMDSIZE         9
 272
 273 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 274 #define R300_RR_ROUTE_0         1
 275 #define R300_RR_ROUTE_1         2
 276 #define R300_RR_ROUTE_2         3
 277 #define R300_RR_ROUTE_3         4
 278 #define R300_RR_ROUTE_4         5
 279 #define R300_RR_ROUTE_5         6
 280 #define R300_RR_ROUTE_6         7
 281 #define R300_RR_ROUTE_7         8
 282 #define R300_RR_CMDSIZE         9
 283
 284 #define R300_FP_CMD_0           0
 285 #define R300_FP_CNTL0           1
 286 #define R300_FP_CNTL1           2
 287 #define R300_FP_CNTL2           3
 288 #define R300_FP_CMD_1           4
 289 #define R300_FP_NODE0           5
 290 #define R300_FP_NODE1           6
 291 #define R300_FP_NODE2           7
 292 #define R300_FP_NODE3           8
 293 #define R300_FP_CMDSIZE         9
 294
 295 #define R300_FPI_CMD_0          0
 296 #define R300_FPI_INSTR_0        1
 297 #define R300_FPI_CMDSIZE        65
 298
 299 #define R300_AT_CMD_0           0
 300 #define R300_AT_ALPHA_TEST      1
 301 #define R300_AT_CMDSIZE         2
 302
 303 #define R300_BLD_CMD_0          0
 304 #define R300_BLD_CBLEND         1
 305 #define R300_BLD_ABLEND         2
 306 #define R300_BLD_CMDSIZE        3
 307
 308 #define R300_CMK_CMD_0          0
 309 #define R300_CMK_COLORMASK      1
 310 #define R300_CMK_CMDSIZE        2
 311
 312 #define R300_CB_CMD_0           0
 313 #define R300_CB_OFFSET          1
 314 #define R300_CB_CMD_1           2
 315 #define R300_CB_PITCH           3
 316 #define R300_CB_CMDSIZE         4
 317
 318 #define R300_ZC_CMD_0           0
 319 #define R300_ZC_CNTL_0          1
 320 #define R300_ZC_CNTL_1          2
 321 #define R300_ZC_CMDSIZE         3
 322
 323 #define R300_ZB_CMD_0           0
 324 #define R300_ZB_OFFSET          1
 325 #define R300_ZB_PITCH           2
 326 #define R300_ZB_CMDSIZE         3
 327
 328 #define R300_VPI_CMD_0          0
 329 #define R300_VPI_INSTR_0        1
 330 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 331
 332 #define R300_VPP_CMD_0          0
 333 #define R300_VPP_PARAM_0        1
 334 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 335
 336 #define R300_VPS_CMD_0          0
 337 #define R300_VPS_ZERO_0         1
 338 #define R300_VPS_ZERO_1         2
 339 #define R300_VPS_POINTSIZE      3
 340 #define R300_VPS_ZERO_3         4
 341 #define R300_VPS_CMDSIZE        5
 342
 343         /* the layout is common for all fields inside tex */
 344 #define R300_TEX_CMD_0          0
 345 #define R300_TEX_VALUE_0        1
 346 /* We don't really use this, instead specify mtu+1 dynamically
 347 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 348 */
 349
 350 /**
 351  * Cache for hardware register state.
 352  */
 353 struct r300_hw_state {
 354         struct r300_state_atom atomlist;
 355
 356         GLboolean       is_dirty;
 357         GLboolean       all_dirty;
 358         int             max_state_size; /* in dwords */
 359
 360         struct r300_state_atom vpt;     /* viewport (1D98) */
 361         struct r300_state_atom unk2080; /* (2080) */
 362         struct r300_state_atom ovf;     /* output vertex format (2090) */
 363         struct r300_state_atom vte;     /* (20B0) */
 364         struct r300_state_atom unk2134; /* (2134) */
 365         struct r300_state_atom unk2140; /* (2140) */
 366         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 367         struct r300_state_atom vic;     /* vap input control (2180) */
 368         struct r300_state_atom unk21DC; /* (21DC) */
 369         struct r300_state_atom unk221C; /* (221C) */
 370         struct r300_state_atom unk2220; /* (2220) */
 371         struct r300_state_atom unk2288; /* (2288) */
 372         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 373         struct r300_state_atom vof;     /* VAP output format register 0x4000 */
 374         struct r300_state_atom gb_enable; /* (4008) */
 375         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 376         struct r300_state_atom txe;     /* tex enable (4104) */
 377         struct r300_state_atom unk4200; /* (4200) */
 378         struct r300_state_atom unk4214; /* (4214) */
 379         struct r300_state_atom ps;      /* pointsize (421C) */
 380         struct r300_state_atom unk4230; /* (4230) */
 381         struct r300_state_atom unk4260; /* (4260) */
 382         struct r300_state_atom unk4274; /* (4274) */
 383         struct r300_state_atom unk4288; /* (4288) */
 384         struct r300_state_atom unk42A0; /* (42A0) */
 385         struct r300_state_atom unk42B4; /* (42B4) */
 386         struct r300_state_atom cul;     /* cull cntl (42B8) */
 387         struct r300_state_atom unk42C0; /* (42C0) */
 388         struct r300_state_atom rc;      /* rs control (4300) */
 389         struct r300_state_atom ri;      /* rs interpolators (4310) */
 390         struct r300_state_atom rr;      /* rs route (4330) */
 391         struct r300_state_atom unk43A4; /* (43A4) */
 392         struct r300_state_atom unk43E8; /* (43E8) */
 393         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 394         struct r300_state_atom unk46A4; /* (46A4) */
 395         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 396         struct r300_state_atom unk4BC0; /* (4BC0) */
 397         struct r300_state_atom unk4BC8; /* (4BC8) */
 398         struct r300_state_atom at;      /* alpha test (4BD4) */
 399         struct r300_state_atom unk4BD8; /* (4BD8) */
 400         struct r300_state_atom unk4E00; /* (4E00) */
 401         struct r300_state_atom bld;     /* blending (4E04) */
 402         struct r300_state_atom cmk;     /* colormask (4E0C) */
 403         struct r300_state_atom unk4E10; /* (4E10) */
 404         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 405         struct r300_state_atom unk4E50; /* (4E50) */
 406         struct r300_state_atom unk4E88; /* (4E88) */
 407         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 408         struct r300_state_atom zc;      /* z control (4F00) */
 409         struct r300_state_atom unk4F08; /* (4F08) */
 410         struct r300_state_atom unk4F10; /* (4F10) */
 411         struct r300_state_atom zb;      /* z buffer (4F20) */
 412         struct r300_state_atom unk4F28; /* (4F28) */
 413         struct r300_state_atom unk4F30; /* (4F30) */
 414         struct r300_state_atom unk4F44; /* (4F44) */
 415         struct r300_state_atom unk4F54; /* (4F54) */
 416
 417         struct r300_state_atom vpi;     /* vp instructions */
 418         struct r300_state_atom vpp;     /* vp parameters */
 419         struct r300_state_atom vps;     /* vertex point size (?) */
 420
 421                 /* 8 texture units */
 422                 /* the state is grouped by function and not by
 423                    texture unit. This makes single unit updates
 424                    really awkward - we are much better off
 425                    updating the whole thing at once */
 426         struct {
 427                 struct r300_state_atom filter;
 428                 struct r300_state_atom unknown1;
 429                 struct r300_state_atom size;
 430                 struct r300_state_atom format;
 431                 struct r300_state_atom offset;
 432                 struct r300_state_atom unknown4;
 433                 struct r300_state_atom unknown5;
 434                 } tex;
 435 };
 436
 437
 438 /**
 439  * This structure holds the command buffer while it is being constructed.
 440  *
 441  * The first batch of commands in the buffer is always the state that needs
 442  * to be re-emitted when the context is lost. This batch can be skipped
 443  * otherwise.
 444  */
 445 struct r300_cmdbuf {
 446         int             size;           /* DWORDs allocated for buffer */
 447         uint32_t*       cmd_buf;
 448         int             count_used;     /* DWORDs filled so far */
 449         int             count_reemit;   /* size of re-emission batch */
 450 };
 451
 452
 453 /**
 454  * State cache
 455  */
 456
 457 struct r300_depthbuffer_state {
 458         GLfloat scale;
 459 };
 460
 461 struct r300_state {
 462         struct r300_depthbuffer_state depth;
 463         struct r300_texture_state texture;
 464 };
 465
 466
 467 /**
 468  * R300 context structure.
 469  */
 470 struct r300_context {
 471         struct radeon_context radeon; /* parent class, must be first */
 472
 473         struct r300_hw_state hw;
 474         struct r300_cmdbuf cmdbuf;
 475         struct r300_state state;
 476
 477         /* Vertex buffers */
 478         int elt_count;  /* size of the buffer for vertices */
 479         int attrib_count; /* size of the buffer for vertex attributes.. Somehow it can be different ? */
 480
 481
 482         /* Vertex buffers
 483          */
 484         #if 0 /* we'll need it later, but not now */
 485         struct r300_ioctl ioctl;
 486         #endif
 487         struct r300_dma dma;
 488         GLboolean save_on_next_unlock;
 489
 490         /* Texture object bookkeeping
 491          */
 492         unsigned nr_heaps;
 493         driTexHeap *texture_heaps[R200_NR_TEX_HEAPS];
 494         driTextureObject swapped;
 495         int texture_depth;
 496         float initialMaxAnisotropy;
 497
 498         /* Clientdata textures;
 499          */
 500         GLuint prefer_gart_client_texturing;
 501
 502         /* TCL stuff
 503          */
 504         GLmatrix TexGenMatrix[R300_MAX_TEXTURE_UNITS];
 505         GLboolean recheck_texgen[R300_MAX_TEXTURE_UNITS];
 506         GLboolean TexGenNeedNormals[R300_MAX_TEXTURE_UNITS];
 507         GLuint TexMatEnabled;
 508         GLuint TexMatCompSel;
 509         GLuint TexGenEnabled;
 510         GLuint TexGenInputs;
 511         GLuint TexGenCompSel;
 512         GLmatrix tmpmat;
 513 };
 514
 515 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 516
 517 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 518 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 519                                    __DRIcontextPrivate * driContextPriv,
 520                                    void *sharedContextPrivate);
 521
 522 #endif                          /* __R300_CONTEXT_H__ */