src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 struct r300_context;
  51 typedef struct r300_context r300ContextRec;
  52 typedef struct r300_context *r300ContextPtr;
  53
  54 #include "radeon_lock.h"
  55 #include "mm.h"
  56
  57
  58 typedef GLuint uint32_t;
  59 typedef GLubyte uint8_t;
  60
  61   /* We should probably change types within vertex_shader
  62       and pixel_shader structure later on */
  63 #define CARD32 GLuint
  64 #include "vertex_shader.h"
  65 #include "pixel_shader.h"
  66 #undef CARD32
  67
  68 static __inline__ uint32_t r300PackFloat32(float fl)
  69 {
  70         union { float fl; uint32_t u; } u;
  71
  72         u.fl = fl;
  73         return u.u;
  74 }
  75
  76
  77 /************ DMA BUFFERS **************/
  78
  79 /* Need refcounting on dma buffers:
  80  */
  81 struct r300_dma_buffer {
  82         int refcount;           /* the number of retained regions in buf */
  83         drmBufPtr buf;
  84 };
  85
  86 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
  87                         (rvb)->address - rmesa->dma.buf0_address +      \
  88                         (rvb)->start)
  89
  90 /* A retained region, eg vertices for indexed vertices.
  91  */
  92 struct r300_dma_region {
  93         struct r300_dma_buffer *buf;
  94         char *address;          /* == buf->address */
  95         int start, end, ptr;    /* offsets from start of buf */
  96         int aos_start;
  97         int aos_stride;
  98         int aos_size;
  99 };
 100
 101 struct r300_dma {
 102         /* Active dma region.  Allocations for vertices and retained
 103          * regions come from here.  Also used for emitting random vertices,
 104          * these may be flushed by calling flush_current();
 105          */
 106         struct r300_dma_region current;
 107
 108         void (*flush) (r300ContextPtr);
 109
 110         char *buf0_address;     /* start of buf[0], for index calcs */
 111         GLuint nr_released_bufs;        /* flush after so many buffers released */
 112 };
 113
 114        /* Texture related */
 115
 116 #define TEX_0   0x1
 117 #define TEX_1   0x2
 118 #define TEX_2   0x4
 119 #define TEX_3   0x8
 120 #define TEX_4   0x10
 121 #define TEX_5   0x20
 122 #define TEX_6   0x40
 123 #define TEX_7   0x80
 124 #define TEX_ALL 0xff
 125
 126 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 127
 128 /* Texture object in locally shared texture space.
 129  */
 130 struct r300_tex_obj {
 131         driTextureObject base;
 132
 133         GLuint bufAddr;         /* Offset to start of locally
 134                                    shared texture block */
 135
 136         GLuint dirty_state;     /* Flags (1 per texunit) for
 137                                    whether or not this texobj
 138                                    has dirty hardware state
 139                                    (pp_*) that needs to be
 140                                    brought into the
 141                                    texunit. */
 142
 143         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 144         /* Six, for the cube faces */
 145
 146
 147         /* hardware register values */
 148         /* Note that R200 has 8 registers per texture and R300 only 7 */
 149         GLuint filter;
 150         GLuint pitch; /* one of the unknown registers.. unknown 1 ?*/
 151         GLuint size;    /* npot only */
 152         GLuint format;
 153         GLuint offset;  /* Image location in texmem.
 154                                    All cube faces follow. */
 155         GLuint unknown4;
 156         GLuint unknown5;
 157         /* end hardware registers */
 158
 159         /* registers computed by r200 code - keep them here to
 160            compare against what is actually written.
 161
 162            to be removed later.. */
 163         GLuint pp_border_color;
 164         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 165         GLuint format_x;
 166
 167
 168         GLboolean border_fallback;
 169 };
 170
 171 struct r300_texture_env_state {
 172         r300TexObjPtr texobj;
 173         GLenum format;
 174         GLenum envMode;
 175 };
 176
 177 #define R300_MAX_TEXTURE_UNITS 8
 178
 179 struct r300_texture_state {
 180         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 181         int tc_count; /* number of incoming texture coordinates from VAP */
 182 };
 183
 184 /**
 185  * A block of hardware state.
 186  *
 187  * When check returns non-zero, the returned number of dwords must be
 188  * copied verbatim into the command buffer in order to update a state atom
 189  * when it is dirty.
 190  */
 191 struct r300_state_atom {
 192         struct r300_state_atom *next, *prev;
 193         const char* name;       /* for debug */
 194         int cmd_size;           /* maximum size in dwords */
 195         GLuint idx;             /* index in an array (e.g. textures) */
 196         uint32_t* cmd;
 197         GLboolean dirty;
 198
 199         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 200 };
 201
 202
 203 #define R300_VPT_CMD_0          0
 204 #define R300_VPT_XSCALE         1
 205 #define R300_VPT_XOFFSET        2
 206 #define R300_VPT_YSCALE         3
 207 #define R300_VPT_YOFFSET        4
 208 #define R300_VPT_ZSCALE         5
 209 #define R300_VPT_ZOFFSET        6
 210 #define R300_VPT_CMDSIZE        7
 211
 212 #define R300_OVF_CMD_0          0
 213 #define R300_OVF_FMT_0          1
 214 #define R300_OVF_FMT_1          2
 215 #define R300_OVF_CMDSIZE        3
 216
 217 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 218 #define R300_VIR_CNTL_0         1
 219 #define R300_VIR_CNTL_1         2
 220 #define R300_VIR_CNTL_2         3
 221 #define R300_VIR_CNTL_3         4
 222 #define R300_VIR_CNTL_4         5
 223 #define R300_VIR_CNTL_5         6
 224 #define R300_VIR_CNTL_6         7
 225 #define R300_VIR_CNTL_7         8
 226 #define R300_VIR_CMDSIZE        9
 227
 228 #define R300_VIC_CMD_0          0
 229 #define R300_VIC_CNTL_0         1
 230 #define R300_VIC_CNTL_1         2
 231 #define R300_VIC_CMDSIZE        3
 232
 233 #define R300_VOF_CMD_0          0
 234 #define R300_VOF_CNTL_0         1
 235 #define R300_VOF_CNTL_1         2
 236 #define R300_VOF_CMDSIZE        3
 237
 238
 239 #define R300_PVS_CMD_0          0
 240 #define R300_PVS_CNTL_1         1
 241 #define R300_PVS_CNTL_2         2
 242 #define R300_PVS_CNTL_3         3
 243 #define R300_PVS_CMDSIZE        4
 244
 245 #define R300_GB_MISC_CMD_0              0
 246 #define R300_GB_MISC_MSPOS_0            1
 247 #define R300_GB_MISC_MSPOS_1            2
 248 #define R300_GB_MISC_TILE_CONFIG        3
 249 #define R300_GB_MISC_SELECT             4
 250 #define R300_GB_MISC_AA_CONFIG          5
 251 #define R300_GB_MISC_CMDSIZE            6
 252
 253 #define R300_TXE_CMD_0          0
 254 #define R300_TXE_ENABLE         1
 255 #define R300_TXE_CMDSIZE        2
 256
 257 #define R300_PS_CMD_0           0
 258 #define R300_PS_POINTSIZE       1
 259 #define R300_PS_CMDSIZE         2
 260
 261 #define R300_CUL_CMD_0          0
 262 #define R300_CUL_CULL           1
 263 #define R300_CUL_CMDSIZE        2
 264
 265 #define R300_RC_CMD_0           0
 266 #define R300_RC_CNTL_0          1
 267 #define R300_RC_CNTL_1          2
 268 #define R300_RC_CMDSIZE         3
 269
 270 #define R300_RI_CMD_0           0
 271 #define R300_RI_INTERP_0        1
 272 #define R300_RI_INTERP_1        2
 273 #define R300_RI_INTERP_2        3
 274 #define R300_RI_INTERP_3        4
 275 #define R300_RI_INTERP_4        5
 276 #define R300_RI_INTERP_5        6
 277 #define R300_RI_INTERP_6        7
 278 #define R300_RI_INTERP_7        8
 279 #define R300_RI_CMDSIZE         9
 280
 281 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 282 #define R300_RR_ROUTE_0         1
 283 #define R300_RR_ROUTE_1         2
 284 #define R300_RR_ROUTE_2         3
 285 #define R300_RR_ROUTE_3         4
 286 #define R300_RR_ROUTE_4         5
 287 #define R300_RR_ROUTE_5         6
 288 #define R300_RR_ROUTE_6         7
 289 #define R300_RR_ROUTE_7         8
 290 #define R300_RR_CMDSIZE         9
 291
 292 #define R300_FP_CMD_0           0
 293 #define R300_FP_CNTL0           1
 294 #define R300_FP_CNTL1           2
 295 #define R300_FP_CNTL2           3
 296 #define R300_FP_CMD_1           4
 297 #define R300_FP_NODE0           5
 298 #define R300_FP_NODE1           6
 299 #define R300_FP_NODE2           7
 300 #define R300_FP_NODE3           8
 301 #define R300_FP_CMDSIZE         9
 302
 303 #define R300_FPI_CMD_0          0
 304 #define R300_FPI_INSTR_0        1
 305 #define R300_FPI_CMDSIZE        65
 306
 307 #define R300_AT_CMD_0           0
 308 #define R300_AT_ALPHA_TEST      1
 309 #define R300_AT_CMDSIZE         2
 310
 311 #define R300_BLD_CMD_0          0
 312 #define R300_BLD_CBLEND         1
 313 #define R300_BLD_ABLEND         2
 314 #define R300_BLD_CMDSIZE        3
 315
 316 #define R300_CMK_CMD_0          0
 317 #define R300_CMK_COLORMASK      1
 318 #define R300_CMK_CMDSIZE        2
 319
 320 #define R300_CB_CMD_0           0
 321 #define R300_CB_OFFSET          1
 322 #define R300_CB_CMD_1           2
 323 #define R300_CB_PITCH           3
 324 #define R300_CB_CMDSIZE         4
 325
 326 #define R300_ZC_CMD_0           0
 327 #define R300_ZC_CNTL_0          1
 328 #define R300_ZC_CNTL_1          2
 329 #define R300_ZC_CMDSIZE         3
 330
 331 #define R300_ZB_CMD_0           0
 332 #define R300_ZB_OFFSET          1
 333 #define R300_ZB_PITCH           2
 334 #define R300_ZB_CMDSIZE         3
 335
 336 #define R300_VPI_CMD_0          0
 337 #define R300_VPI_INSTR_0        1
 338 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 339
 340 #define R300_VPP_CMD_0          0
 341 #define R300_VPP_PARAM_0        1
 342 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 343
 344 #define R300_VPS_CMD_0          0
 345 #define R300_VPS_ZERO_0         1
 346 #define R300_VPS_ZERO_1         2
 347 #define R300_VPS_POINTSIZE      3
 348 #define R300_VPS_ZERO_3         4
 349 #define R300_VPS_CMDSIZE        5
 350
 351         /* the layout is common for all fields inside tex */
 352 #define R300_TEX_CMD_0          0
 353 #define R300_TEX_VALUE_0        1
 354 /* We don't really use this, instead specify mtu+1 dynamically
 355 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 356 */
 357
 358 /**
 359  * Cache for hardware register state.
 360  */
 361 struct r300_hw_state {
 362         struct r300_state_atom atomlist;
 363
 364         GLboolean       is_dirty;
 365         GLboolean       all_dirty;
 366         int             max_state_size; /* in dwords */
 367
 368         struct r300_state_atom vpt;     /* viewport (1D98) */
 369         struct r300_state_atom unk2080; /* (2080) */
 370         struct r300_state_atom ovf;     /* output vertex format (2090) */
 371         struct r300_state_atom vte;     /* (20B0) */
 372         struct r300_state_atom unk2134; /* (2134) */
 373         struct r300_state_atom unk2140; /* (2140) */
 374         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 375         struct r300_state_atom vic;     /* vap input control (2180) */
 376         struct r300_state_atom unk21DC; /* (21DC) */
 377         struct r300_state_atom unk221C; /* (221C) */
 378         struct r300_state_atom unk2220; /* (2220) */
 379         struct r300_state_atom unk2288; /* (2288) */
 380         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 381         struct r300_state_atom vof;     /* VAP output format register 0x4000 */
 382         struct r300_state_atom gb_enable; /* (4008) */
 383         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 384         struct r300_state_atom unk4200; /* (4200) */
 385         struct r300_state_atom unk4214; /* (4214) */
 386         struct r300_state_atom ps;      /* pointsize (421C) */
 387         struct r300_state_atom unk4230; /* (4230) */
 388         struct r300_state_atom unk4260; /* (4260) */
 389         struct r300_state_atom unk4274; /* (4274) */
 390         struct r300_state_atom unk4288; /* (4288) */
 391         struct r300_state_atom unk42A0; /* (42A0) */
 392         struct r300_state_atom unk42B4; /* (42B4) */
 393         struct r300_state_atom cul;     /* cull cntl (42B8) */
 394         struct r300_state_atom unk42C0; /* (42C0) */
 395         struct r300_state_atom rc;      /* rs control (4300) */
 396         struct r300_state_atom ri;      /* rs interpolators (4310) */
 397         struct r300_state_atom rr;      /* rs route (4330) */
 398         struct r300_state_atom unk43A4; /* (43A4) */
 399         struct r300_state_atom unk43E8; /* (43E8) */
 400         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 401         struct r300_state_atom unk46A4; /* (46A4) */
 402         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 403         struct r300_state_atom unk4BC0; /* (4BC0) */
 404         struct r300_state_atom unk4BC8; /* (4BC8) */
 405         struct r300_state_atom at;      /* alpha test (4BD4) */
 406         struct r300_state_atom unk4BD8; /* (4BD8) */
 407         struct r300_state_atom unk4E00; /* (4E00) */
 408         struct r300_state_atom bld;     /* blending (4E04) */
 409         struct r300_state_atom cmk;     /* colormask (4E0C) */
 410         struct r300_state_atom unk4E10; /* (4E10) */
 411         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 412         struct r300_state_atom unk4E50; /* (4E50) */
 413         struct r300_state_atom unk4E88; /* (4E88) */
 414         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 415         struct r300_state_atom zc;      /* z control (4F00) */
 416         struct r300_state_atom unk4F08; /* (4F08) */
 417         struct r300_state_atom unk4F10; /* (4F10) */
 418         struct r300_state_atom zb;      /* z buffer (4F20) */
 419         struct r300_state_atom unk4F28; /* (4F28) */
 420         struct r300_state_atom unk4F30; /* (4F30) */
 421         struct r300_state_atom unk4F44; /* (4F44) */
 422         struct r300_state_atom unk4F54; /* (4F54) */
 423
 424         struct r300_state_atom vpi;     /* vp instructions */
 425         struct r300_state_atom vpp;     /* vp parameters */
 426         struct r300_state_atom vps;     /* vertex point size (?) */
 427
 428                 /* 8 texture units */
 429                 /* the state is grouped by function and not by
 430                    texture unit. This makes single unit updates
 431                    really awkward - we are much better off
 432                    updating the whole thing at once */
 433         struct {
 434                 struct r300_state_atom filter;
 435                 struct r300_state_atom unknown1;
 436                 struct r300_state_atom size;
 437                 struct r300_state_atom format;
 438                 struct r300_state_atom offset;
 439                 struct r300_state_atom unknown4;
 440                 struct r300_state_atom unknown5;
 441                 } tex;
 442         struct r300_state_atom txe;     /* tex enable (4104) */
 443 };
 444
 445
 446 /**
 447  * This structure holds the command buffer while it is being constructed.
 448  *
 449  * The first batch of commands in the buffer is always the state that needs
 450  * to be re-emitted when the context is lost. This batch can be skipped
 451  * otherwise.
 452  */
 453 struct r300_cmdbuf {
 454         int             size;           /* DWORDs allocated for buffer */
 455         uint32_t*       cmd_buf;
 456         int             count_used;     /* DWORDs filled so far */
 457         int             count_reemit;   /* size of re-emission batch */
 458 };
 459
 460
 461 /**
 462  * State cache
 463  */
 464
 465 struct r300_depthbuffer_state {
 466         GLfloat scale;
 467 };
 468
 469 struct r300_vap_reg_state {
 470            /* input register assigments */
 471            int i_coords;
 472            int i_color[2];
 473            int i_tex[R300_MAX_TEXTURE_UNITS];
 474         };
 475
 476 /* Vertex shader state */
 477
 478 /* 64 appears to be the maximum */
 479 #define VSF_MAX_FRAGMENT_LENGTH 64
 480
 481
 482 struct r300_vertex_shader_fragment {
 483         int length;
 484         union {
 485                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 486                 float f[VSF_MAX_FRAGMENT_LENGTH];
 487                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH/4];
 488                 } body;
 489         };
 490
 491 #define VSF_DEST_PROGRAM        0x0
 492 #define VSF_DEST_MATRIX0        0x200
 493 #define VSF_DEST_MATRIX1        0x204
 494 #define VSF_DEST_MATRIX2        0x208
 495 #define VSF_DEST_VECTOR0        0x20c
 496 #define VSF_DEST_VECTOR1        0x20d
 497 #define VSF_DEST_UNKNOWN1       0x400
 498 #define VSF_DEST_UNKNOWN2       0x406
 499
 500 struct r300_vertex_shader_state {
 501         struct r300_vertex_shader_fragment program;
 502
 503         /* a bit of a waste - each uses only a subset of allocated space..
 504             but easier to program */
 505         struct r300_vertex_shader_fragment matrix[3];
 506         struct r300_vertex_shader_fragment vector[2];
 507
 508         struct r300_vertex_shader_fragment unknown1;
 509         struct r300_vertex_shader_fragment unknown2;
 510
 511         int program_start;
 512         int unknown_ptr1;  /* pointer within program space */
 513         int program_end;
 514
 515         int param_offset;
 516         int param_count;
 517
 518         int unknown_ptr2;  /* pointer within program space */
 519         int unknown_ptr3;  /* pointer within program space */
 520         };
 521
 522 /* 64 appears to be the maximum */
 523 #define PSF_MAX_PROGRAM_LENGTH 64
 524
 525 struct r300_pixel_shader_program {
 526         struct {
 527                 int length;
 528                 GLuint inst[PSF_MAX_PROGRAM_LENGTH];
 529                 } tex;
 530
 531         /* ALU intructions (logic and integer) */
 532         struct {
 533                 int length;
 534                 struct {
 535                         GLuint inst0;
 536                         GLuint inst1;
 537                         GLuint inst2;
 538                         GLuint inst3;
 539                         } inst[PSF_MAX_PROGRAM_LENGTH];
 540                 } alu;
 541
 542         /* node information */
 543         /* nodes are used to synchronize ALU and TEX streams */
 544         /* There could be up to 4 nodes each consisting of
 545            a number of TEX instructions followed by some ALU
 546            instructions */
 547         /* the last node of a program should always be node3 */
 548         struct {
 549                 int tex_offset;
 550                 int tex_end;
 551                 int alu_offset;
 552                 int alu_end;
 553                 } node[4];
 554
 555         int active_nodes;       /* must be between 1 and 4, inclusive */
 556         int first_node_has_tex;  /* other nodes always have it */
 557
 558         int temp_register_count;  /* magic value goes into PFS_CNTL_1 */
 559
 560         /* entire program */
 561         int tex_offset;
 562         int tex_end;
 563         int alu_offset;
 564         int alu_end;
 565
 566         };
 567
 568         #define MAX_PIXEL_SHADER_PARAMS 32
 569 struct r300_pixel_shader_state {
 570         struct r300_pixel_shader_program program;
 571
 572         /* parameters */
 573         int param_length;  /* to limit the number of unnecessary writes */
 574         struct {
 575                 float x;
 576                 float y;
 577                 float z;
 578                 float w;
 579                 } param[MAX_PIXEL_SHADER_PARAMS];
 580         };
 581
 582 /* 8 is somewhat bogus... it is probably something like 24 */
 583 #define R300_MAX_AOS_ARRAYS             8
 584
 585 struct r300_aos_rec {
 586         GLuint offset;
 587         int element_size; /* in dwords */
 588         int stride;       /* distance between elements, in dwords */
 589
 590         #define AOS_FORMAT_FLOAT        1
 591         #define AOS_FORMAT_UBYTE        2
 592         #define AOS_FORMAT_FLOAT_COLOR  3
 593         int format;
 594
 595         int ncomponents; /* number of components - between 1 and 4, inclusive */
 596
 597          /* just guesses */
 598         #define REG_COORDS      0
 599         #define REG_COLOR0      1
 600         #define REG_TEX0        2
 601         int reg; /* which register they are assigned to. */
 602
 603         };
 604
 605 struct r300_state {
 606         struct r300_depthbuffer_state depth;
 607         struct r300_texture_state texture;
 608         struct r300_vap_reg_state vap_reg;
 609         struct r300_vertex_shader_state vertex_shader;
 610         struct r300_pixel_shader_state pixel_shader;
 611         struct r300_aos_rec aos[R300_MAX_AOS_ARRAYS];
 612         int aos_count;
 613
 614 };
 615
 616
 617 /**
 618  * R300 context structure.
 619  */
 620 struct r300_context {
 621         struct radeon_context radeon; /* parent class, must be first */
 622
 623         struct r300_hw_state hw;
 624         struct r300_cmdbuf cmdbuf;
 625         struct r300_state state;
 626
 627         /* Vertex buffers */
 628         int elt_count;  /* size of the buffer for vertices */
 629         int attrib_count; /* size of the buffer for vertex attributes.. Somehow it can be different ? */
 630
 631
 632         /* Vertex buffers
 633          */
 634         #if 0 /* we'll need it later, but not now */
 635         struct r300_ioctl ioctl;
 636         #endif
 637         struct r300_dma dma;
 638         GLboolean save_on_next_unlock;
 639
 640         /* Texture object bookkeeping
 641          */
 642         unsigned nr_heaps;
 643         driTexHeap *texture_heaps[R200_NR_TEX_HEAPS];
 644         driTextureObject swapped;
 645         int texture_depth;
 646         float initialMaxAnisotropy;
 647
 648         /* Clientdata textures;
 649          */
 650         GLuint prefer_gart_client_texturing;
 651
 652         /* TCL stuff
 653          */
 654         GLmatrix TexGenMatrix[R300_MAX_TEXTURE_UNITS];
 655         GLboolean recheck_texgen[R300_MAX_TEXTURE_UNITS];
 656         GLboolean TexGenNeedNormals[R300_MAX_TEXTURE_UNITS];
 657         GLuint TexMatEnabled;
 658         GLuint TexMatCompSel;
 659         GLuint TexGenEnabled;
 660         GLuint TexGenInputs;
 661         GLuint TexGenCompSel;
 662         GLmatrix tmpmat;
 663 };
 664
 665 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 666
 667 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 668 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 669                                    __DRIcontextPrivate * driContextPriv,
 670                                    void *sharedContextPrivate);
 671
 672 #endif                          /* __R300_CONTEXT_H__ */