src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 #define USER_BUFFERS
  51 /* KW: Disable this code.  Driver should hook into vbo module
  52  * directly, see i965 driver for example.
  53  */
  54 /* #define RADEON_VTXFMT_A */
  55 #ifdef RADEON_VTXFMT_A
  56 #define HW_VBOS
  57 #endif
  58
  59 /* We don't handle 16 bits elts swapping yet */
  60 #ifdef MESA_BIG_ENDIAN
  61 #define FORCE_32BITS_ELTS
  62 #endif
  63
  64 //#define OPTIMIZE_ELTS
  65
  66 struct r300_context;
  67 typedef struct r300_context r300ContextRec;
  68 typedef struct r300_context *r300ContextPtr;
  69
  70 #include "radeon_lock.h"
  71 #include "mm.h"
  72
  73 /* Checkpoint.. for convenience */
  74 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  75 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  76    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  77    with other compilers ... GLUE!
  78 */
  79 #if 1
  80 #define WARN_ONCE(a, ...)       { \
  81         static int warn##__LINE__=1; \
  82         if(warn##__LINE__){ \
  83                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  84                 fprintf(stderr, "File %s function %s line %d\n", \
  85                         __FILE__, __FUNCTION__, __LINE__); \
  86                 fprintf(stderr,  a, ## __VA_ARGS__);\
  87                 fprintf(stderr, "***************************************************************************\n"); \
  88                 warn##__LINE__=0;\
  89                 } \
  90         }
  91 #else
  92 #define WARN_ONCE(a, ...) {}
  93 #endif
  94
  95 #include "r300_vertprog.h"
  96 #include "r300_fragprog.h"
  97
  98 static __inline__ uint32_t r300PackFloat32(float fl)
  99 {
 100         union {
 101                 float fl;
 102                 uint32_t u;
 103         } u;
 104
 105         u.fl = fl;
 106         return u.u;
 107 }
 108
 109 /************ DMA BUFFERS **************/
 110
 111 /* Need refcounting on dma buffers:
 112  */
 113 struct r300_dma_buffer {
 114         int refcount;           /* the number of retained regions in buf */
 115         drmBufPtr buf;
 116         int id;
 117 };
 118 #undef GET_START
 119 #ifdef USER_BUFFERS
 120 #define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start))
 121 #else
 122 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 123                         (rvb)->address - rmesa->dma.buf0_address +      \
 124                         (rvb)->start)
 125 #endif
 126 /* A retained region, eg vertices for indexed vertices.
 127  */
 128 struct r300_dma_region {
 129         struct r300_dma_buffer *buf;
 130         char *address;          /* == buf->address */
 131         int start, end, ptr;    /* offsets from start of buf */
 132
 133         int aos_offset;         /* address in GART memory */
 134         int aos_stride;         /* distance between elements, in dwords */
 135         int aos_size;           /* number of components (1-4) */
 136         int aos_reg;            /* VAP register assignment */
 137 };
 138
 139 struct r300_dma {
 140         /* Active dma region.  Allocations for vertices and retained
 141          * regions come from here.  Also used for emitting random vertices,
 142          * these may be flushed by calling flush_current();
 143          */
 144         struct r300_dma_region current;
 145
 146         void (*flush) (r300ContextPtr);
 147
 148         char *buf0_address;     /* start of buf[0], for index calcs */
 149
 150         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 151          * for which a DISCARD command is currently queued in the command buffer.
 152          */
 153         GLuint nr_released_bufs;
 154 };
 155
 156        /* Texture related */
 157
 158 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 159
 160 /* Texture object in locally shared texture space.
 161  */
 162 struct r300_tex_obj {
 163         driTextureObject base;
 164
 165         GLuint bufAddr;         /* Offset to start of locally
 166                                    shared texture block */
 167
 168         GLuint dirty_state;     /* Flags (1 per texunit) for
 169                                    whether or not this texobj
 170                                    has dirty hardware state
 171                                    (pp_*) that needs to be
 172                                    brought into the
 173                                    texunit. */
 174
 175         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 176         /* Six, for the cube faces */
 177
 178         GLuint pitch;           /* this isn't sent to hardware just used in calculations */
 179         /* hardware register values */
 180         /* Note that R200 has 8 registers per texture and R300 only 7 */
 181         GLuint filter;
 182         GLuint filter_1;
 183         GLuint pitch_reg;
 184         GLuint size;            /* npot only */
 185         GLuint format;
 186         GLuint offset;          /* Image location in the card's address space.
 187                                    All cube faces follow. */
 188         GLuint unknown4;
 189         GLuint unknown5;
 190         /* end hardware registers */
 191
 192         /* registers computed by r200 code - keep them here to
 193            compare against what is actually written.
 194
 195            to be removed later.. */
 196         GLuint pp_border_color;
 197         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 198         GLuint format_x;
 199
 200         GLboolean border_fallback;
 201
 202         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 203 };
 204
 205 struct r300_texture_env_state {
 206         r300TexObjPtr texobj;
 207         GLenum format;
 208         GLenum envMode;
 209 };
 210
 211 /* The blit width for texture uploads
 212  */
 213 #define R300_BLIT_WIDTH_BYTES 1024
 214 #define R300_MAX_TEXTURE_UNITS 8
 215
 216 struct r300_texture_state {
 217         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 218         int tc_count;           /* number of incoming texture coordinates from VAP */
 219 };
 220
 221 /**
 222  * A block of hardware state.
 223  *
 224  * When check returns non-zero, the returned number of dwords must be
 225  * copied verbatim into the command buffer in order to update a state atom
 226  * when it is dirty.
 227  */
 228 struct r300_state_atom {
 229         struct r300_state_atom *next, *prev;
 230         const char *name;       /* for debug */
 231         int cmd_size;           /* maximum size in dwords */
 232         GLuint idx;             /* index in an array (e.g. textures) */
 233         uint32_t *cmd;
 234         GLboolean dirty;
 235
 236         int (*check) (r300ContextPtr, struct r300_state_atom * atom);
 237 };
 238
 239 #define R300_VPT_CMD_0          0
 240 #define R300_VPT_XSCALE         1
 241 #define R300_VPT_XOFFSET        2
 242 #define R300_VPT_YSCALE         3
 243 #define R300_VPT_YOFFSET        4
 244 #define R300_VPT_ZSCALE         5
 245 #define R300_VPT_ZOFFSET        6
 246 #define R300_VPT_CMDSIZE        7
 247
 248 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
 249 #define R300_VIR_CNTL_0         1
 250 #define R300_VIR_CNTL_1         2
 251 #define R300_VIR_CNTL_2         3
 252 #define R300_VIR_CNTL_3         4
 253 #define R300_VIR_CNTL_4         5
 254 #define R300_VIR_CNTL_5         6
 255 #define R300_VIR_CNTL_6         7
 256 #define R300_VIR_CNTL_7         8
 257 #define R300_VIR_CMDSIZE        9
 258
 259 #define R300_VIC_CMD_0          0
 260 #define R300_VIC_CNTL_0         1
 261 #define R300_VIC_CNTL_1         2
 262 #define R300_VIC_CMDSIZE        3
 263
 264 #define R300_VOF_CMD_0          0
 265 #define R300_VOF_CNTL_0         1
 266 #define R300_VOF_CNTL_1         2
 267 #define R300_VOF_CMDSIZE        3
 268
 269 #define R300_PVS_CMD_0          0
 270 #define R300_PVS_CNTL_1         1
 271 #define R300_PVS_CNTL_2         2
 272 #define R300_PVS_CNTL_3         3
 273 #define R300_PVS_CMDSIZE        4
 274
 275 #define R300_GB_MISC_CMD_0              0
 276 #define R300_GB_MISC_MSPOS_0            1
 277 #define R300_GB_MISC_MSPOS_1            2
 278 #define R300_GB_MISC_TILE_CONFIG        3
 279 #define R300_GB_MISC_SELECT             4
 280 #define R300_GB_MISC_AA_CONFIG          5
 281 #define R300_GB_MISC_CMDSIZE            6
 282
 283 #define R300_TXE_CMD_0          0
 284 #define R300_TXE_ENABLE         1
 285 #define R300_TXE_CMDSIZE        2
 286
 287 #define R300_PS_CMD_0           0
 288 #define R300_PS_POINTSIZE       1
 289 #define R300_PS_CMDSIZE         2
 290
 291 #define R300_ZBS_CMD_0          0
 292 #define R300_ZBS_T_FACTOR       1
 293 #define R300_ZBS_T_CONSTANT     2
 294 #define R300_ZBS_W_FACTOR       3
 295 #define R300_ZBS_W_CONSTANT     4
 296 #define R300_ZBS_CMDSIZE        5
 297
 298 #define R300_CUL_CMD_0          0
 299 #define R300_CUL_CULL           1
 300 #define R300_CUL_CMDSIZE        2
 301
 302 #define R300_RC_CMD_0           0
 303 #define R300_RC_CNTL_0          1
 304 #define R300_RC_CNTL_1          2
 305 #define R300_RC_CMDSIZE         3
 306
 307 #define R300_RI_CMD_0           0
 308 #define R300_RI_INTERP_0        1
 309 #define R300_RI_INTERP_1        2
 310 #define R300_RI_INTERP_2        3
 311 #define R300_RI_INTERP_3        4
 312 #define R300_RI_INTERP_4        5
 313 #define R300_RI_INTERP_5        6
 314 #define R300_RI_INTERP_6        7
 315 #define R300_RI_INTERP_7        8
 316 #define R300_RI_CMDSIZE         9
 317
 318 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 319 #define R300_RR_ROUTE_0         1
 320 #define R300_RR_ROUTE_1         2
 321 #define R300_RR_ROUTE_2         3
 322 #define R300_RR_ROUTE_3         4
 323 #define R300_RR_ROUTE_4         5
 324 #define R300_RR_ROUTE_5         6
 325 #define R300_RR_ROUTE_6         7
 326 #define R300_RR_ROUTE_7         8
 327 #define R300_RR_CMDSIZE         9
 328
 329 #define R300_FP_CMD_0           0
 330 #define R300_FP_CNTL0           1
 331 #define R300_FP_CNTL1           2
 332 #define R300_FP_CNTL2           3
 333 #define R300_FP_CMD_1           4
 334 #define R300_FP_NODE0           5
 335 #define R300_FP_NODE1           6
 336 #define R300_FP_NODE2           7
 337 #define R300_FP_NODE3           8
 338 #define R300_FP_CMDSIZE         9
 339
 340 #define R300_FPT_CMD_0          0
 341 #define R300_FPT_INSTR_0        1
 342 #define R300_FPT_CMDSIZE        65
 343
 344 #define R300_FPI_CMD_0          0
 345 #define R300_FPI_INSTR_0        1
 346 #define R300_FPI_CMDSIZE        65
 347
 348 #define R300_FPP_CMD_0          0
 349 #define R300_FPP_PARAM_0        1
 350 #define R300_FPP_CMDSIZE        (32*4+1)
 351
 352 #define R300_FOGS_CMD_0         0
 353 #define R300_FOGS_STATE         1
 354 #define R300_FOGS_CMDSIZE       2
 355
 356 #define R300_FOGC_CMD_0         0
 357 #define R300_FOGC_R             1
 358 #define R300_FOGC_G             2
 359 #define R300_FOGC_B             3
 360 #define R300_FOGC_CMDSIZE       4
 361
 362 #define R300_FOGP_CMD_0         0
 363 #define R300_FOGP_SCALE         1
 364 #define R300_FOGP_START         2
 365 #define R300_FOGP_CMDSIZE       3
 366
 367 #define R300_AT_CMD_0           0
 368 #define R300_AT_ALPHA_TEST      1
 369 #define R300_AT_UNKNOWN         2
 370 #define R300_AT_CMDSIZE         3
 371
 372 #define R300_BLD_CMD_0          0
 373 #define R300_BLD_CBLEND         1
 374 #define R300_BLD_ABLEND         2
 375 #define R300_BLD_CMDSIZE        3
 376
 377 #define R300_CMK_CMD_0          0
 378 #define R300_CMK_COLORMASK      1
 379 #define R300_CMK_CMDSIZE        2
 380
 381 #define R300_CB_CMD_0           0
 382 #define R300_CB_OFFSET          1
 383 #define R300_CB_CMD_1           2
 384 #define R300_CB_PITCH           3
 385 #define R300_CB_CMDSIZE         4
 386
 387 #define R300_ZS_CMD_0           0
 388 #define R300_ZS_CNTL_0          1
 389 #define R300_ZS_CNTL_1          2
 390 #define R300_ZS_CNTL_2          3
 391 #define R300_ZS_CMDSIZE         4
 392
 393 #define R300_ZB_CMD_0           0
 394 #define R300_ZB_OFFSET          1
 395 #define R300_ZB_PITCH           2
 396 #define R300_ZB_CMDSIZE         3
 397
 398 #define R300_VPI_CMD_0          0
 399 #define R300_VPI_INSTR_0        1
 400 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 401
 402 #define R300_VPP_CMD_0          0
 403 #define R300_VPP_PARAM_0        1
 404 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 405
 406 #define R300_VPS_CMD_0          0
 407 #define R300_VPS_ZERO_0         1
 408 #define R300_VPS_ZERO_1         2
 409 #define R300_VPS_POINTSIZE      3
 410 #define R300_VPS_ZERO_3         4
 411 #define R300_VPS_CMDSIZE        5
 412
 413         /* the layout is common for all fields inside tex */
 414 #define R300_TEX_CMD_0          0
 415 #define R300_TEX_VALUE_0        1
 416 /* We don't really use this, instead specify mtu+1 dynamically
 417 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 418 */
 419
 420 /**
 421  * Cache for hardware register state.
 422  */
 423 struct r300_hw_state {
 424         struct r300_state_atom atomlist;
 425
 426         GLboolean is_dirty;
 427         GLboolean all_dirty;
 428         int max_state_size;     /* in dwords */
 429
 430         struct r300_state_atom vpt;     /* viewport (1D98) */
 431         struct r300_state_atom vap_cntl;
 432         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 433         struct r300_state_atom vte;     /* (20B0) */
 434         struct r300_state_atom unk2134; /* (2134) */
 435         struct r300_state_atom vap_cntl_status;
 436         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 437         struct r300_state_atom vic;     /* vap input control (2180) */
 438         struct r300_state_atom unk21DC; /* (21DC) */
 439         struct r300_state_atom unk221C; /* (221C) */
 440         struct r300_state_atom unk2220; /* (2220) */
 441         struct r300_state_atom unk2288; /* (2288) */
 442         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 443         struct r300_state_atom gb_enable;       /* (4008) */
 444         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 445         struct r300_state_atom unk4200; /* (4200) */
 446         struct r300_state_atom unk4214; /* (4214) */
 447         struct r300_state_atom ps;      /* pointsize (421C) */
 448         struct r300_state_atom unk4230; /* (4230) */
 449         struct r300_state_atom lcntl;   /* line control */
 450         struct r300_state_atom unk4260; /* (4260) */
 451         struct r300_state_atom shade;
 452         struct r300_state_atom polygon_mode;
 453         struct r300_state_atom fogp;    /* fog parameters (4294) */
 454         struct r300_state_atom unk429C; /* (429C) */
 455         struct r300_state_atom zbias_cntl;
 456         struct r300_state_atom zbs;     /* zbias (42A4) */
 457         struct r300_state_atom occlusion_cntl;
 458         struct r300_state_atom cul;     /* cull cntl (42B8) */
 459         struct r300_state_atom unk42C0; /* (42C0) */
 460         struct r300_state_atom rc;      /* rs control (4300) */
 461         struct r300_state_atom ri;      /* rs interpolators (4310) */
 462         struct r300_state_atom rr;      /* rs route (4330) */
 463         struct r300_state_atom unk43A4; /* (43A4) */
 464         struct r300_state_atom unk43E8; /* (43E8) */
 465         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 466         struct r300_state_atom fpt;     /* texi - (4620) */
 467         struct r300_state_atom unk46A4; /* (46A4) */
 468         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 469         struct r300_state_atom fogs;    /* fog state (4BC0) */
 470         struct r300_state_atom fogc;    /* fog color (4BC8) */
 471         struct r300_state_atom at;      /* alpha test (4BD4) */
 472         struct r300_state_atom unk4BD8; /* (4BD8) */
 473         struct r300_state_atom fpp;     /* 0x4C00 and following */
 474         struct r300_state_atom unk4E00; /* (4E00) */
 475         struct r300_state_atom bld;     /* blending (4E04) */
 476         struct r300_state_atom cmk;     /* colormask (4E0C) */
 477         struct r300_state_atom blend_color;     /* constant blend color */
 478         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 479         struct r300_state_atom unk4E50; /* (4E50) */
 480         struct r300_state_atom unk4E88; /* (4E88) */
 481         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 482         struct r300_state_atom zs;      /* zstencil control (4F00) */
 483         struct r300_state_atom zstencil_format;
 484         struct r300_state_atom zb;      /* z buffer (4F20) */
 485         struct r300_state_atom unk4F28; /* (4F28) */
 486         struct r300_state_atom unk4F30; /* (4F30) */
 487         struct r300_state_atom unk4F44; /* (4F44) */
 488         struct r300_state_atom unk4F54; /* (4F54) */
 489
 490         struct r300_state_atom vpi;     /* vp instructions */
 491         struct r300_state_atom vpp;     /* vp parameters */
 492         struct r300_state_atom vps;     /* vertex point size (?) */
 493         /* 8 texture units */
 494         /* the state is grouped by function and not by
 495            texture unit. This makes single unit updates
 496            really awkward - we are much better off
 497            updating the whole thing at once */
 498         struct {
 499                 struct r300_state_atom filter;
 500                 struct r300_state_atom filter_1;
 501                 struct r300_state_atom size;
 502                 struct r300_state_atom format;
 503                 struct r300_state_atom pitch;
 504                 struct r300_state_atom offset;
 505                 struct r300_state_atom chroma_key;
 506                 struct r300_state_atom border_color;
 507         } tex;
 508         struct r300_state_atom txe;     /* tex enable (4104) */
 509 };
 510
 511 /**
 512  * This structure holds the command buffer while it is being constructed.
 513  *
 514  * The first batch of commands in the buffer is always the state that needs
 515  * to be re-emitted when the context is lost. This batch can be skipped
 516  * otherwise.
 517  */
 518 struct r300_cmdbuf {
 519         int size;               /* DWORDs allocated for buffer */
 520         uint32_t *cmd_buf;
 521         int count_used;         /* DWORDs filled so far */
 522         int count_reemit;       /* size of re-emission batch */
 523 };
 524
 525 /**
 526  * State cache
 527  */
 528
 529 struct r300_depthbuffer_state {
 530         GLfloat scale;
 531 };
 532
 533 struct r300_stencilbuffer_state {
 534         GLuint clear;
 535         GLboolean hw_stencil;
 536
 537 };
 538
 539 /* Vertex shader state */
 540
 541 /* Perhaps more if we store programs in vmem? */
 542 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 543 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 544
 545 /* Can be tested with colormat currently. */
 546 #define VSF_MAX_FRAGMENT_TEMPS (14)
 547
 548 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 549 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 550
 551 struct r300_vertex_shader_fragment {
 552         int length;
 553         union {
 554                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 555                 float f[VSF_MAX_FRAGMENT_LENGTH];
 556                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH / 4];
 557         } body;
 558 };
 559
 560 #define VSF_DEST_PROGRAM        0x0
 561 #define VSF_DEST_MATRIX0        0x200
 562 #define VSF_DEST_MATRIX1        0x204
 563 #define VSF_DEST_MATRIX2        0x208
 564 #define VSF_DEST_VECTOR0        0x20c
 565 #define VSF_DEST_VECTOR1        0x20d
 566 #define VSF_DEST_UNKNOWN1       0x400
 567 #define VSF_DEST_UNKNOWN2       0x406
 568
 569 struct r300_vertex_shader_state {
 570         struct r300_vertex_shader_fragment program;
 571
 572         struct r300_vertex_shader_fragment unknown1;
 573         struct r300_vertex_shader_fragment unknown2;
 574
 575         int program_start;
 576         int unknown_ptr1;       /* pointer within program space */
 577         int program_end;
 578
 579         int param_offset;
 580         int param_count;
 581
 582         int unknown_ptr2;       /* pointer within program space */
 583         int unknown_ptr3;       /* pointer within program space */
 584 };
 585
 586 extern int hw_tcl_on;
 587
 588 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 589 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 590
 591 /* Should but doesnt work */
 592 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 593
 594 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 595  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 596  */
 597
 598 struct r300_vertex_program_key {
 599         GLuint InputsRead;
 600         GLuint OutputsWritten;
 601 };
 602
 603 struct r300_vertex_program {
 604         struct r300_vertex_program *next;
 605         struct r300_vertex_program_key key;
 606         int translated;
 607
 608         struct r300_vertex_shader_fragment program;
 609
 610         int pos_end;
 611         int num_temporaries;    /* Number of temp vars used by program */
 612         int wpos_idx;
 613         int inputs[VERT_ATTRIB_MAX];
 614         int outputs[VERT_RESULT_MAX];
 615         int native;
 616         int ref_count;
 617         int use_ref_count;
 618 };
 619
 620 struct r300_vertex_program_cont {
 621         struct gl_vertex_program mesa_program;  /* Must be first */
 622         struct r300_vertex_shader_fragment params;
 623         struct r300_vertex_program *progs;
 624 };
 625
 626 #define PFS_MAX_ALU_INST        64
 627 #define PFS_MAX_TEX_INST        64
 628 #define PFS_MAX_TEX_INDIRECT 4
 629 #define PFS_NUM_TEMP_REGS       32
 630 #define PFS_NUM_CONST_REGS      16
 631
 632 /* Mapping Mesa registers to R300 temporaries */
 633 struct reg_acc {
 634         int reg;                /* Assigned hw temp */
 635         unsigned int refcount;  /* Number of uses by mesa program */
 636 };
 637
 638 /**
 639  * Describe the current lifetime information for an R300 temporary
 640  */
 641 struct reg_lifetime {
 642         /* Index of the first slot where this register is free in the sense
 643            that it can be used as a new destination register.
 644            This is -1 if the register has been assigned to a Mesa register
 645            and the last access to the register has not yet been emitted */
 646         int free;
 647
 648         /* Index of the first slot where this register is currently reserved.
 649            This is used to stop e.g. a scalar operation from being moved
 650            before the allocation time of a register that was first allocated
 651            for a vector operation. */
 652         int reserved;
 653
 654         /* Index of the first slot in which the register can be used as a
 655            source without losing the value that is written by the last
 656            emitted instruction that writes to the register */
 657         int vector_valid;
 658         int scalar_valid;
 659
 660         /* Index to the slot where the register was last read.
 661            This is also the first slot in which the register may be written again */
 662         int vector_lastread;
 663         int scalar_lastread;
 664 };
 665
 666 /**
 667  * Store usage information about an ALU instruction slot during the
 668  * compilation of a fragment program.
 669  */
 670 #define SLOT_SRC_VECTOR  (1<<0)
 671 #define SLOT_SRC_SCALAR  (1<<3)
 672 #define SLOT_SRC_BOTH    (SLOT_SRC_VECTOR | SLOT_SRC_SCALAR)
 673 #define SLOT_OP_VECTOR   (1<<16)
 674 #define SLOT_OP_SCALAR   (1<<17)
 675 #define SLOT_OP_BOTH     (SLOT_OP_VECTOR | SLOT_OP_SCALAR)
 676
 677 struct r300_pfs_compile_slot {
 678         /* Bitmask indicating which parts of the slot are used, using SLOT_ constants
 679            defined above */
 680         unsigned int used;
 681
 682         /* Selected sources */
 683         int vsrc[3];
 684         int ssrc[3];
 685 };
 686
 687 /**
 688  * Store information during compilation of fragment programs.
 689  */
 690 struct r300_pfs_compile_state {
 691         int nrslots;            /* number of ALU slots used so far */
 692
 693         /* Track which (parts of) slots are already filled with instructions */
 694         struct r300_pfs_compile_slot slot[PFS_MAX_ALU_INST];
 695
 696         /* Track the validity of R300 temporaries */
 697         struct reg_lifetime hwtemps[PFS_NUM_TEMP_REGS];
 698
 699         /* Used to map Mesa's inputs/temps onto hardware temps */
 700         int temp_in_use;
 701         struct reg_acc temps[PFS_NUM_TEMP_REGS];
 702         struct reg_acc inputs[32];      /* don't actually need 32... */
 703
 704         /* Track usage of hardware temps, for register allocation,
 705          * indirection detection, etc. */
 706         GLuint used_in_node;
 707         GLuint dest_in_node;
 708 };
 709
 710 /**
 711  * Store everything about a fragment program that is needed
 712  * to render with that program.
 713  */
 714 struct r300_fragment_program {
 715         struct gl_fragment_program mesa_program;
 716
 717         GLcontext *ctx;
 718         GLboolean translated;
 719         GLboolean error;
 720         struct r300_pfs_compile_state *cs;
 721
 722         struct {
 723                 int length;
 724                 GLuint inst[PFS_MAX_TEX_INST];
 725         } tex;
 726
 727         struct {
 728                 struct {
 729                         GLuint inst0;
 730                         GLuint inst1;
 731                         GLuint inst2;
 732                         GLuint inst3;
 733                 } inst[PFS_MAX_ALU_INST];
 734         } alu;
 735
 736         struct {
 737                 int tex_offset;
 738                 int tex_end;
 739                 int alu_offset;
 740                 int alu_end;
 741                 int flags;
 742         } node[4];
 743         int cur_node;
 744         int first_node_has_tex;
 745
 746         int alu_offset;
 747         int alu_end;
 748         int tex_offset;
 749         int tex_end;
 750
 751         /* Hardware constants.
 752          * Contains a pointer to the value. The destination of the pointer
 753          * is supposed to be updated when GL state changes.
 754          * Typically, this is either a pointer into
 755          * gl_program_parameter_list::ParameterValues, or a pointer to a
 756          * global constant (e.g. for sin/cos-approximation)
 757          */
 758         const GLfloat *constant[PFS_NUM_CONST_REGS];
 759         int const_nr;
 760
 761         int max_temp_idx;
 762
 763         GLuint optimization;
 764 };
 765
 766 #define R300_MAX_AOS_ARRAYS             16
 767
 768 #define AOS_FORMAT_USHORT       0
 769 #define AOS_FORMAT_FLOAT        1
 770 #define AOS_FORMAT_UBYTE        2
 771 #define AOS_FORMAT_FLOAT_COLOR  3
 772
 773 #define REG_COORDS      0
 774 #define REG_COLOR0      1
 775 #define REG_TEX0        2
 776
 777 struct dt {
 778         GLint size;
 779         GLenum type;
 780         GLsizei stride;
 781         void *data;
 782 };
 783
 784 struct radeon_vertex_buffer {
 785         int Count;
 786         void *Elts;
 787         int elt_size;
 788         int elt_min, elt_max;   /* debug */
 789
 790         struct dt AttribPtr[VERT_ATTRIB_MAX];
 791
 792         const struct _mesa_prim *Primitive;
 793         GLuint PrimitiveCount;
 794         GLint LockFirst;
 795         GLsizei LockCount;
 796         int lock_uptodate;
 797 };
 798
 799 struct r300_aos_rec {
 800         GLuint offset;
 801         int element_size;       /* in dwords */
 802         int stride;             /* distance between elements, in dwords */
 803
 804         int format;
 805
 806         int ncomponents;        /* number of components - between 1 and 4, inclusive */
 807
 808         int reg;                /* which register they are assigned to. */
 809
 810 };
 811
 812 struct r300_state {
 813         struct r300_depthbuffer_state depth;
 814         struct r300_texture_state texture;
 815         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 816         struct r300_vertex_shader_state vertex_shader;
 817         struct r300_pfs_compile_state pfs_compile;
 818         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 819         int aos_count;
 820         struct radeon_vertex_buffer VB;
 821
 822         GLuint *Elts;
 823         struct r300_dma_region elt_dma;
 824
 825          DECLARE_RENDERINPUTS(render_inputs_bitset);    /* actual render inputs that R300 was configured for.
 826                                                            They are the same as tnl->render_inputs for fixed pipeline */
 827
 828         struct {
 829                 int transform_offset;   /* Transform matrix offset, -1 if none */
 830         } vap_param;            /* vertex processor parameter allocation - tells where to write parameters */
 831
 832         struct r300_stencilbuffer_state stencil;
 833
 834 };
 835
 836 #define R300_FALLBACK_NONE 0
 837 #define R300_FALLBACK_TCL 1
 838 #define R300_FALLBACK_RAST 2
 839
 840 /**
 841  * R300 context structure.
 842  */
 843 struct r300_context {
 844         struct radeon_context radeon;   /* parent class, must be first */
 845
 846         struct r300_hw_state hw;
 847         struct r300_cmdbuf cmdbuf;
 848         struct r300_state state;
 849         struct gl_vertex_program *curr_vp;
 850         struct r300_vertex_program *selected_vp;
 851
 852         /* Vertex buffers
 853          */
 854         struct r300_dma dma;
 855         GLboolean save_on_next_unlock;
 856         GLuint NewGLState;
 857
 858         /* Texture object bookkeeping
 859          */
 860         unsigned nr_heaps;
 861         driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
 862         driTextureObject swapped;
 863         int texture_depth;
 864         float initialMaxAnisotropy;
 865
 866         /* Clientdata textures;
 867          */
 868         GLuint prefer_gart_client_texturing;
 869
 870 #ifdef USER_BUFFERS
 871         struct radeon_memory_manager *rmm;
 872         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 873         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 874 #endif
 875
 876         GLboolean texmicrotile;
 877         GLboolean span_dlocking;
 878         GLboolean disable_lowimpact_fallback;
 879 };
 880
 881 struct r300_buffer_object {
 882         struct gl_buffer_object mesa_obj;
 883         int id;
 884 };
 885
 886 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 887
 888 static __inline GLuint r300PackColor(GLuint cpp,
 889                                      GLubyte r, GLubyte g, GLubyte b, GLubyte a)
 890 {
 891         switch (cpp) {
 892         case 2:
 893                 return PACK_COLOR_565(r, g, b);
 894         case 4:
 895                 return PACK_COLOR_8888(r, g, b, a);
 896         default:
 897                 return 0;
 898         }
 899 }
 900 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 901 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 902                                    __DRIcontextPrivate * driContextPriv,
 903                                    void *sharedContextPrivate);
 904
 905 extern int r300_get_num_verts(r300ContextPtr rmesa, int num_verts, int prim);
 906
 907 extern void r300_select_vertex_shader(r300ContextPtr r300);
 908 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 909 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 910                                       struct r300_vertex_program_cont *vp,
 911                                       float *dst);
 912 extern int r300Fallback(GLcontext * ctx);
 913
 914 extern void radeon_vb_to_rvb(r300ContextPtr rmesa,
 915                              struct radeon_vertex_buffer *rvb,
 916                              struct vertex_buffer *vb);
 917 extern GLboolean r300RunRender(GLcontext * ctx,
 918                                struct tnl_pipeline_stage *stage);
 919
 920 #ifdef RADEON_VTXFMT_A
 921 extern void radeon_init_vtxfmt_a(r300ContextPtr rmesa);
 922 #endif
 923
 924 #ifdef HW_VBOS
 925 extern void r300InitVBOFuncs(struct dd_function_table *functions);
 926 extern void r300EvictVBOs(GLcontext * ctx, int amount);
 927 #endif
 928
 929 #define RADEON_D_CAPTURE 0
 930 #define RADEON_D_PLAYBACK 1
 931 #define RADEON_D_PLAYBACK_RAW 2
 932 #define RADEON_D_T 3
 933
 934 #endif                          /* __R300_CONTEXT_H__ */