b8523b677224439d55f49de1ab88fcfbfa11ef0f
[mesa.git] / src / mesa / drivers / dri / r300 / r300_context.h
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Keith Whitwell <keith@tungstengraphics.com>
33 * Nicolai Haehnle <prefect_@gmx.net>
34 */
35
36 #ifndef __R300_CONTEXT_H__
37 #define __R300_CONTEXT_H__
38
39 #include "tnl/t_vertex.h"
40 #include "drm.h"
41 #include "radeon_drm.h"
42 #include "dri_util.h"
43 #include "texmem.h"
44
45 #include "macros.h"
46 #include "mtypes.h"
47 #include "colormac.h"
48 #include "radeon_context.h"
49
50 struct r300_context;
51 typedef struct r300_context r300ContextRec;
52 typedef struct r300_context *r300ContextPtr;
53
54 #include "radeon_lock.h"
55 #include "mm.h"
56
57
58 static __inline__ uint32_t r300PackFloat32(float fl)
59 {
60 union { float fl; uint32_t u; } u;
61
62 u.fl = fl;
63 return u.u;
64 }
65
66 /**
67 * A block of hardware state.
68 *
69 * When check returns non-zero, the returned number of dwords must be
70 * copied verbatim into the command buffer in order to update a state atom
71 * when it is dirty.
72 */
73 struct r300_state_atom {
74 struct r300_state_atom *next, *prev;
75 const char* name; /* for debug */
76 int cmd_size; /* maximum size in dwords */
77 GLuint idx; /* index in an array (e.g. textures) */
78 uint32_t* cmd;
79 GLboolean dirty;
80
81 int (*check)(r300ContextPtr, struct r300_state_atom* atom);
82 };
83
84
85 #define R300_VPT_CMD_0 0
86 #define R300_VPT_XSCALE 1
87 #define R300_VPT_XOFFSET 2
88 #define R300_VPT_YSCALE 3
89 #define R300_VPT_YOFFSET 4
90 #define R300_VPT_ZSCALE 5
91 #define R300_VPT_ZOFFSET 6
92 #define R300_VPT_CMDSIZE 7
93
94 #define R300_OVF_CMD_0 0
95 #define R300_OVF_FMT_0 1
96 #define R300_OVF_FMT_1 2
97 #define R300_OVF_CMDSIZE 3
98
99 #define R300_VIR_CMD_0 0 /* vir is variable size (at least 1) */
100 #define R300_VIR_CNTL_0 1
101 #define R300_VIR_CNTL_1 2
102 #define R300_VIR_CNTL_2 3
103 #define R300_VIR_CNTL_3 4
104 #define R300_VIR_CNTL_4 5
105 #define R300_VIR_CNTL_5 6
106 #define R300_VIR_CNTL_6 7
107 #define R300_VIR_CNTL_7 8
108 #define R300_VIR_CMDSIZE 9
109
110 #define R300_VIC_CMD_0 0
111 #define R300_VIC_CNTL_0 1
112 #define R300_VIC_CNTL_1 2
113 #define R300_VIC_CMDSIZE 3
114
115 #define R300_PVS_CMD_0 0
116 #define R300_PVS_CNTL_1 1
117 #define R300_PVS_CNTL_2 2
118 #define R300_PVS_CNTL_3 3
119 #define R300_PVS_CMDSIZE 4
120
121 #define R300_TXE_CMD_0 0
122 #define R300_TXE_ENABLE 1
123 #define R300_TXE_CMDSIZE 2
124
125 #define R300_RC_CMD_0 0
126 #define R300_RC_CNTL_0 1
127 #define R300_RC_CNTL_1 2
128 #define R300_RC_CMDSIZE 3
129
130 #define R300_RI_CMD_0 0
131 #define R300_RI_INTERP_0 1
132 #define R300_RI_INTERP_1 2
133 #define R300_RI_INTERP_2 3
134 #define R300_RI_INTERP_3 4
135 #define R300_RI_INTERP_4 5
136 #define R300_RI_INTERP_5 6
137 #define R300_RI_INTERP_6 7
138 #define R300_RI_INTERP_7 8
139 #define R300_RI_CMDSIZE 9
140
141 #define R300_RR_CMD_0 0 /* rr is variable size (at least 1) */
142 #define R300_RR_ROUTE_0 1
143 #define R300_RR_ROUTE_1 2
144 #define R300_RR_ROUTE_2 3
145 #define R300_RR_ROUTE_3 4
146 #define R300_RR_ROUTE_4 5
147 #define R300_RR_ROUTE_5 6
148 #define R300_RR_ROUTE_6 7
149 #define R300_RR_ROUTE_7 8
150 #define R300_RR_CMDSIZE 9
151
152 #define R300_FP_CMD_0 0
153 #define R300_FP_CNTL0 1
154 #define R300_FP_CNTL1 2
155 #define R300_FP_CNTL2 3
156 #define R300_FP_CMD_1 4
157 #define R300_FP_NODE0 5
158 #define R300_FP_NODE1 6
159 #define R300_FP_NODE2 7
160 #define R300_FP_NODE3 8
161 #define R300_FP_CMDSIZE 9
162
163 #define R300_FPI_CMD_0 0
164 #define R300_FPI_INSTR_0 1
165 #define R300_FPI_CMDSIZE 65
166
167 #define R300_AT_CMD_0 0
168 #define R300_AT_ALPHA_TEST 1
169 #define R300_AT_CMDSIZE 2
170
171 #define R300_BLD_CMD_0 0
172 #define R300_BLD_CBLEND 1
173 #define R300_BLD_ABLEND 2
174 #define R300_BLD_CMDSIZE 3
175
176 #define R300_CMK_CMD_0 0
177 #define R300_CMK_COLORMASK 1
178 #define R300_CMK_CMDSIZE 2
179
180 #define R300_CB_CMD_0 0
181 #define R300_CB_OFFSET 1
182 #define R300_CB_CMD_1 2
183 #define R300_CB_PITCH 3
184 #define R300_CB_CMDSIZE 4
185
186 #define R300_ZC_CMD_0 0
187 #define R300_ZC_CNTL_0 1
188 #define R300_ZC_CNTL_1 2
189 #define R300_ZC_CMDSIZE 3
190
191 #define R300_ZB_CMD_0 0
192 #define R300_ZB_OFFSET 1
193 #define R300_ZB_PITCH 2
194 #define R300_ZB_CMDSIZE 3
195
196 #define R300_VPI_CMD_0 0
197 #define R300_VPI_INSTR_0 1
198 #define R300_VPI_CMDSIZE 1025 /* 256 16 byte instructions */
199
200 #define R300_VPP_CMD_0 0
201 #define R300_VPP_PARAM_0 1
202 #define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */
203
204 /**
205 * Cache for hardware register state.
206 */
207 struct r300_hw_state {
208 struct r300_state_atom atomlist;
209
210 GLboolean is_dirty;
211 GLboolean all_dirty;
212 int max_state_size; /* in dwords */
213
214 struct r300_state_atom vpt; /* viewport (1D98) */
215 struct r300_state_atom unk2080; /* (2080) */
216 struct r300_state_atom ovf; /* output vertex format (2090) */
217 struct r300_state_atom unk20B0; /* (20B0) */
218 struct r300_state_atom unk2134; /* (2134) */
219 struct r300_state_atom unk2140; /* (2140) */
220 struct r300_state_atom vir[2]; /* vap input route (2150/21E0) */
221 struct r300_state_atom vic; /* vap input control (2180) */
222 struct r300_state_atom unk21DC; /* (21DC) */
223 struct r300_state_atom unk221C; /* (221C) */
224 struct r300_state_atom unk2220; /* (2220) */
225 struct r300_state_atom unk2288; /* (2288) */
226 struct r300_state_atom pvs; /* pvs_cntl (22D0) */
227 struct r300_state_atom unk4008; /* (4008) */
228 struct r300_state_atom unk4010; /* (4010) */
229 struct r300_state_atom txe; /* tex enable (4104) */
230 struct r300_state_atom unk4200; /* (4200) */
231 struct r300_state_atom unk4214; /* (4214) */
232 // what about UNKNOWN_421C? (see r300_reg.h)
233 struct r300_state_atom unk4230; /* (4230) */
234 struct r300_state_atom unk4260; /* (4260) */
235 struct r300_state_atom unk4274; /* (4274) */
236 struct r300_state_atom unk4288; /* (4288) */
237 struct r300_state_atom unk42A0; /* (42A0) */
238 struct r300_state_atom unk42B4; /* (42B4) */
239 struct r300_state_atom unk42C0; /* (42C0) */
240 struct r300_state_atom rc; /* rs control (4300) */
241 struct r300_state_atom ri; /* rs interpolators (4310) */
242 struct r300_state_atom rr; /* rs route (4330) */
243 struct r300_state_atom unk43A4; /* (43A4) */
244 struct r300_state_atom unk43E0; /* (43E0) */
245 struct r300_state_atom fp; /* fragment program cntl + nodes (4600) */
246 struct r300_state_atom unk46A4; /* (46A4) */
247 struct r300_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */
248 struct r300_state_atom unk4BC0; /* (4BC0) */
249 struct r300_state_atom unk4BC8; /* (4BC8) */
250 struct r300_state_atom at; /* alpha test (4BD4) */
251 struct r300_state_atom unk4BD8; /* (4BD8) */
252 struct r300_state_atom unk4E00; /* (4E00) */
253 struct r300_state_atom bld; /* blending (4E04) */
254 struct r300_state_atom cmk; /* colormask (4E0C) */
255 struct r300_state_atom unk4E10; /* (4E10) */
256 struct r300_state_atom cb; /* colorbuffer (4E28) */
257 struct r300_state_atom unk4E50; /* (4E50) */
258 struct r300_state_atom unk4E88; /* (4E88) */
259 struct r300_state_atom zc; /* z control (4F00) */
260 struct r300_state_atom unk4F08; /* (4F08) */
261 struct r300_state_atom zb; /* z buffer (4F20) */
262 struct r300_state_atom unk4F28; /* (4F28) */
263 struct r300_state_atom unk4F30; /* (4F30) */
264 struct r300_state_atom unk4F44; /* (4F44) */
265 struct r300_state_atom unk4F54; /* (4F54) */
266
267 struct r300_state_atom vpi; /* vp instructions */
268 struct r300_state_atom vpp; /* vp parameters */
269 };
270
271
272 /**
273 * This structure holds the command buffer while it is being constructed.
274 *
275 * The first batch of commands in the buffer is always the state that needs
276 * to be re-emitted when the context is lost. This batch can be skipped
277 * otherwise.
278 */
279 struct r300_cmdbuf {
280 int size; /* DWORDs allocated for buffer */
281 uint32_t* cmd_buf;
282 int count_used; /* DWORDs filled so far */
283 int count_reemit; /* size of re-emission batch */
284 };
285
286
287 /**
288 * State cache
289 */
290 struct r300_state {
291 };
292
293
294 /**
295 * R300 context structure.
296 */
297 struct r300_context {
298 struct radeon_context radeon; /* parent class, must be first */
299
300 struct r300_hw_state hw;
301 struct r300_cmdbuf cmdbuf;
302 struct r300_state state;
303 };
304
305 #define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx))
306
307 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
308 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
309 __DRIcontextPrivate * driContextPriv,
310 void *sharedContextPrivate);
311
312 #endif /* __R300_CONTEXT_H__ */