src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 #define USER_BUFFERS
  51 #define RADEON_VTXFMT_A
  52 #define HW_VBOS
  53
  54 /* We don't handle 16 bits elts swapping yet */
  55 #ifdef MESA_BIG_ENDIAN
  56 #define FORCE_32BITS_ELTS
  57 #endif
  58
  59 //#define OPTIMIZE_ELTS
  60 #define CB_DPATH
  61
  62 struct r300_context;
  63 typedef struct r300_context r300ContextRec;
  64 typedef struct r300_context *r300ContextPtr;
  65
  66 #include "radeon_lock.h"
  67 #include "mm.h"
  68
  69 /* Checkpoint.. for convenience */
  70 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  71 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  72    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  73    with other compilers ... GLUE!
  74 */
  75 #if 1
  76 #define WARN_ONCE(a, ...)       { \
  77         static int warn##__LINE__=1; \
  78         if(warn##__LINE__){ \
  79                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  80                 fprintf(stderr, "File %s function %s line %d\n", \
  81                         __FILE__, __FUNCTION__, __LINE__); \
  82                 fprintf(stderr,  a, ## __VA_ARGS__);\
  83                 fprintf(stderr, "***************************************************************************\n"); \
  84                 warn##__LINE__=0;\
  85                 } \
  86         }
  87 #else
  88 #define WARN_ONCE(a, ...) {}
  89 #endif
  90
  91   /* We should probably change types within vertex_shader
  92       and pixel_shader structure later on */
  93 #define CARD32 GLuint
  94 #include "vertex_shader.h"
  95 #include "r300_fragprog.h"
  96 #undef CARD32
  97
  98 static __inline__ uint32_t r300PackFloat32(float fl)
  99 {
 100         union { float fl; uint32_t u; } u;
 101
 102         u.fl = fl;
 103         return u.u;
 104 }
 105
 106
 107 /************ DMA BUFFERS **************/
 108
 109 /* Need refcounting on dma buffers:
 110  */
 111 struct r300_dma_buffer {
 112         int refcount;           /* the number of retained regions in buf */
 113         drmBufPtr buf;
 114         int id;
 115 };
 116 #undef GET_START
 117 #ifdef USER_BUFFERS
 118 #define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start))
 119 #else
 120 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 121                         (rvb)->address - rmesa->dma.buf0_address +      \
 122                         (rvb)->start)
 123 #endif
 124 /* A retained region, eg vertices for indexed vertices.
 125  */
 126 struct r300_dma_region {
 127         struct r300_dma_buffer *buf;
 128         char *address;          /* == buf->address */
 129         int start, end, ptr;    /* offsets from start of buf */
 130
 131     int aos_offset;     /* address in GART memory */
 132     int aos_stride;     /* distance between elements, in dwords */
 133     int aos_size;       /* number of components (1-4) */
 134     int aos_reg;        /* VAP register assignment */
 135 };
 136
 137 struct r300_dma {
 138         /* Active dma region.  Allocations for vertices and retained
 139          * regions come from here.  Also used for emitting random vertices,
 140          * these may be flushed by calling flush_current();
 141          */
 142         struct r300_dma_region current;
 143
 144         void (*flush) (r300ContextPtr);
 145
 146         char *buf0_address;     /* start of buf[0], for index calcs */
 147
 148         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 149          * for which a DISCARD command is currently queued in the command buffer.
 150          */
 151         GLuint nr_released_bufs;
 152 };
 153
 154        /* Texture related */
 155
 156 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 157
 158 /* Texture object in locally shared texture space.
 159  */
 160 struct r300_tex_obj {
 161         driTextureObject base;
 162
 163         GLuint bufAddr;         /* Offset to start of locally
 164                                    shared texture block */
 165
 166         GLuint dirty_state;     /* Flags (1 per texunit) for
 167                                    whether or not this texobj
 168                                    has dirty hardware state
 169                                    (pp_*) that needs to be
 170                                    brought into the
 171                                    texunit. */
 172
 173         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 174         /* Six, for the cube faces */
 175
 176
 177         GLuint pitch; /* this isn't sent to hardware just used in calculations */
 178         /* hardware register values */
 179         /* Note that R200 has 8 registers per texture and R300 only 7 */
 180         GLuint filter;
 181         GLuint pitch_reg;
 182         GLuint size;    /* npot only */
 183         GLuint format;
 184         GLuint offset;  /* Image location in the card's address space.
 185                                    All cube faces follow. */
 186         GLuint unknown4;
 187         GLuint unknown5;
 188         /* end hardware registers */
 189
 190         /* registers computed by r200 code - keep them here to
 191            compare against what is actually written.
 192
 193            to be removed later.. */
 194         GLuint pp_border_color;
 195         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 196         GLuint format_x;
 197
 198
 199         GLboolean border_fallback;
 200
 201         GLuint tile_bits; /* hw texture tile bits used on this texture */
 202 };
 203
 204 struct r300_texture_env_state {
 205         r300TexObjPtr texobj;
 206         GLenum format;
 207         GLenum envMode;
 208 };
 209
 210
 211 /* The blit width for texture uploads
 212  */
 213 #define R300_BLIT_WIDTH_BYTES 1024
 214 #define R300_MAX_TEXTURE_UNITS 8
 215
 216 struct r300_texture_state {
 217         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 218         int tc_count; /* number of incoming texture coordinates from VAP */
 219 };
 220
 221 /**
 222  * A block of hardware state.
 223  *
 224  * When check returns non-zero, the returned number of dwords must be
 225  * copied verbatim into the command buffer in order to update a state atom
 226  * when it is dirty.
 227  */
 228 struct r300_state_atom {
 229         struct r300_state_atom *next, *prev;
 230         const char* name;       /* for debug */
 231         int cmd_size;           /* maximum size in dwords */
 232         GLuint idx;             /* index in an array (e.g. textures) */
 233         uint32_t* cmd;
 234         GLboolean dirty;
 235
 236         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 237 };
 238
 239
 240 #define R300_VPT_CMD_0          0
 241 #define R300_VPT_XSCALE         1
 242 #define R300_VPT_XOFFSET        2
 243 #define R300_VPT_YSCALE         3
 244 #define R300_VPT_YOFFSET        4
 245 #define R300_VPT_ZSCALE         5
 246 #define R300_VPT_ZOFFSET        6
 247 #define R300_VPT_CMDSIZE        7
 248
 249 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 250 #define R300_VIR_CNTL_0         1
 251 #define R300_VIR_CNTL_1         2
 252 #define R300_VIR_CNTL_2         3
 253 #define R300_VIR_CNTL_3         4
 254 #define R300_VIR_CNTL_4         5
 255 #define R300_VIR_CNTL_5         6
 256 #define R300_VIR_CNTL_6         7
 257 #define R300_VIR_CNTL_7         8
 258 #define R300_VIR_CMDSIZE        9
 259
 260 #define R300_VIC_CMD_0          0
 261 #define R300_VIC_CNTL_0         1
 262 #define R300_VIC_CNTL_1         2
 263 #define R300_VIC_CMDSIZE        3
 264
 265 #define R300_VOF_CMD_0          0
 266 #define R300_VOF_CNTL_0         1
 267 #define R300_VOF_CNTL_1         2
 268 #define R300_VOF_CMDSIZE        3
 269
 270
 271 #define R300_PVS_CMD_0          0
 272 #define R300_PVS_CNTL_1         1
 273 #define R300_PVS_CNTL_2         2
 274 #define R300_PVS_CNTL_3         3
 275 #define R300_PVS_CMDSIZE        4
 276
 277 #define R300_GB_MISC_CMD_0              0
 278 #define R300_GB_MISC_MSPOS_0            1
 279 #define R300_GB_MISC_MSPOS_1            2
 280 #define R300_GB_MISC_TILE_CONFIG        3
 281 #define R300_GB_MISC_SELECT             4
 282 #define R300_GB_MISC_AA_CONFIG          5
 283 #define R300_GB_MISC_CMDSIZE            6
 284
 285 #define R300_TXE_CMD_0          0
 286 #define R300_TXE_ENABLE         1
 287 #define R300_TXE_CMDSIZE        2
 288
 289 #define R300_PS_CMD_0           0
 290 #define R300_PS_POINTSIZE       1
 291 #define R300_PS_CMDSIZE         2
 292
 293 #define R300_ZBS_CMD_0          0
 294 #define R300_ZBS_T_FACTOR       1
 295 #define R300_ZBS_T_CONSTANT     2
 296 #define R300_ZBS_W_FACTOR       3
 297 #define R300_ZBS_W_CONSTANT     4
 298 #define R300_ZBS_CMDSIZE        5
 299
 300 #define R300_CUL_CMD_0          0
 301 #define R300_CUL_CULL           1
 302 #define R300_CUL_CMDSIZE        2
 303
 304 #define R300_RC_CMD_0           0
 305 #define R300_RC_CNTL_0          1
 306 #define R300_RC_CNTL_1          2
 307 #define R300_RC_CMDSIZE         3
 308
 309 #define R300_RI_CMD_0           0
 310 #define R300_RI_INTERP_0        1
 311 #define R300_RI_INTERP_1        2
 312 #define R300_RI_INTERP_2        3
 313 #define R300_RI_INTERP_3        4
 314 #define R300_RI_INTERP_4        5
 315 #define R300_RI_INTERP_5        6
 316 #define R300_RI_INTERP_6        7
 317 #define R300_RI_INTERP_7        8
 318 #define R300_RI_CMDSIZE         9
 319
 320 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 321 #define R300_RR_ROUTE_0         1
 322 #define R300_RR_ROUTE_1         2
 323 #define R300_RR_ROUTE_2         3
 324 #define R300_RR_ROUTE_3         4
 325 #define R300_RR_ROUTE_4         5
 326 #define R300_RR_ROUTE_5         6
 327 #define R300_RR_ROUTE_6         7
 328 #define R300_RR_ROUTE_7         8
 329 #define R300_RR_CMDSIZE         9
 330
 331 #define R300_FP_CMD_0           0
 332 #define R300_FP_CNTL0           1
 333 #define R300_FP_CNTL1           2
 334 #define R300_FP_CNTL2           3
 335 #define R300_FP_CMD_1           4
 336 #define R300_FP_NODE0           5
 337 #define R300_FP_NODE1           6
 338 #define R300_FP_NODE2           7
 339 #define R300_FP_NODE3           8
 340 #define R300_FP_CMDSIZE         9
 341
 342 #define R300_FPT_CMD_0          0
 343 #define R300_FPT_INSTR_0        1
 344 #define R300_FPT_CMDSIZE        65
 345
 346 #define R300_FPI_CMD_0          0
 347 #define R300_FPI_INSTR_0        1
 348 #define R300_FPI_CMDSIZE        65
 349
 350 #define R300_FPP_CMD_0          0
 351 #define R300_FPP_PARAM_0        1
 352 #define R300_FPP_CMDSIZE        (32*4+1)
 353
 354 #define R300_FOGS_CMD_0         0
 355 #define R300_FOGS_STATE         1
 356 #define R300_FOGS_CMDSIZE       2
 357
 358 #define R300_FOGC_CMD_0         0
 359 #define R300_FOGC_R             1
 360 #define R300_FOGC_G             2
 361 #define R300_FOGC_B             3
 362 #define R300_FOGC_CMDSIZE       4
 363
 364 #define R300_FOGP_CMD_0         0
 365 #define R300_FOGP_SCALE         1
 366 #define R300_FOGP_START         2
 367 #define R300_FOGP_CMDSIZE       3
 368
 369 #define R300_AT_CMD_0           0
 370 #define R300_AT_ALPHA_TEST      1
 371 #define R300_AT_UNKNOWN         2
 372 #define R300_AT_CMDSIZE         3
 373
 374 #define R300_BLD_CMD_0          0
 375 #define R300_BLD_CBLEND         1
 376 #define R300_BLD_ABLEND         2
 377 #define R300_BLD_CMDSIZE        3
 378
 379 #define R300_CMK_CMD_0          0
 380 #define R300_CMK_COLORMASK      1
 381 #define R300_CMK_CMDSIZE        2
 382
 383 #define R300_CB_CMD_0           0
 384 #define R300_CB_OFFSET          1
 385 #define R300_CB_CMD_1           2
 386 #define R300_CB_PITCH           3
 387 #define R300_CB_CMDSIZE         4
 388
 389 #define R300_ZS_CMD_0           0
 390 #define R300_ZS_CNTL_0          1
 391 #define R300_ZS_CNTL_1          2
 392 #define R300_ZS_CNTL_2          3
 393 #define R300_ZS_CMDSIZE         4
 394
 395 #define R300_ZB_CMD_0           0
 396 #define R300_ZB_OFFSET          1
 397 #define R300_ZB_PITCH           2
 398 #define R300_ZB_CMDSIZE         3
 399
 400 #define R300_VPI_CMD_0          0
 401 #define R300_VPI_INSTR_0        1
 402 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 403
 404 #define R300_VPP_CMD_0          0
 405 #define R300_VPP_PARAM_0        1
 406 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 407
 408 #define R300_VPS_CMD_0          0
 409 #define R300_VPS_ZERO_0         1
 410 #define R300_VPS_ZERO_1         2
 411 #define R300_VPS_POINTSIZE      3
 412 #define R300_VPS_ZERO_3         4
 413 #define R300_VPS_CMDSIZE        5
 414
 415         /* the layout is common for all fields inside tex */
 416 #define R300_TEX_CMD_0          0
 417 #define R300_TEX_VALUE_0        1
 418 /* We don't really use this, instead specify mtu+1 dynamically
 419 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 420 */
 421
 422 /**
 423  * Cache for hardware register state.
 424  */
 425 struct r300_hw_state {
 426         struct r300_state_atom atomlist;
 427
 428         GLboolean       is_dirty;
 429         GLboolean       all_dirty;
 430         int             max_state_size; /* in dwords */
 431
 432         struct r300_state_atom vpt;     /* viewport (1D98) */
 433         struct r300_state_atom unk2080; /* (2080) */
 434         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 435         struct r300_state_atom vte;     /* (20B0) */
 436         struct r300_state_atom unk2134; /* (2134) */
 437         struct r300_state_atom unk2140; /* (2140) */
 438         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 439         struct r300_state_atom vic;     /* vap input control (2180) */
 440         struct r300_state_atom unk21DC; /* (21DC) */
 441         struct r300_state_atom unk221C; /* (221C) */
 442         struct r300_state_atom unk2220; /* (2220) */
 443         struct r300_state_atom unk2288; /* (2288) */
 444         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 445         struct r300_state_atom gb_enable; /* (4008) */
 446         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 447         struct r300_state_atom unk4200; /* (4200) */
 448         struct r300_state_atom unk4214; /* (4214) */
 449         struct r300_state_atom ps;      /* pointsize (421C) */
 450         struct r300_state_atom unk4230; /* (4230) */
 451         struct r300_state_atom lcntl;   /* line control */
 452         struct r300_state_atom unk4260; /* (4260) */
 453         struct r300_state_atom unk4274; /* (4274) */
 454         struct r300_state_atom unk4288; /* (4288) */
 455         struct r300_state_atom fogp;    /* fog parameters (4294) */
 456         struct r300_state_atom unk429C; /* (429C) */
 457         struct r300_state_atom unk42A0; /* (42A0) */
 458         struct r300_state_atom zbs;     /* zbias (42A4) */
 459         struct r300_state_atom unk42B4; /* (42B4) */
 460         struct r300_state_atom cul;     /* cull cntl (42B8) */
 461         struct r300_state_atom unk42C0; /* (42C0) */
 462         struct r300_state_atom rc;      /* rs control (4300) */
 463         struct r300_state_atom ri;      /* rs interpolators (4310) */
 464         struct r300_state_atom rr;      /* rs route (4330) */
 465         struct r300_state_atom unk43A4; /* (43A4) */
 466         struct r300_state_atom unk43E8; /* (43E8) */
 467         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 468         struct r300_state_atom fpt;     /* texi - (4620) */
 469         struct r300_state_atom unk46A4; /* (46A4) */
 470         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 471         struct r300_state_atom fogs;    /* fog state (4BC0) */
 472         struct r300_state_atom fogc;    /* fog color (4BC8) */
 473         struct r300_state_atom at;      /* alpha test (4BD4) */
 474         struct r300_state_atom unk4BD8; /* (4BD8) */
 475         struct r300_state_atom fpp;     /* 0x4C00 and following */
 476         struct r300_state_atom unk4E00; /* (4E00) */
 477         struct r300_state_atom bld;     /* blending (4E04) */
 478         struct r300_state_atom cmk;     /* colormask (4E0C) */
 479         struct r300_state_atom unk4E10; /* constant blend color + ??? (4E10) */
 480         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 481         struct r300_state_atom unk4E50; /* (4E50) */
 482         struct r300_state_atom unk4E88; /* (4E88) */
 483         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 484         struct r300_state_atom zs;      /* zstencil control (4F00) */
 485         struct r300_state_atom unk4F10; /* (4F10) */
 486         struct r300_state_atom zb;      /* z buffer (4F20) */
 487         struct r300_state_atom unk4F28; /* (4F28) */
 488         struct r300_state_atom unk4F30; /* (4F30) */
 489         struct r300_state_atom unk4F44; /* (4F44) */
 490         struct r300_state_atom unk4F54; /* (4F54) */
 491
 492         struct r300_state_atom vpi;     /* vp instructions */
 493         struct r300_state_atom vpp;     /* vp parameters */
 494         struct r300_state_atom vps;     /* vertex point size (?) */
 495                 /* 8 texture units */
 496                 /* the state is grouped by function and not by
 497                    texture unit. This makes single unit updates
 498                    really awkward - we are much better off
 499                    updating the whole thing at once */
 500         struct {
 501                 struct r300_state_atom filter;
 502                 struct r300_state_atom unknown1;
 503                 struct r300_state_atom size;
 504                 struct r300_state_atom format;
 505                 struct r300_state_atom pitch;
 506                 struct r300_state_atom offset;
 507                 struct r300_state_atom unknown4;
 508                 struct r300_state_atom border_color;
 509                 } tex;
 510         struct r300_state_atom txe;     /* tex enable (4104) */
 511 };
 512
 513
 514 /**
 515  * This structure holds the command buffer while it is being constructed.
 516  *
 517  * The first batch of commands in the buffer is always the state that needs
 518  * to be re-emitted when the context is lost. This batch can be skipped
 519  * otherwise.
 520  */
 521 struct r300_cmdbuf {
 522         int             size;           /* DWORDs allocated for buffer */
 523         uint32_t*       cmd_buf;
 524         int             count_used;     /* DWORDs filled so far */
 525         int             count_reemit;   /* size of re-emission batch */
 526 };
 527
 528
 529 /**
 530  * State cache
 531  */
 532
 533 struct r300_depthbuffer_state {
 534         GLfloat scale;
 535 };
 536
 537 struct r300_stencilbuffer_state {
 538         GLuint clear;
 539         GLboolean hw_stencil;
 540
 541 };
 542
 543 /* Vertex shader state */
 544
 545 /* Perhaps more if we store programs in vmem? */
 546 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 547 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 548
 549 /* Can be tested with colormat currently. */
 550 #define VSF_MAX_FRAGMENT_TEMPS (14)
 551
 552 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 553
 554 struct r300_vertex_shader_fragment {
 555         int length;
 556         union {
 557                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 558                 float f[VSF_MAX_FRAGMENT_LENGTH];
 559                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH/4];
 560                 } body;
 561         };
 562
 563 #define VSF_DEST_PROGRAM        0x0
 564 #define VSF_DEST_MATRIX0        0x200
 565 #define VSF_DEST_MATRIX1        0x204
 566 #define VSF_DEST_MATRIX2        0x208
 567 #define VSF_DEST_VECTOR0        0x20c
 568 #define VSF_DEST_VECTOR1        0x20d
 569 #define VSF_DEST_UNKNOWN1       0x400
 570 #define VSF_DEST_UNKNOWN2       0x406
 571
 572 struct r300_vertex_shader_state {
 573         struct r300_vertex_shader_fragment program;
 574
 575         /* a bit of a waste - each uses only a subset of allocated space..
 576             but easier to program */
 577         struct r300_vertex_shader_fragment matrix[3];
 578         struct r300_vertex_shader_fragment vector[2];
 579
 580         struct r300_vertex_shader_fragment unknown1;
 581         struct r300_vertex_shader_fragment unknown2;
 582
 583         int program_start;
 584         int unknown_ptr1;  /* pointer within program space */
 585         int program_end;
 586
 587         int param_offset;
 588         int param_count;
 589
 590         int unknown_ptr2;  /* pointer within program space */
 591         int unknown_ptr3;  /* pointer within program space */
 592         };
 593
 594 extern int hw_tcl_on;
 595
 596 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 597 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 598
 599 /* Should but doesnt work */
 600 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 601
 602 //#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && (OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit)))) :
 603 //      (r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit))))
 604 //#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit))) :
 605 //      ctx->Texture.Unit[unit]._ReallyEnabled && r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit)))
 606
 607 #define TMU_ENABLED(ctx, unit) (ctx->Texture.Unit[unit]._ReallyEnabled)
 608
 609 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 610  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 611  */
 612
 613 struct r300_vertex_program_key {
 614         GLuint InputsRead;
 615         GLuint OutputsWritten;
 616 };
 617
 618 struct r300_vertex_program {
 619         struct r300_vertex_program *next;
 620         struct r300_vertex_program_key key;
 621         int translated;
 622
 623         struct r300_vertex_shader_fragment program;
 624
 625         int pos_end;
 626         int num_temporaries; /* Number of temp vars used by program */
 627         int wpos_idx;
 628         int inputs[VERT_ATTRIB_MAX];
 629         int outputs[VERT_RESULT_MAX];
 630         int native;
 631         int ref_count;
 632         int use_ref_count;
 633 };
 634
 635 struct r300_vertex_program_cont {
 636         struct gl_vertex_program mesa_program; /* Must be first */
 637         struct r300_vertex_shader_fragment params;
 638         struct r300_vertex_program *progs;
 639 };
 640
 641 #define PFS_MAX_ALU_INST        64
 642 #define PFS_MAX_TEX_INST        64
 643 #define PFS_MAX_TEX_INDIRECT 4
 644 #define PFS_NUM_TEMP_REGS       32
 645 #define PFS_NUM_CONST_REGS      16
 646
 647 /* Tracking data for Mesa registers */
 648 struct reg_acc {
 649        int reg;        /* Assigned hw temp */
 650        unsigned int refcount; /* Number of uses by mesa program */
 651 };
 652
 653 struct r300_pfs_compile_state {
 654        int v_pos, s_pos;       /* highest ALU slots used */
 655
 656        /* Track some information gathered during opcode
 657         * construction.
 658         *
 659         * NOTE: Data is only set by the code, and isn't used yet.
 660         */
 661        struct {
 662                int vsrc[3];
 663                int ssrc[3];
 664                int umask;
 665        } slot[PFS_MAX_ALU_INST];
 666
 667        /* Used to map Mesa's inputs/temps onto hardware temps */
 668        int temp_in_use;
 669        struct reg_acc temps[PFS_NUM_TEMP_REGS];
 670        struct reg_acc inputs[32]; /* don't actually need 32... */
 671
 672        /* Track usage of hardware temps, for register allocation,
 673         * indirection detection, etc. */
 674        int hwreg_in_use;
 675        GLuint used_in_node;
 676        GLuint dest_in_node;
 677 };
 678
 679 struct r300_fragment_program {
 680         struct gl_fragment_program mesa_program;
 681
 682         GLcontext *ctx;
 683         GLboolean translated;
 684         GLboolean error;
 685         struct r300_pfs_compile_state *cs;
 686
 687         struct {
 688                 int length;
 689                 GLuint inst[PFS_MAX_TEX_INST];
 690         } tex;
 691
 692         struct {
 693                 struct {
 694                         GLuint inst0;
 695                         GLuint inst1;
 696                         GLuint inst2;
 697                         GLuint inst3;
 698                 } inst[PFS_MAX_ALU_INST];
 699         } alu;
 700
 701         struct {
 702                 int tex_offset;
 703                 int tex_end;
 704                 int alu_offset;
 705                 int alu_end;
 706                 int flags;
 707         } node[4];
 708         int cur_node;
 709         int first_node_has_tex;
 710
 711         int alu_offset;
 712         int alu_end;
 713         int tex_offset;
 714         int tex_end;
 715
 716         /* Hardware constants */
 717         GLfloat constant[PFS_NUM_CONST_REGS][4];
 718         int const_nr;
 719
 720         /* Tracked parameters */
 721         struct {
 722                 int idx;                        /* hardware index */
 723                 GLfloat *values;        /* pointer to values */
 724         } param[PFS_NUM_CONST_REGS];
 725         int param_nr;
 726         GLboolean params_uptodate;
 727
 728         int max_temp_idx;
 729 };
 730
 731 #define R300_MAX_AOS_ARRAYS             16
 732
 733 #define AOS_FORMAT_USHORT       0
 734 #define AOS_FORMAT_FLOAT        1
 735 #define AOS_FORMAT_UBYTE        2
 736 #define AOS_FORMAT_FLOAT_COLOR  3
 737
 738 #define REG_COORDS      0
 739 #define REG_COLOR0      1
 740 #define REG_TEX0        2
 741
 742 struct dt {
 743         GLint size;
 744         GLenum type;
 745         GLsizei stride;
 746         void *data;
 747 };
 748
 749 struct radeon_vertex_buffer {
 750         int Count;
 751         void *Elts;
 752         int elt_size;
 753         int elt_min, elt_max; /* debug */
 754
 755         struct dt AttribPtr[VERT_ATTRIB_MAX];
 756
 757         struct tnl_prim  *Primitive;
 758         GLuint      PrimitiveCount;
 759         GLint LockFirst;
 760         GLsizei LockCount;
 761         int lock_uptodate;
 762 };
 763
 764 struct r300_aos_rec {
 765         GLuint offset;
 766         int element_size; /* in dwords */
 767         int stride;       /* distance between elements, in dwords */
 768
 769         int format;
 770
 771         int ncomponents; /* number of components - between 1 and 4, inclusive */
 772
 773         int reg; /* which register they are assigned to. */
 774
 775         };
 776
 777 struct r300_state {
 778         struct r300_depthbuffer_state depth;
 779         struct r300_texture_state texture;
 780         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 781         struct r300_vertex_shader_state vertex_shader;
 782         struct r300_pfs_compile_state pfs_compile;
 783         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 784         int aos_count;
 785         struct radeon_vertex_buffer VB;
 786
 787         GLuint *Elts;
 788         struct r300_dma_region elt_dma;
 789
 790         DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for.
 791                                  They are the same as tnl->render_inputs for fixed pipeline */
 792
 793         struct {
 794                 int transform_offset;  /* Transform matrix offset, -1 if none */
 795                 } vap_param;  /* vertex processor parameter allocation - tells where to write parameters */
 796
 797         struct r300_stencilbuffer_state stencil;
 798
 799 };
 800
 801 #define R300_FALLBACK_NONE 0
 802 #define R300_FALLBACK_TCL 1
 803 #define R300_FALLBACK_RAST 2
 804
 805 /**
 806  * R300 context structure.
 807  */
 808 struct r300_context {
 809         struct radeon_context radeon; /* parent class, must be first */
 810
 811         struct r300_hw_state hw;
 812         struct r300_cmdbuf cmdbuf;
 813         struct r300_state state;
 814         struct gl_vertex_program *curr_vp;
 815         struct r300_vertex_program *selected_vp;
 816
 817         /* Vertex buffers
 818          */
 819         struct r300_dma dma;
 820         GLboolean save_on_next_unlock;
 821         GLuint NewGLState;
 822
 823         /* Texture object bookkeeping
 824          */
 825         unsigned nr_heaps;
 826         driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
 827         driTextureObject swapped;
 828         int texture_depth;
 829         float initialMaxAnisotropy;
 830
 831         /* Clientdata textures;
 832          */
 833         GLuint prefer_gart_client_texturing;
 834
 835 #ifdef USER_BUFFERS
 836         struct radeon_memory_manager *rmm;
 837         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 838         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 839 #endif
 840
 841         GLboolean texmicrotile;
 842         GLboolean span_dlocking;
 843         GLboolean disable_lowimpact_fallback;
 844 };
 845
 846 struct r300_buffer_object {
 847         struct gl_buffer_object mesa_obj;
 848         int id;
 849 };
 850
 851 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 852
 853 static __inline GLuint r300PackColor( GLuint cpp,
 854                                         GLubyte r, GLubyte g,
 855                                         GLubyte b, GLubyte a )
 856 {
 857    switch ( cpp ) {
 858    case 2:
 859       return PACK_COLOR_565( r, g, b );
 860    case 4:
 861       return PACK_COLOR_8888( r, g, b, a );
 862    default:
 863       return 0;
 864    }
 865 }
 866 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 867 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 868                                    __DRIcontextPrivate * driContextPriv,
 869                                    void *sharedContextPrivate);
 870
 871 extern int r300_get_num_verts(r300ContextPtr rmesa, int num_verts, int prim);
 872
 873 extern void r300_select_vertex_shader(r300ContextPtr r300);
 874 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 875 extern int r300VertexProgUpdateParams(GLcontext *ctx, struct r300_vertex_program_cont *vp, float *dst);
 876 extern int r300Fallback(GLcontext *ctx);
 877
 878 extern void radeon_vb_to_rvb(r300ContextPtr rmesa, struct radeon_vertex_buffer *rvb, struct vertex_buffer *vb);
 879 extern GLboolean r300_run_vb_render(GLcontext *ctx, struct tnl_pipeline_stage *stage);
 880
 881 #ifdef RADEON_VTXFMT_A
 882 extern void radeon_init_vtxfmt_a(r300ContextPtr rmesa);
 883 #endif
 884
 885 #ifdef HW_VBOS
 886 extern void r300_init_vbo_funcs(struct dd_function_table *functions);
 887 extern void r300_evict_vbos(GLcontext *ctx, int amount);
 888 #endif
 889
 890 #define RADEON_D_CAPTURE 0
 891 #define RADEON_D_PLAYBACK 1
 892 #define RADEON_D_PLAYBACK_RAW 2
 893 #define RADEON_D_T 3
 894
 895 #endif                          /* __R300_CONTEXT_H__ */