src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45 #include "radeon_bo.h"
  46
  47 #include "main/macros.h"
  48 #include "main/mtypes.h"
  49 #include "main/colormac.h"
  50
  51 struct r300_context;
  52 typedef struct r300_context r300ContextRec;
  53 typedef struct r300_context *r300ContextPtr;
  54
  55 #include "radeon_lock.h"
  56 #include "main/mm.h"
  57
  58 /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  59    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  60    with other compilers ... GLUE!
  61 */
  62 #define WARN_ONCE(a, ...)       { \
  63         static int warn##__LINE__=1; \
  64         if(warn##__LINE__){ \
  65                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  66                 fprintf(stderr, "File %s function %s line %d\n", \
  67                         __FILE__, __FUNCTION__, __LINE__); \
  68                 fprintf(stderr,  a, ## __VA_ARGS__);\
  69                 fprintf(stderr, "***************************************************************************\n"); \
  70                 warn##__LINE__=0;\
  71                 } \
  72         }
  73
  74 #include "r300_vertprog.h"
  75 #include "r500_fragprog.h"
  76
  77 /**
  78  * This function takes a float and packs it into a uint32_t
  79  */
  80 static INLINE uint32_t r300PackFloat32(float fl)
  81 {
  82         union {
  83                 float fl;
  84                 uint32_t u;
  85         } u;
  86
  87         u.fl = fl;
  88         return u.u;
  89 }
  90
  91 /* This is probably wrong for some values, I need to test this
  92  * some more.  Range checking would be a good idea also..
  93  *
  94  * But it works for most things.  I'll fix it later if someone
  95  * else with a better clue doesn't
  96  */
  97 static INLINE uint32_t r300PackFloat24(float f)
  98 {
  99         float mantissa;
 100         int exponent;
 101         uint32_t float24 = 0;
 102
 103         if (f == 0.0)
 104                 return 0;
 105
 106         mantissa = frexpf(f, &exponent);
 107
 108         /* Handle -ve */
 109         if (mantissa < 0) {
 110                 float24 |= (1 << 23);
 111                 mantissa = mantissa * -1.0;
 112         }
 113         /* Handle exponent, bias of 63 */
 114         exponent += 62;
 115         float24 |= (exponent << 16);
 116         /* Kill 7 LSB of mantissa */
 117         float24 |= (r300PackFloat32(mantissa) & 0x7FFFFF) >> 7;
 118
 119         return float24;
 120 }
 121
 122 /************ DMA BUFFERS **************/
 123
 124
 125 /* Texture related */
 126 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 127 typedef struct _r300_texture_image r300_texture_image;
 128
 129
 130 struct _r300_texture_image {
 131         struct gl_texture_image base;
 132
 133         /**
 134          * If mt != 0, the image is stored in hardware format in the
 135          * given mipmap tree. In this case, base.Data may point into the
 136          * mapping of the buffer object that contains the mipmap tree.
 137          *
 138          * If mt == 0, the image is stored in normal memory pointed to
 139          * by base.Data.
 140          */
 141         struct _r300_mipmap_tree *mt;
 142     struct radeon_bo *bo;
 143
 144         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 145         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 146 };
 147
 148 static INLINE r300_texture_image *get_r300_texture_image(struct gl_texture_image *image)
 149 {
 150         return (r300_texture_image*)image;
 151 }
 152
 153
 154 /* Texture object in locally shared texture space.
 155  */
 156 struct r300_tex_obj {
 157         struct gl_texture_object base;
 158         struct _r300_mipmap_tree *mt;
 159
 160         /**
 161          * This is true if we've verified that the mipmap tree above is complete
 162          * and so on.
 163          */
 164         GLboolean validated;
 165
 166         GLboolean image_override;       /* Image overridden by GLX_EXT_tfp */
 167         GLuint override_offset;
 168
 169         /* hardware register values */
 170         /* Note that R200 has 8 registers per texture and R300 only 7 */
 171         GLuint filter;
 172         GLuint filter_1;
 173         GLuint pitch_reg;
 174         GLuint size;            /* npot only */
 175         GLuint format;
 176         GLuint pp_border_color;
 177         /* end hardware registers */
 178
 179         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 180     struct radeon_bo *bo;
 181 };
 182
 183 static INLINE r300TexObj* r300_tex_obj(struct gl_texture_object *texObj)
 184 {
 185         return (r300TexObj*)texObj;
 186 }
 187
 188 /* The blit width for texture uploads
 189  */
 190 #define R300_BLIT_WIDTH_BYTES 1024
 191 #define R300_MAX_TEXTURE_UNITS 8
 192
 193 struct r300_texture_state {
 194         int tc_count;           /* number of incoming texture coordinates from VAP */
 195 };
 196
 197
 198 #define R300_VPT_CMD_0          0
 199 #define R300_VPT_XSCALE         1
 200 #define R300_VPT_XOFFSET        2
 201 #define R300_VPT_YSCALE         3
 202 #define R300_VPT_YOFFSET        4
 203 #define R300_VPT_ZSCALE         5
 204 #define R300_VPT_ZOFFSET        6
 205 #define R300_VPT_CMDSIZE        7
 206
 207 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
 208 #define R300_VIR_CNTL_0         1
 209 #define R300_VIR_CNTL_1         2
 210 #define R300_VIR_CNTL_2         3
 211 #define R300_VIR_CNTL_3         4
 212 #define R300_VIR_CNTL_4         5
 213 #define R300_VIR_CNTL_5         6
 214 #define R300_VIR_CNTL_6         7
 215 #define R300_VIR_CNTL_7         8
 216 #define R300_VIR_CMDSIZE        9
 217
 218 #define R300_VIC_CMD_0          0
 219 #define R300_VIC_CNTL_0         1
 220 #define R300_VIC_CNTL_1         2
 221 #define R300_VIC_CMDSIZE        3
 222
 223 #define R300_VOF_CMD_0          0
 224 #define R300_VOF_CNTL_0         1
 225 #define R300_VOF_CNTL_1         2
 226 #define R300_VOF_CMDSIZE        3
 227
 228 #define R300_PVS_CMD_0          0
 229 #define R300_PVS_CNTL_1         1
 230 #define R300_PVS_CNTL_2         2
 231 #define R300_PVS_CNTL_3         3
 232 #define R300_PVS_CMDSIZE        4
 233
 234 #define R300_GB_MISC_CMD_0              0
 235 #define R300_GB_MISC_MSPOS_0            1
 236 #define R300_GB_MISC_MSPOS_1            2
 237 #define R300_GB_MISC_TILE_CONFIG        3
 238 #define R300_GB_MISC_SELECT             4
 239 #define R300_GB_MISC_AA_CONFIG          5
 240 #define R300_GB_MISC_CMDSIZE            6
 241
 242 #define R300_TXE_CMD_0          0
 243 #define R300_TXE_ENABLE         1
 244 #define R300_TXE_CMDSIZE        2
 245
 246 #define R300_PS_CMD_0           0
 247 #define R300_PS_POINTSIZE       1
 248 #define R300_PS_CMDSIZE         2
 249
 250 #define R300_ZBS_CMD_0          0
 251 #define R300_ZBS_T_FACTOR       1
 252 #define R300_ZBS_T_CONSTANT     2
 253 #define R300_ZBS_W_FACTOR       3
 254 #define R300_ZBS_W_CONSTANT     4
 255 #define R300_ZBS_CMDSIZE        5
 256
 257 #define R300_CUL_CMD_0          0
 258 #define R300_CUL_CULL           1
 259 #define R300_CUL_CMDSIZE        2
 260
 261 #define R300_RC_CMD_0           0
 262 #define R300_RC_CNTL_0          1
 263 #define R300_RC_CNTL_1          2
 264 #define R300_RC_CMDSIZE         3
 265
 266 #define R300_RI_CMD_0           0
 267 #define R300_RI_INTERP_0        1
 268 #define R300_RI_INTERP_1        2
 269 #define R300_RI_INTERP_2        3
 270 #define R300_RI_INTERP_3        4
 271 #define R300_RI_INTERP_4        5
 272 #define R300_RI_INTERP_5        6
 273 #define R300_RI_INTERP_6        7
 274 #define R300_RI_INTERP_7        8
 275 #define R300_RI_CMDSIZE         9
 276
 277 #define R500_RI_CMDSIZE        17
 278
 279 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 280 #define R300_RR_INST_0          1
 281 #define R300_RR_INST_1          2
 282 #define R300_RR_INST_2          3
 283 #define R300_RR_INST_3          4
 284 #define R300_RR_INST_4          5
 285 #define R300_RR_INST_5          6
 286 #define R300_RR_INST_6          7
 287 #define R300_RR_INST_7          8
 288 #define R300_RR_CMDSIZE         9
 289
 290 #define R300_FP_CMD_0           0
 291 #define R300_FP_CNTL0           1
 292 #define R300_FP_CNTL1           2
 293 #define R300_FP_CNTL2           3
 294 #define R300_FP_CMD_1           4
 295 #define R300_FP_NODE0           5
 296 #define R300_FP_NODE1           6
 297 #define R300_FP_NODE2           7
 298 #define R300_FP_NODE3           8
 299 #define R300_FP_CMDSIZE         9
 300
 301 #define R500_FP_CMD_0           0
 302 #define R500_FP_CNTL            1
 303 #define R500_FP_PIXSIZE         2
 304 #define R500_FP_CMD_1           3
 305 #define R500_FP_CODE_ADDR       4
 306 #define R500_FP_CODE_RANGE      5
 307 #define R500_FP_CODE_OFFSET     6
 308 #define R500_FP_CMD_2           7
 309 #define R500_FP_FC_CNTL         8
 310 #define R500_FP_CMDSIZE         9
 311
 312 #define R300_FPT_CMD_0          0
 313 #define R300_FPT_INSTR_0        1
 314 #define R300_FPT_CMDSIZE        65
 315
 316 #define R300_FPI_CMD_0          0
 317 #define R300_FPI_INSTR_0        1
 318 #define R300_FPI_CMDSIZE        65
 319 /* R500 has space for 512 instructions - 6 dwords per instruction */
 320 #define R500_FPI_CMDSIZE        (512*6+1)
 321
 322 #define R300_FPP_CMD_0          0
 323 #define R300_FPP_PARAM_0        1
 324 #define R300_FPP_CMDSIZE        (32*4+1)
 325 /* R500 has spcae for 256 constants - 4 dwords per constant */
 326 #define R500_FPP_CMDSIZE        (256*4+1)
 327
 328 #define R300_FOGS_CMD_0         0
 329 #define R300_FOGS_STATE         1
 330 #define R300_FOGS_CMDSIZE       2
 331
 332 #define R300_FOGC_CMD_0         0
 333 #define R300_FOGC_R             1
 334 #define R300_FOGC_G             2
 335 #define R300_FOGC_B             3
 336 #define R300_FOGC_CMDSIZE       4
 337
 338 #define R300_FOGP_CMD_0         0
 339 #define R300_FOGP_SCALE         1
 340 #define R300_FOGP_START         2
 341 #define R300_FOGP_CMDSIZE       3
 342
 343 #define R300_AT_CMD_0           0
 344 #define R300_AT_ALPHA_TEST      1
 345 #define R300_AT_UNKNOWN         2
 346 #define R300_AT_CMDSIZE         3
 347
 348 #define R300_BLD_CMD_0          0
 349 #define R300_BLD_CBLEND         1
 350 #define R300_BLD_ABLEND         2
 351 #define R300_BLD_CMDSIZE        3
 352
 353 #define R300_CMK_CMD_0          0
 354 #define R300_CMK_COLORMASK      1
 355 #define R300_CMK_CMDSIZE        2
 356
 357 #define R300_CB_CMD_0           0
 358 #define R300_CB_OFFSET          1
 359 #define R300_CB_CMD_1           2
 360 #define R300_CB_PITCH           3
 361 #define R300_CB_CMDSIZE         4
 362
 363 #define R300_ZS_CMD_0           0
 364 #define R300_ZS_CNTL_0          1
 365 #define R300_ZS_CNTL_1          2
 366 #define R300_ZS_CNTL_2          3
 367 #define R300_ZS_CMDSIZE         4
 368
 369 #define R300_ZB_CMD_0           0
 370 #define R300_ZB_OFFSET          1
 371 #define R300_ZB_PITCH           2
 372 #define R300_ZB_CMDSIZE         3
 373
 374 #define R300_VAP_CNTL_FLUSH     0
 375 #define R300_VAP_CNTL_FLUSH_1   1
 376 #define R300_VAP_CNTL_CMD       2
 377 #define R300_VAP_CNTL_INSTR     3
 378 #define R300_VAP_CNTL_SIZE      4
 379
 380 #define R300_VPI_CMD_0          0
 381 #define R300_VPI_INSTR_0        1
 382 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 383
 384 #define R300_VPP_CMD_0          0
 385 #define R300_VPP_PARAM_0        1
 386 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 387
 388 #define R300_VPUCP_CMD_0                0
 389 #define R300_VPUCP_X            1
 390 #define R300_VPUCP_Y            2
 391 #define R300_VPUCP_Z            3
 392 #define R300_VPUCP_W            4
 393 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 394
 395 #define R300_VPS_CMD_0          0
 396 #define R300_VPS_ZERO_0         1
 397 #define R300_VPS_ZERO_1         2
 398 #define R300_VPS_POINTSIZE      3
 399 #define R300_VPS_ZERO_3         4
 400 #define R300_VPS_CMDSIZE        5
 401
 402         /* the layout is common for all fields inside tex */
 403 #define R300_TEX_CMD_0          0
 404 #define R300_TEX_VALUE_0        1
 405 /* We don't really use this, instead specify mtu+1 dynamically
 406 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 407 */
 408
 409 /**
 410  * Cache for hardware register state.
 411  */
 412 struct r300_hw_state {
 413         struct radeon_state_atom atomlist;
 414
 415         GLboolean is_dirty;
 416         GLboolean all_dirty;
 417         int max_state_size;     /* in dwords */
 418
 419         struct radeon_state_atom vpt;   /* viewport (1D98) */
 420         struct radeon_state_atom vap_cntl;
 421         struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
 422         struct radeon_state_atom vof;   /* VAP output format register 0x2090 */
 423         struct radeon_state_atom vte;   /* (20B0) */
 424         struct radeon_state_atom vap_vf_max_vtx_indx;   /* Maximum Vertex Indx Clamp (2134) */
 425         struct radeon_state_atom vap_cntl_status;
 426         struct radeon_state_atom vir[2];        /* vap input route (2150/21E0) */
 427         struct radeon_state_atom vic;   /* vap input control (2180) */
 428         struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 429         struct radeon_state_atom vap_clip_cntl;
 430         struct radeon_state_atom vap_clip;
 431         struct radeon_state_atom vap_pvs_vtx_timeout_reg;       /* Vertex timeout register (2288) */
 432         struct radeon_state_atom pvs;   /* pvs_cntl (22D0) */
 433         struct radeon_state_atom gb_enable;     /* (4008) */
 434         struct radeon_state_atom gb_misc;       /* Multisampling position shifts ? (4010) */
 435         struct radeon_state_atom ga_point_s0;   /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 436         struct radeon_state_atom ga_triangle_stipple;   /* (4214) */
 437         struct radeon_state_atom ps;    /* pointsize (421C) */
 438         struct radeon_state_atom ga_point_minmax;       /* (4230) */
 439         struct radeon_state_atom lcntl; /* line control */
 440         struct radeon_state_atom ga_line_stipple;       /* (4260) */
 441         struct radeon_state_atom shade;
 442         struct radeon_state_atom polygon_mode;
 443         struct radeon_state_atom fogp;  /* fog parameters (4294) */
 444         struct radeon_state_atom ga_soft_reset; /* (429C) */
 445         struct radeon_state_atom zbias_cntl;
 446         struct radeon_state_atom zbs;   /* zbias (42A4) */
 447         struct radeon_state_atom occlusion_cntl;
 448         struct radeon_state_atom cul;   /* cull cntl (42B8) */
 449         struct radeon_state_atom su_depth_scale;        /* (42C0) */
 450         struct radeon_state_atom rc;    /* rs control (4300) */
 451         struct radeon_state_atom ri;    /* rs interpolators (4310) */
 452         struct radeon_state_atom rr;    /* rs route (4330) */
 453         struct radeon_state_atom sc_hyperz;     /* (43A4) */
 454         struct radeon_state_atom sc_screendoor; /* (43E8) */
 455         struct radeon_state_atom fp;    /* fragment program cntl + nodes (4600) */
 456         struct radeon_state_atom fpt;   /* texi - (4620) */
 457         struct radeon_state_atom us_out_fmt;    /* (46A4) */
 458         struct radeon_state_atom r500fp;        /* r500 fp instructions */
 459         struct radeon_state_atom r500fp_const;  /* r500 fp constants */
 460         struct radeon_state_atom fpi[4];        /* fp instructions (46C0/47C0/48C0/49C0) */
 461         struct radeon_state_atom fogs;  /* fog state (4BC0) */
 462         struct radeon_state_atom fogc;  /* fog color (4BC8) */
 463         struct radeon_state_atom at;    /* alpha test (4BD4) */
 464         struct radeon_state_atom fg_depth_src;  /* (4BD8) */
 465         struct radeon_state_atom fpp;   /* 0x4C00 and following */
 466         struct radeon_state_atom rb3d_cctl;     /* (4E00) */
 467         struct radeon_state_atom bld;   /* blending (4E04) */
 468         struct radeon_state_atom cmk;   /* colormask (4E0C) */
 469         struct radeon_state_atom blend_color;   /* constant blend color */
 470         struct radeon_state_atom rop;   /* ropcntl */
 471         struct radeon_state_atom cb;    /* colorbuffer (4E28) */
 472         struct radeon_state_atom rb3d_dither_ctl;       /* (4E50) */
 473         struct radeon_state_atom rb3d_aaresolve_ctl;    /* (4E88) */
 474         struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold;  /* (4E88) I saw it only written on RV350 hardware..  */
 475         struct radeon_state_atom zs;    /* zstencil control (4F00) */
 476         struct radeon_state_atom zstencil_format;
 477         struct radeon_state_atom zb;    /* z buffer (4F20) */
 478         struct radeon_state_atom zb_depthclearvalue;    /* (4F28) */
 479         struct radeon_state_atom unk4F30;       /* (4F30) */
 480         struct radeon_state_atom zb_hiz_offset; /* (4F44) */
 481         struct radeon_state_atom zb_hiz_pitch;  /* (4F54) */
 482
 483         struct radeon_state_atom vpi;   /* vp instructions */
 484         struct radeon_state_atom vpp;   /* vp parameters */
 485         struct radeon_state_atom vps;   /* vertex point size (?) */
 486         struct radeon_state_atom vpucp[6];      /* vp user clip plane - 6 */
 487         /* 8 texture units */
 488         /* the state is grouped by function and not by
 489            texture unit. This makes single unit updates
 490            really awkward - we are much better off
 491            updating the whole thing at once */
 492         struct {
 493                 struct radeon_state_atom filter;
 494                 struct radeon_state_atom filter_1;
 495                 struct radeon_state_atom size;
 496                 struct radeon_state_atom format;
 497                 struct radeon_state_atom pitch;
 498                 struct radeon_state_atom offset;
 499                 struct radeon_state_atom chroma_key;
 500                 struct radeon_state_atom border_color;
 501         } tex;
 502         struct radeon_state_atom txe;   /* tex enable (4104) */
 503
 504         r300TexObj *textures[R300_MAX_TEXTURE_UNITS];
 505 };
 506
 507 /**
 508  * This structure holds the command buffer while it is being constructed.
 509  *
 510  * The first batch of commands in the buffer is always the state that needs
 511  * to be re-emitted when the context is lost. This batch can be skipped
 512  * otherwise.
 513  */
 514 struct r300_cmdbuf {
 515     struct radeon_cs_manager    *csm;
 516     struct radeon_cs            *cs;
 517         int size; /** # of dwords total */
 518         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 519 };
 520
 521 /**
 522  * State cache
 523  */
 524
 525 /* Vertex shader state */
 526
 527 /* Perhaps more if we store programs in vmem? */
 528 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 529 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 530
 531 /* Can be tested with colormat currently. */
 532 #define VSF_MAX_FRAGMENT_TEMPS (14)
 533
 534 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 535 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 536
 537 struct r300_vertex_shader_fragment {
 538         int length;
 539         union {
 540                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 541                 float f[VSF_MAX_FRAGMENT_LENGTH];
 542                 GLuint i[VSF_MAX_FRAGMENT_LENGTH];
 543         } body;
 544 };
 545
 546 struct r300_vertex_shader_state {
 547         struct r300_vertex_shader_fragment program;
 548 };
 549
 550 extern int hw_tcl_on;
 551
 552 #define COLOR_IS_RGBA
 553 #define TAG(x) r300##x
 554 #include "tnl_dd/t_dd_vertex.h"
 555 #undef TAG
 556
 557 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 558 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 559
 560 /* Should but doesnt work */
 561 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 562
 563 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 564  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 565  */
 566
 567 struct r300_vertex_program_key {
 568         GLuint InputsRead;
 569         GLuint OutputsWritten;
 570         GLuint OutputsAdded;
 571 };
 572
 573 struct r300_vertex_program {
 574         struct r300_vertex_program *next;
 575         struct r300_vertex_program_key key;
 576         int translated;
 577
 578         struct r300_vertex_shader_fragment program;
 579
 580         int pos_end;
 581         int num_temporaries;    /* Number of temp vars used by program */
 582         int wpos_idx;
 583         int inputs[VERT_ATTRIB_MAX];
 584         int outputs[VERT_RESULT_MAX];
 585         int native;
 586         int ref_count;
 587         int use_ref_count;
 588 };
 589
 590 struct r300_vertex_program_cont {
 591         struct gl_vertex_program mesa_program;  /* Must be first */
 592         struct r300_vertex_shader_fragment params;
 593         struct r300_vertex_program *progs;
 594 };
 595
 596 #define PFS_MAX_ALU_INST        64
 597 #define PFS_MAX_TEX_INST        64
 598 #define PFS_MAX_TEX_INDIRECT 4
 599 #define PFS_NUM_TEMP_REGS       32
 600 #define PFS_NUM_CONST_REGS      16
 601
 602 struct r300_pfs_compile_state;
 603
 604
 605 /**
 606  * Stores state that influences the compilation of a fragment program.
 607  */
 608 struct r300_fragment_program_external_state {
 609         struct {
 610                 /**
 611                  * If the sampler is used as a shadow sampler,
 612                  * this field is:
 613                  *  0 - GL_LUMINANCE
 614                  *  1 - GL_INTENSITY
 615                  *  2 - GL_ALPHA
 616                  * depending on the depth texture mode.
 617                  */
 618                 GLuint depth_texture_mode : 2;
 619
 620                 /**
 621                  * If the sampler is used as a shadow sampler,
 622                  * this field is (texture_compare_func - GL_NEVER).
 623                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 624                  *
 625                  * Otherwise, this field is 0.
 626                  */
 627                 GLuint texture_compare_func : 3;
 628         } unit[16];
 629 };
 630
 631
 632 struct r300_fragment_program_node {
 633         int tex_offset; /**< first tex instruction */
 634         int tex_end; /**< last tex instruction, relative to tex_offset */
 635         int alu_offset; /**< first ALU instruction */
 636         int alu_end; /**< last ALU instruction, relative to alu_offset */
 637         int flags;
 638 };
 639
 640 /**
 641  * Stores an R300 fragment program in its compiled-to-hardware form.
 642  */
 643 struct r300_fragment_program_code {
 644         struct {
 645                 int length; /**< total # of texture instructions used */
 646                 GLuint inst[PFS_MAX_TEX_INST];
 647         } tex;
 648
 649         struct {
 650                 int length; /**< total # of ALU instructions used */
 651                 struct {
 652                         GLuint inst0;
 653                         GLuint inst1;
 654                         GLuint inst2;
 655                         GLuint inst3;
 656                 } inst[PFS_MAX_ALU_INST];
 657         } alu;
 658
 659         struct r300_fragment_program_node node[4];
 660         int cur_node;
 661         int first_node_has_tex;
 662
 663         /**
 664          * Remember which program register a given hardware constant
 665          * belongs to.
 666          */
 667         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 668         int const_nr;
 669
 670         int max_temp_idx;
 671 };
 672
 673 /**
 674  * Store everything about a fragment program that is needed
 675  * to render with that program.
 676  */
 677 struct r300_fragment_program {
 678         struct gl_fragment_program mesa_program;
 679
 680         GLboolean translated;
 681         GLboolean error;
 682
 683         struct r300_fragment_program_external_state state;
 684         struct r300_fragment_program_code code;
 685
 686         GLboolean WritesDepth;
 687         GLuint optimization;
 688 };
 689
 690 struct r500_pfs_compile_state;
 691
 692 struct r500_fragment_program_external_state {
 693         struct {
 694                 /**
 695                  * If the sampler is used as a shadow sampler,
 696                  * this field is:
 697                  *  0 - GL_LUMINANCE
 698                  *  1 - GL_INTENSITY
 699                  *  2 - GL_ALPHA
 700                  * depending on the depth texture mode.
 701                  */
 702                 GLuint depth_texture_mode : 2;
 703
 704                 /**
 705                  * If the sampler is used as a shadow sampler,
 706                  * this field is (texture_compare_func - GL_NEVER).
 707                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 708                  *
 709                  * Otherwise, this field is 0.
 710                  */
 711                 GLuint texture_compare_func : 3;
 712         } unit[16];
 713 };
 714
 715 struct r500_fragment_program_code {
 716         struct {
 717                 GLuint inst0;
 718                 GLuint inst1;
 719                 GLuint inst2;
 720                 GLuint inst3;
 721                 GLuint inst4;
 722                 GLuint inst5;
 723         } inst[512];
 724
 725         int inst_offset;
 726         int inst_end;
 727
 728         /**
 729          * Remember which program register a given hardware constant
 730          * belongs to.
 731          */
 732         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 733         int const_nr;
 734
 735         int max_temp_idx;
 736 };
 737
 738 struct r500_fragment_program {
 739         struct gl_fragment_program mesa_program;
 740
 741         GLcontext *ctx;
 742         GLboolean translated;
 743         GLboolean error;
 744
 745         struct r500_fragment_program_external_state state;
 746         struct r500_fragment_program_code code;
 747
 748         GLboolean writes_depth;
 749
 750         GLuint optimization;
 751 };
 752
 753 #define R300_MAX_AOS_ARRAYS             16
 754
 755 #define REG_COORDS      0
 756 #define REG_COLOR0      1
 757 #define REG_TEX0        2
 758
 759 struct r300_aos {
 760         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 761         int offset; /** Offset into buffer object, in bytes */
 762         int components; /** Number of components per vertex */
 763         int stride; /** Stride in dwords (may be 0 for repeating) */
 764         int count; /** Number of vertices */
 765 };
 766
 767 struct r300_state {
 768         struct r300_texture_state texture;
 769         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 770         struct r300_vertex_shader_state vertex_shader;
 771         struct r300_aos aos[R300_MAX_AOS_ARRAYS];
 772         int aos_count;
 773
 774         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 775         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 776
 777         DECLARE_RENDERINPUTS(render_inputs_bitset);     /* actual render inputs that R300 was configured for.
 778                                                            They are the same as tnl->render_inputs for fixed pipeline */
 779
 780 };
 781
 782 #define R300_FALLBACK_NONE 0
 783 #define R300_FALLBACK_TCL 1
 784 #define R300_FALLBACK_RAST 2
 785
 786 /* r300_swtcl.c
 787  */
 788 struct r300_swtcl_info {
 789    GLuint RenderIndex;
 790
 791    /**
 792     * Size of a hardware vertex.  This is calculated when \c ::vertex_attrs is
 793     * installed in the Mesa state vector.
 794     */
 795    GLuint vertex_size;
 796
 797    /**
 798     * Attributes instructing the Mesa TCL pipeline where / how to put vertex
 799     * data in the hardware buffer.
 800     */
 801    struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 802
 803    /**
 804     * Number of elements of \c ::vertex_attrs that are actually used.
 805     */
 806    GLuint vertex_attr_count;
 807
 808    /**
 809     * Cached pointer to the buffer where Mesa will store vertex data.
 810     */
 811    GLubyte *verts;
 812
 813    /* Fallback rasterization functions
 814     */
 815    GLuint hw_primitive;
 816    GLenum render_primitive;
 817    GLuint numverts;
 818
 819    /**
 820     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 821     */
 822    GLuint coloroffset;
 823
 824    /**
 825     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 826     */
 827    GLuint specoffset;
 828
 829    struct radeon_bo *bo;
 830    void (*flush) (r300ContextPtr);
 831 };
 832
 833
 834 /**
 835  * \brief R300 context structure.
 836  */
 837 struct r300_context {
 838         struct radeon_context radeon;   /* parent class, must be first */
 839
 840         struct r300_hw_state hw;
 841         struct r300_cmdbuf cmdbuf;
 842         struct r300_state state;
 843         struct gl_vertex_program *curr_vp;
 844         struct r300_vertex_program *selected_vp;
 845
 846         /* Vertex buffers
 847          */
 848         GLuint NewGLState;
 849
 850         int texture_depth;
 851         float initialMaxAnisotropy;
 852
 853         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 854         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 855
 856         GLboolean disable_lowimpact_fallback;
 857
 858         DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
 859         struct r300_swtcl_info swtcl;
 860 };
 861
 862 struct r300_buffer_object {
 863         struct gl_buffer_object mesa_obj;
 864         int id;
 865 };
 866
 867 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 868
 869 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 870 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 871                                    __DRIcontextPrivate * driContextPriv,
 872                                    void *sharedContextPrivate);
 873
 874 extern void r300SelectVertexShader(r300ContextPtr r300);
 875 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 876 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 877                                       struct r300_vertex_program_cont *vp,
 878                                       float *dst);
 879
 880 #define RADEON_D_CAPTURE 0
 881 #define RADEON_D_PLAYBACK 1
 882 #define RADEON_D_PLAYBACK_RAW 2
 883 #define RADEON_D_T 3
 884
 885 #endif                          /* __R300_CONTEXT_H__ */