src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R300_CONTEXT_H__
  38 #define __R300_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45 #include "common_context.h"
  46 #include "radeon_context.h"
  47 #include "radeon_bo.h"
  48
  49 #include "main/macros.h"
  50 #include "main/mtypes.h"
  51 #include "main/colormac.h"
  52
  53 struct r300_context;
  54 typedef struct r300_context r300ContextRec;
  55 typedef struct r300_context *r300ContextPtr;
  56
  57
  58 #include "main/mm.h"
  59
  60 /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  61    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  62    with other compilers ... GLUE!
  63 */
  64 #define WARN_ONCE(a, ...)       { \
  65         static int warn##__LINE__=1; \
  66         if(warn##__LINE__){ \
  67                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  68                 fprintf(stderr, "File %s function %s line %d\n", \
  69                         __FILE__, __FUNCTION__, __LINE__); \
  70                 fprintf(stderr,  a, ## __VA_ARGS__);\
  71                 fprintf(stderr, "***************************************************************************\n"); \
  72                 warn##__LINE__=0;\
  73                 } \
  74         }
  75
  76 #include "r300_vertprog.h"
  77 #include "r500_fragprog.h"
  78
  79
  80
  81 /************ DMA BUFFERS **************/
  82
  83 /* The blit width for texture uploads
  84  */
  85 #define R300_BLIT_WIDTH_BYTES 1024
  86 #define R300_MAX_TEXTURE_UNITS 8
  87
  88 struct r300_texture_state {
  89         int tc_count;           /* number of incoming texture coordinates from VAP */
  90 };
  91
  92
  93 #define R300_VPT_CMD_0          0
  94 #define R300_VPT_XSCALE         1
  95 #define R300_VPT_XOFFSET        2
  96 #define R300_VPT_YSCALE         3
  97 #define R300_VPT_YOFFSET        4
  98 #define R300_VPT_ZSCALE         5
  99 #define R300_VPT_ZOFFSET        6
 100 #define R300_VPT_CMDSIZE        7
 101
 102 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
 103 #define R300_VIR_CNTL_0         1
 104 #define R300_VIR_CNTL_1         2
 105 #define R300_VIR_CNTL_2         3
 106 #define R300_VIR_CNTL_3         4
 107 #define R300_VIR_CNTL_4         5
 108 #define R300_VIR_CNTL_5         6
 109 #define R300_VIR_CNTL_6         7
 110 #define R300_VIR_CNTL_7         8
 111 #define R300_VIR_CMDSIZE        9
 112
 113 #define R300_VIC_CMD_0          0
 114 #define R300_VIC_CNTL_0         1
 115 #define R300_VIC_CNTL_1         2
 116 #define R300_VIC_CMDSIZE        3
 117
 118 #define R300_VOF_CMD_0          0
 119 #define R300_VOF_CNTL_0         1
 120 #define R300_VOF_CNTL_1         2
 121 #define R300_VOF_CMDSIZE        3
 122
 123 #define R300_PVS_CMD_0          0
 124 #define R300_PVS_CNTL_1         1
 125 #define R300_PVS_CNTL_2         2
 126 #define R300_PVS_CNTL_3         3
 127 #define R300_PVS_CMDSIZE        4
 128
 129 #define R300_GB_MISC_CMD_0              0
 130 #define R300_GB_MISC_MSPOS_0            1
 131 #define R300_GB_MISC_MSPOS_1            2
 132 #define R300_GB_MISC_TILE_CONFIG        3
 133 #define R300_GB_MISC_SELECT             4
 134 #define R300_GB_MISC_AA_CONFIG          5
 135 #define R300_GB_MISC_CMDSIZE            6
 136
 137 #define R300_TXE_CMD_0          0
 138 #define R300_TXE_ENABLE         1
 139 #define R300_TXE_CMDSIZE        2
 140
 141 #define R300_PS_CMD_0           0
 142 #define R300_PS_POINTSIZE       1
 143 #define R300_PS_CMDSIZE         2
 144
 145 #define R300_ZBS_CMD_0          0
 146 #define R300_ZBS_T_FACTOR       1
 147 #define R300_ZBS_T_CONSTANT     2
 148 #define R300_ZBS_W_FACTOR       3
 149 #define R300_ZBS_W_CONSTANT     4
 150 #define R300_ZBS_CMDSIZE        5
 151
 152 #define R300_CUL_CMD_0          0
 153 #define R300_CUL_CULL           1
 154 #define R300_CUL_CMDSIZE        2
 155
 156 #define R300_RC_CMD_0           0
 157 #define R300_RC_CNTL_0          1
 158 #define R300_RC_CNTL_1          2
 159 #define R300_RC_CMDSIZE         3
 160
 161 #define R300_RI_CMD_0           0
 162 #define R300_RI_INTERP_0        1
 163 #define R300_RI_INTERP_1        2
 164 #define R300_RI_INTERP_2        3
 165 #define R300_RI_INTERP_3        4
 166 #define R300_RI_INTERP_4        5
 167 #define R300_RI_INTERP_5        6
 168 #define R300_RI_INTERP_6        7
 169 #define R300_RI_INTERP_7        8
 170 #define R300_RI_CMDSIZE         9
 171
 172 #define R500_RI_CMDSIZE        17
 173
 174 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 175 #define R300_RR_INST_0          1
 176 #define R300_RR_INST_1          2
 177 #define R300_RR_INST_2          3
 178 #define R300_RR_INST_3          4
 179 #define R300_RR_INST_4          5
 180 #define R300_RR_INST_5          6
 181 #define R300_RR_INST_6          7
 182 #define R300_RR_INST_7          8
 183 #define R300_RR_CMDSIZE         9
 184
 185 #define R300_FP_CMD_0           0
 186 #define R300_FP_CNTL0           1
 187 #define R300_FP_CNTL1           2
 188 #define R300_FP_CNTL2           3
 189 #define R300_FP_CMD_1           4
 190 #define R300_FP_NODE0           5
 191 #define R300_FP_NODE1           6
 192 #define R300_FP_NODE2           7
 193 #define R300_FP_NODE3           8
 194 #define R300_FP_CMDSIZE         9
 195
 196 #define R500_FP_CMD_0           0
 197 #define R500_FP_CNTL            1
 198 #define R500_FP_PIXSIZE         2
 199 #define R500_FP_CMD_1           3
 200 #define R500_FP_CODE_ADDR       4
 201 #define R500_FP_CODE_RANGE      5
 202 #define R500_FP_CODE_OFFSET     6
 203 #define R500_FP_CMD_2           7
 204 #define R500_FP_FC_CNTL         8
 205 #define R500_FP_CMDSIZE         9
 206
 207 #define R300_FPT_CMD_0          0
 208 #define R300_FPT_INSTR_0        1
 209 #define R300_FPT_CMDSIZE        65
 210
 211 #define R300_FPI_CMD_0          0
 212 #define R300_FPI_INSTR_0        1
 213 #define R300_FPI_CMDSIZE        65
 214 /* R500 has space for 512 instructions - 6 dwords per instruction */
 215 #define R500_FPI_CMDSIZE        (512*6+1)
 216
 217 #define R300_FPP_CMD_0          0
 218 #define R300_FPP_PARAM_0        1
 219 #define R300_FPP_CMDSIZE        (32*4+1)
 220 /* R500 has spcae for 256 constants - 4 dwords per constant */
 221 #define R500_FPP_CMDSIZE        (256*4+1)
 222
 223 #define R300_FOGS_CMD_0         0
 224 #define R300_FOGS_STATE         1
 225 #define R300_FOGS_CMDSIZE       2
 226
 227 #define R300_FOGC_CMD_0         0
 228 #define R300_FOGC_R             1
 229 #define R300_FOGC_G             2
 230 #define R300_FOGC_B             3
 231 #define R300_FOGC_CMDSIZE       4
 232
 233 #define R300_FOGP_CMD_0         0
 234 #define R300_FOGP_SCALE         1
 235 #define R300_FOGP_START         2
 236 #define R300_FOGP_CMDSIZE       3
 237
 238 #define R300_AT_CMD_0           0
 239 #define R300_AT_ALPHA_TEST      1
 240 #define R300_AT_UNKNOWN         2
 241 #define R300_AT_CMDSIZE         3
 242
 243 #define R300_BLD_CMD_0          0
 244 #define R300_BLD_CBLEND         1
 245 #define R300_BLD_ABLEND         2
 246 #define R300_BLD_CMDSIZE        3
 247
 248 #define R300_CMK_CMD_0          0
 249 #define R300_CMK_COLORMASK      1
 250 #define R300_CMK_CMDSIZE        2
 251
 252 #define R300_CB_CMD_0           0
 253 #define R300_CB_OFFSET          1
 254 #define R300_CB_CMD_1           2
 255 #define R300_CB_PITCH           3
 256 #define R300_CB_CMDSIZE         4
 257
 258 #define R300_ZS_CMD_0           0
 259 #define R300_ZS_CNTL_0          1
 260 #define R300_ZS_CNTL_1          2
 261 #define R300_ZS_CNTL_2          3
 262 #define R300_ZS_CMDSIZE         4
 263
 264 #define R300_ZB_CMD_0           0
 265 #define R300_ZB_OFFSET          1
 266 #define R300_ZB_PITCH           2
 267 #define R300_ZB_CMDSIZE         3
 268
 269 #define R300_VAP_CNTL_FLUSH     0
 270 #define R300_VAP_CNTL_FLUSH_1   1
 271 #define R300_VAP_CNTL_CMD       2
 272 #define R300_VAP_CNTL_INSTR     3
 273 #define R300_VAP_CNTL_SIZE      4
 274
 275 #define R300_VPI_CMD_0          0
 276 #define R300_VPI_INSTR_0        1
 277 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 278
 279 #define R300_VPP_CMD_0          0
 280 #define R300_VPP_PARAM_0        1
 281 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 282
 283 #define R300_VPUCP_CMD_0                0
 284 #define R300_VPUCP_X            1
 285 #define R300_VPUCP_Y            2
 286 #define R300_VPUCP_Z            3
 287 #define R300_VPUCP_W            4
 288 #define R300_VPUCP_CMDSIZE      5       /* 256 4-component parameters */
 289
 290 #define R300_VPS_CMD_0          0
 291 #define R300_VPS_ZERO_0         1
 292 #define R300_VPS_ZERO_1         2
 293 #define R300_VPS_POINTSIZE      3
 294 #define R300_VPS_ZERO_3         4
 295 #define R300_VPS_CMDSIZE        5
 296
 297         /* the layout is common for all fields inside tex */
 298 #define R300_TEX_CMD_0          0
 299 #define R300_TEX_VALUE_0        1
 300 /* We don't really use this, instead specify mtu+1 dynamically
 301 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 302 */
 303
 304 /**
 305  * Cache for hardware register state.
 306  */
 307 struct r300_hw_state {
 308         struct radeon_state_atom vpt;   /* viewport (1D98) */
 309         struct radeon_state_atom vap_cntl;
 310         struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
 311         struct radeon_state_atom vof;   /* VAP output format register 0x2090 */
 312         struct radeon_state_atom vte;   /* (20B0) */
 313         struct radeon_state_atom vap_vf_max_vtx_indx;   /* Maximum Vertex Indx Clamp (2134) */
 314         struct radeon_state_atom vap_cntl_status;
 315         struct radeon_state_atom vir[2];        /* vap input route (2150/21E0) */
 316         struct radeon_state_atom vic;   /* vap input control (2180) */
 317         struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
 318         struct radeon_state_atom vap_clip_cntl;
 319         struct radeon_state_atom vap_clip;
 320         struct radeon_state_atom vap_pvs_vtx_timeout_reg;       /* Vertex timeout register (2288) */
 321         struct radeon_state_atom pvs;   /* pvs_cntl (22D0) */
 322         struct radeon_state_atom gb_enable;     /* (4008) */
 323         struct radeon_state_atom gb_misc;       /* Multisampling position shifts ? (4010) */
 324         struct radeon_state_atom ga_point_s0;   /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
 325         struct radeon_state_atom ga_triangle_stipple;   /* (4214) */
 326         struct radeon_state_atom ps;    /* pointsize (421C) */
 327         struct radeon_state_atom ga_point_minmax;       /* (4230) */
 328         struct radeon_state_atom lcntl; /* line control */
 329         struct radeon_state_atom ga_line_stipple;       /* (4260) */
 330         struct radeon_state_atom shade;
 331         struct radeon_state_atom polygon_mode;
 332         struct radeon_state_atom fogp;  /* fog parameters (4294) */
 333         struct radeon_state_atom ga_soft_reset; /* (429C) */
 334         struct radeon_state_atom zbias_cntl;
 335         struct radeon_state_atom zbs;   /* zbias (42A4) */
 336         struct radeon_state_atom occlusion_cntl;
 337         struct radeon_state_atom cul;   /* cull cntl (42B8) */
 338         struct radeon_state_atom su_depth_scale;        /* (42C0) */
 339         struct radeon_state_atom rc;    /* rs control (4300) */
 340         struct radeon_state_atom ri;    /* rs interpolators (4310) */
 341         struct radeon_state_atom rr;    /* rs route (4330) */
 342         struct radeon_state_atom sc_hyperz;     /* (43A4) */
 343         struct radeon_state_atom sc_screendoor; /* (43E8) */
 344         struct radeon_state_atom fp;    /* fragment program cntl + nodes (4600) */
 345         struct radeon_state_atom fpt;   /* texi - (4620) */
 346         struct radeon_state_atom us_out_fmt;    /* (46A4) */
 347         struct radeon_state_atom r500fp;        /* r500 fp instructions */
 348         struct radeon_state_atom r500fp_const;  /* r500 fp constants */
 349         struct radeon_state_atom fpi[4];        /* fp instructions (46C0/47C0/48C0/49C0) */
 350         struct radeon_state_atom fogs;  /* fog state (4BC0) */
 351         struct radeon_state_atom fogc;  /* fog color (4BC8) */
 352         struct radeon_state_atom at;    /* alpha test (4BD4) */
 353         struct radeon_state_atom fg_depth_src;  /* (4BD8) */
 354         struct radeon_state_atom fpp;   /* 0x4C00 and following */
 355         struct radeon_state_atom rb3d_cctl;     /* (4E00) */
 356         struct radeon_state_atom bld;   /* blending (4E04) */
 357         struct radeon_state_atom cmk;   /* colormask (4E0C) */
 358         struct radeon_state_atom blend_color;   /* constant blend color */
 359         struct radeon_state_atom rop;   /* ropcntl */
 360         struct radeon_state_atom cb;    /* colorbuffer (4E28) */
 361         struct radeon_state_atom rb3d_dither_ctl;       /* (4E50) */
 362         struct radeon_state_atom rb3d_aaresolve_ctl;    /* (4E88) */
 363         struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold;  /* (4E88) I saw it only written on RV350 hardware..  */
 364         struct radeon_state_atom zs;    /* zstencil control (4F00) */
 365         struct radeon_state_atom zstencil_format;
 366         struct radeon_state_atom zb;    /* z buffer (4F20) */
 367         struct radeon_state_atom zb_depthclearvalue;    /* (4F28) */
 368         struct radeon_state_atom unk4F30;       /* (4F30) */
 369         struct radeon_state_atom zb_hiz_offset; /* (4F44) */
 370         struct radeon_state_atom zb_hiz_pitch;  /* (4F54) */
 371
 372         struct radeon_state_atom vpi;   /* vp instructions */
 373         struct radeon_state_atom vpp;   /* vp parameters */
 374         struct radeon_state_atom vps;   /* vertex point size (?) */
 375         struct radeon_state_atom vpucp[6];      /* vp user clip plane - 6 */
 376         /* 8 texture units */
 377         /* the state is grouped by function and not by
 378            texture unit. This makes single unit updates
 379            really awkward - we are much better off
 380            updating the whole thing at once */
 381         struct {
 382                 struct radeon_state_atom filter;
 383                 struct radeon_state_atom filter_1;
 384                 struct radeon_state_atom size;
 385                 struct radeon_state_atom format;
 386                 struct radeon_state_atom pitch;
 387                 struct radeon_state_atom offset;
 388                 struct radeon_state_atom chroma_key;
 389                 struct radeon_state_atom border_color;
 390         } tex;
 391         struct radeon_state_atom txe;   /* tex enable (4104) */
 392
 393         radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
 394 };
 395
 396 /**
 397  * State cache
 398  */
 399
 400 /* Vertex shader state */
 401
 402 /* Perhaps more if we store programs in vmem? */
 403 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 404 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 405
 406 /* Can be tested with colormat currently. */
 407 #define VSF_MAX_FRAGMENT_TEMPS (14)
 408
 409 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 410 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 411
 412 struct r300_vertex_shader_fragment {
 413         int length;
 414         union {
 415                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 416                 float f[VSF_MAX_FRAGMENT_LENGTH];
 417                 GLuint i[VSF_MAX_FRAGMENT_LENGTH];
 418         } body;
 419 };
 420
 421 struct r300_vertex_shader_state {
 422         struct r300_vertex_shader_fragment program;
 423 };
 424
 425 extern int hw_tcl_on;
 426
 427 #define COLOR_IS_RGBA
 428 #define TAG(x) r300##x
 429 #include "tnl_dd/t_dd_vertex.h"
 430 #undef TAG
 431
 432 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 433 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 434
 435 /* Should but doesnt work */
 436 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 437
 438 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 439  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 440  */
 441
 442 struct r300_vertex_program_key {
 443         GLuint InputsRead;
 444         GLuint OutputsWritten;
 445         GLuint OutputsAdded;
 446 };
 447
 448 struct r300_vertex_program {
 449         struct r300_vertex_program *next;
 450         struct r300_vertex_program_key key;
 451         int translated;
 452
 453         struct r300_vertex_shader_fragment program;
 454
 455         int pos_end;
 456         int num_temporaries;    /* Number of temp vars used by program */
 457         int wpos_idx;
 458         int inputs[VERT_ATTRIB_MAX];
 459         int outputs[VERT_RESULT_MAX];
 460         int native;
 461         int ref_count;
 462         int use_ref_count;
 463 };
 464
 465 struct r300_vertex_program_cont {
 466         struct gl_vertex_program mesa_program;  /* Must be first */
 467         struct r300_vertex_shader_fragment params;
 468         struct r300_vertex_program *progs;
 469 };
 470
 471 #define PFS_MAX_ALU_INST        64
 472 #define PFS_MAX_TEX_INST        64
 473 #define PFS_MAX_TEX_INDIRECT 4
 474 #define PFS_NUM_TEMP_REGS       32
 475 #define PFS_NUM_CONST_REGS      16
 476
 477 struct r300_pfs_compile_state;
 478
 479
 480 /**
 481  * Stores state that influences the compilation of a fragment program.
 482  */
 483 struct r300_fragment_program_external_state {
 484         struct {
 485                 /**
 486                  * If the sampler is used as a shadow sampler,
 487                  * this field is:
 488                  *  0 - GL_LUMINANCE
 489                  *  1 - GL_INTENSITY
 490                  *  2 - GL_ALPHA
 491                  * depending on the depth texture mode.
 492                  */
 493                 GLuint depth_texture_mode : 2;
 494
 495                 /**
 496                  * If the sampler is used as a shadow sampler,
 497                  * this field is (texture_compare_func - GL_NEVER).
 498                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 499                  *
 500                  * Otherwise, this field is 0.
 501                  */
 502                 GLuint texture_compare_func : 3;
 503         } unit[16];
 504 };
 505
 506
 507 struct r300_fragment_program_node {
 508         int tex_offset; /**< first tex instruction */
 509         int tex_end; /**< last tex instruction, relative to tex_offset */
 510         int alu_offset; /**< first ALU instruction */
 511         int alu_end; /**< last ALU instruction, relative to alu_offset */
 512         int flags;
 513 };
 514
 515 /**
 516  * Stores an R300 fragment program in its compiled-to-hardware form.
 517  */
 518 struct r300_fragment_program_code {
 519         struct {
 520                 int length; /**< total # of texture instructions used */
 521                 GLuint inst[PFS_MAX_TEX_INST];
 522         } tex;
 523
 524         struct {
 525                 int length; /**< total # of ALU instructions used */
 526                 struct {
 527                         GLuint inst0;
 528                         GLuint inst1;
 529                         GLuint inst2;
 530                         GLuint inst3;
 531                 } inst[PFS_MAX_ALU_INST];
 532         } alu;
 533
 534         struct r300_fragment_program_node node[4];
 535         int cur_node;
 536         int first_node_has_tex;
 537
 538         /**
 539          * Remember which program register a given hardware constant
 540          * belongs to.
 541          */
 542         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 543         int const_nr;
 544
 545         int max_temp_idx;
 546 };
 547
 548 /**
 549  * Store everything about a fragment program that is needed
 550  * to render with that program.
 551  */
 552 struct r300_fragment_program {
 553         struct gl_fragment_program mesa_program;
 554
 555         GLboolean translated;
 556         GLboolean error;
 557
 558         struct r300_fragment_program_external_state state;
 559         struct r300_fragment_program_code code;
 560
 561         GLboolean WritesDepth;
 562         GLuint optimization;
 563 };
 564
 565 struct r500_pfs_compile_state;
 566
 567 struct r500_fragment_program_external_state {
 568         struct {
 569                 /**
 570                  * If the sampler is used as a shadow sampler,
 571                  * this field is:
 572                  *  0 - GL_LUMINANCE
 573                  *  1 - GL_INTENSITY
 574                  *  2 - GL_ALPHA
 575                  * depending on the depth texture mode.
 576                  */
 577                 GLuint depth_texture_mode : 2;
 578
 579                 /**
 580                  * If the sampler is used as a shadow sampler,
 581                  * this field is (texture_compare_func - GL_NEVER).
 582                  * [e.g. if compare function is GL_LEQUAL, this field is 3]
 583                  *
 584                  * Otherwise, this field is 0.
 585                  */
 586                 GLuint texture_compare_func : 3;
 587         } unit[16];
 588 };
 589
 590 struct r500_fragment_program_code {
 591         struct {
 592                 GLuint inst0;
 593                 GLuint inst1;
 594                 GLuint inst2;
 595                 GLuint inst3;
 596                 GLuint inst4;
 597                 GLuint inst5;
 598         } inst[512];
 599
 600         int inst_offset;
 601         int inst_end;
 602
 603         /**
 604          * Remember which program register a given hardware constant
 605          * belongs to.
 606          */
 607         struct prog_src_register constant[PFS_NUM_CONST_REGS];
 608         int const_nr;
 609
 610         int max_temp_idx;
 611 };
 612
 613 struct r500_fragment_program {
 614         struct gl_fragment_program mesa_program;
 615
 616         GLcontext *ctx;
 617         GLboolean translated;
 618         GLboolean error;
 619
 620         struct r500_fragment_program_external_state state;
 621         struct r500_fragment_program_code code;
 622
 623         GLboolean writes_depth;
 624
 625         GLuint optimization;
 626 };
 627
 628 #define R300_MAX_AOS_ARRAYS             16
 629
 630 #define REG_COORDS      0
 631 #define REG_COLOR0      1
 632 #define REG_TEX0        2
 633
 634 struct r300_state {
 635         struct r300_texture_state texture;
 636         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 637         struct r300_vertex_shader_state vertex_shader;
 638         struct radeon_aos aos[R300_MAX_AOS_ARRAYS];
 639         int aos_count;
 640
 641         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 642         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 643
 644         DECLARE_RENDERINPUTS(render_inputs_bitset);     /* actual render inputs that R300 was configured for.
 645                                                            They are the same as tnl->render_inputs for fixed pipeline */
 646
 647 };
 648
 649 #define R300_FALLBACK_NONE 0
 650 #define R300_FALLBACK_TCL 1
 651 #define R300_FALLBACK_RAST 2
 652
 653 /* r300_swtcl.c
 654  */
 655 struct r300_swtcl_info {
 656   /*
 657     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 658     */
 659    GLuint coloroffset;
 660
 661    /**
 662     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 663     */
 664    GLuint specoffset;
 665 };
 666
 667
 668 /**
 669  * \brief R300 context structure.
 670  */
 671 struct r300_context {
 672         struct radeon_context radeon;   /* parent class, must be first */
 673
 674         struct r300_hw_state hw;
 675
 676         struct r300_state state;
 677         struct gl_vertex_program *curr_vp;
 678         struct r300_vertex_program *selected_vp;
 679
 680         /* Vertex buffers
 681          */
 682         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 683         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 684
 685         GLboolean disable_lowimpact_fallback;
 686
 687         DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
 688         struct r300_swtcl_info swtcl;
 689 };
 690
 691 struct r300_buffer_object {
 692         struct gl_buffer_object mesa_obj;
 693         int id;
 694 };
 695
 696 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 697
 698 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 699 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 700                                    __DRIcontextPrivate * driContextPriv,
 701                                    void *sharedContextPrivate);
 702
 703 extern void r300SelectVertexShader(r300ContextPtr r300);
 704 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 705 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 706                                       struct r300_vertex_program_cont *vp,
 707                                       float *dst);
 708
 709 #define RADEON_D_CAPTURE 0
 710 #define RADEON_D_PLAYBACK 1
 711 #define RADEON_D_PLAYBACK_RAW 2
 712 #define RADEON_D_T 3
 713
 714 #define r300PackFloat32 radeonPackFloat32
 715 #define r300PackFloat24 radeonPackFloat24
 716
 717 #endif                          /* __R300_CONTEXT_H__ */