src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 #define USER_BUFFERS
  51 #define RADEON_VTXFMT_A
  52 #define HW_VBOS
  53
  54 /* We don't handle 16 bits elts swapping yet */
  55 #ifdef MESA_BIG_ENDIAN
  56 #define FORCE_32BITS_ELTS
  57 #endif
  58
  59 //#define OPTIMIZE_ELTS
  60 #define CB_DPATH
  61
  62 struct r300_context;
  63 typedef struct r300_context r300ContextRec;
  64 typedef struct r300_context *r300ContextPtr;
  65
  66 #include "radeon_lock.h"
  67 #include "mm.h"
  68
  69 /* Checkpoint.. for convenience */
  70 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  71 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  72    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  73    with other compilers ... GLUE!
  74 */
  75 #if 1
  76 #define WARN_ONCE(a, ...)       { \
  77         static int warn##__LINE__=1; \
  78         if(warn##__LINE__){ \
  79                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  80                 fprintf(stderr, "File %s function %s line %d\n", \
  81                         __FILE__, __FUNCTION__, __LINE__); \
  82                 fprintf(stderr,  a, ## __VA_ARGS__);\
  83                 fprintf(stderr, "***************************************************************************\n"); \
  84                 warn##__LINE__=0;\
  85                 } \
  86         }
  87 #else
  88 #define WARN_ONCE(a, ...) {}
  89 #endif
  90
  91   /* We should probably change types within vertex_shader
  92       and pixel_shader structure later on */
  93 #define CARD32 GLuint
  94 #include "vertex_shader.h"
  95 #include "r300_fragprog.h"
  96 #undef CARD32
  97
  98 static __inline__ uint32_t r300PackFloat32(float fl)
  99 {
 100         union { float fl; uint32_t u; } u;
 101
 102         u.fl = fl;
 103         return u.u;
 104 }
 105
 106
 107 /************ DMA BUFFERS **************/
 108
 109 /* Need refcounting on dma buffers:
 110  */
 111 struct r300_dma_buffer {
 112         int refcount;           /* the number of retained regions in buf */
 113         drmBufPtr buf;
 114         int id;
 115 };
 116 #undef GET_START
 117 #ifdef USER_BUFFERS
 118 #define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start))
 119 #else
 120 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 121                         (rvb)->address - rmesa->dma.buf0_address +      \
 122                         (rvb)->start)
 123 #endif
 124 /* A retained region, eg vertices for indexed vertices.
 125  */
 126 struct r300_dma_region {
 127         struct r300_dma_buffer *buf;
 128         char *address;          /* == buf->address */
 129         int start, end, ptr;    /* offsets from start of buf */
 130
 131     int aos_offset;     /* address in GART memory */
 132     int aos_stride;     /* distance between elements, in dwords */
 133     int aos_size;       /* number of components (1-4) */
 134     int aos_format;     /* format of components */
 135     int aos_reg;        /* VAP register assignment */
 136 };
 137
 138 struct r300_dma {
 139         /* Active dma region.  Allocations for vertices and retained
 140          * regions come from here.  Also used for emitting random vertices,
 141          * these may be flushed by calling flush_current();
 142          */
 143         struct r300_dma_region current;
 144
 145         void (*flush) (r300ContextPtr);
 146
 147         char *buf0_address;     /* start of buf[0], for index calcs */
 148
 149         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 150          * for which a DISCARD command is currently queued in the command buffer.
 151          */
 152         GLuint nr_released_bufs;
 153 };
 154
 155        /* Texture related */
 156
 157 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 158
 159 /* Texture object in locally shared texture space.
 160  */
 161 struct r300_tex_obj {
 162         driTextureObject base;
 163
 164         GLuint bufAddr;         /* Offset to start of locally
 165                                    shared texture block */
 166
 167         GLuint dirty_state;     /* Flags (1 per texunit) for
 168                                    whether or not this texobj
 169                                    has dirty hardware state
 170                                    (pp_*) that needs to be
 171                                    brought into the
 172                                    texunit. */
 173
 174         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 175         /* Six, for the cube faces */
 176
 177
 178         GLuint pitch; /* this isn't sent to hardware just used in calculations */
 179         /* hardware register values */
 180         /* Note that R200 has 8 registers per texture and R300 only 7 */
 181         GLuint filter;
 182         GLuint pitch_reg;
 183         GLuint size;    /* npot only */
 184         GLuint format;
 185         GLuint offset;  /* Image location in the card's address space.
 186                                    All cube faces follow. */
 187         GLuint unknown4;
 188         GLuint unknown5;
 189         /* end hardware registers */
 190
 191         /* registers computed by r200 code - keep them here to
 192            compare against what is actually written.
 193
 194            to be removed later.. */
 195         GLuint pp_border_color;
 196         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 197         GLuint format_x;
 198
 199
 200         GLboolean border_fallback;
 201
 202         GLuint tile_bits; /* hw texture tile bits used on this texture */
 203 };
 204
 205 struct r300_texture_env_state {
 206         r300TexObjPtr texobj;
 207         GLenum format;
 208         GLenum envMode;
 209 };
 210
 211 #define R300_MAX_TEXTURE_UNITS 8
 212
 213 struct r300_texture_state {
 214         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 215         int tc_count; /* number of incoming texture coordinates from VAP */
 216 };
 217
 218 /**
 219  * A block of hardware state.
 220  *
 221  * When check returns non-zero, the returned number of dwords must be
 222  * copied verbatim into the command buffer in order to update a state atom
 223  * when it is dirty.
 224  */
 225 struct r300_state_atom {
 226         struct r300_state_atom *next, *prev;
 227         const char* name;       /* for debug */
 228         int cmd_size;           /* maximum size in dwords */
 229         GLuint idx;             /* index in an array (e.g. textures) */
 230         uint32_t* cmd;
 231         GLboolean dirty;
 232
 233         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 234 };
 235
 236
 237 #define R300_VPT_CMD_0          0
 238 #define R300_VPT_XSCALE         1
 239 #define R300_VPT_XOFFSET        2
 240 #define R300_VPT_YSCALE         3
 241 #define R300_VPT_YOFFSET        4
 242 #define R300_VPT_ZSCALE         5
 243 #define R300_VPT_ZOFFSET        6
 244 #define R300_VPT_CMDSIZE        7
 245
 246 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 247 #define R300_VIR_CNTL_0         1
 248 #define R300_VIR_CNTL_1         2
 249 #define R300_VIR_CNTL_2         3
 250 #define R300_VIR_CNTL_3         4
 251 #define R300_VIR_CNTL_4         5
 252 #define R300_VIR_CNTL_5         6
 253 #define R300_VIR_CNTL_6         7
 254 #define R300_VIR_CNTL_7         8
 255 #define R300_VIR_CMDSIZE        9
 256
 257 #define R300_VIC_CMD_0          0
 258 #define R300_VIC_CNTL_0         1
 259 #define R300_VIC_CNTL_1         2
 260 #define R300_VIC_CMDSIZE        3
 261
 262 #define R300_VOF_CMD_0          0
 263 #define R300_VOF_CNTL_0         1
 264 #define R300_VOF_CNTL_1         2
 265 #define R300_VOF_CMDSIZE        3
 266
 267
 268 #define R300_PVS_CMD_0          0
 269 #define R300_PVS_CNTL_1         1
 270 #define R300_PVS_CNTL_2         2
 271 #define R300_PVS_CNTL_3         3
 272 #define R300_PVS_CMDSIZE        4
 273
 274 #define R300_GB_MISC_CMD_0              0
 275 #define R300_GB_MISC_MSPOS_0            1
 276 #define R300_GB_MISC_MSPOS_1            2
 277 #define R300_GB_MISC_TILE_CONFIG        3
 278 #define R300_GB_MISC_SELECT             4
 279 #define R300_GB_MISC_AA_CONFIG          5
 280 #define R300_GB_MISC_CMDSIZE            6
 281
 282 #define R300_TXE_CMD_0          0
 283 #define R300_TXE_ENABLE         1
 284 #define R300_TXE_CMDSIZE        2
 285
 286 #define R300_PS_CMD_0           0
 287 #define R300_PS_POINTSIZE       1
 288 #define R300_PS_CMDSIZE         2
 289
 290 #define R300_ZBS_CMD_0          0
 291 #define R300_ZBS_T_FACTOR       1
 292 #define R300_ZBS_T_CONSTANT     2
 293 #define R300_ZBS_W_FACTOR       3
 294 #define R300_ZBS_W_CONSTANT     4
 295 #define R300_ZBS_CMDSIZE        5
 296
 297 #define R300_CUL_CMD_0          0
 298 #define R300_CUL_CULL           1
 299 #define R300_CUL_CMDSIZE        2
 300
 301 #define R300_RC_CMD_0           0
 302 #define R300_RC_CNTL_0          1
 303 #define R300_RC_CNTL_1          2
 304 #define R300_RC_CMDSIZE         3
 305
 306 #define R300_RI_CMD_0           0
 307 #define R300_RI_INTERP_0        1
 308 #define R300_RI_INTERP_1        2
 309 #define R300_RI_INTERP_2        3
 310 #define R300_RI_INTERP_3        4
 311 #define R300_RI_INTERP_4        5
 312 #define R300_RI_INTERP_5        6
 313 #define R300_RI_INTERP_6        7
 314 #define R300_RI_INTERP_7        8
 315 #define R300_RI_CMDSIZE         9
 316
 317 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 318 #define R300_RR_ROUTE_0         1
 319 #define R300_RR_ROUTE_1         2
 320 #define R300_RR_ROUTE_2         3
 321 #define R300_RR_ROUTE_3         4
 322 #define R300_RR_ROUTE_4         5
 323 #define R300_RR_ROUTE_5         6
 324 #define R300_RR_ROUTE_6         7
 325 #define R300_RR_ROUTE_7         8
 326 #define R300_RR_CMDSIZE         9
 327
 328 #define R300_FP_CMD_0           0
 329 #define R300_FP_CNTL0           1
 330 #define R300_FP_CNTL1           2
 331 #define R300_FP_CNTL2           3
 332 #define R300_FP_CMD_1           4
 333 #define R300_FP_NODE0           5
 334 #define R300_FP_NODE1           6
 335 #define R300_FP_NODE2           7
 336 #define R300_FP_NODE3           8
 337 #define R300_FP_CMDSIZE         9
 338
 339 #define R300_FPT_CMD_0          0
 340 #define R300_FPT_INSTR_0        1
 341 #define R300_FPT_CMDSIZE        65
 342
 343 #define R300_FPI_CMD_0          0
 344 #define R300_FPI_INSTR_0        1
 345 #define R300_FPI_CMDSIZE        65
 346
 347 #define R300_FPP_CMD_0          0
 348 #define R300_FPP_PARAM_0        1
 349 #define R300_FPP_CMDSIZE        (32*4+1)
 350
 351 #define R300_FOGS_CMD_0         0
 352 #define R300_FOGS_STATE         1
 353 #define R300_FOGS_CMDSIZE       2
 354
 355 #define R300_FOGC_CMD_0         0
 356 #define R300_FOGC_R             1
 357 #define R300_FOGC_G             2
 358 #define R300_FOGC_B             3
 359 #define R300_FOGC_CMDSIZE       4
 360
 361 #define R300_FOGP_CMD_0         0
 362 #define R300_FOGP_SCALE         1
 363 #define R300_FOGP_START         2
 364 #define R300_FOGP_CMDSIZE       3
 365
 366 #define R300_AT_CMD_0           0
 367 #define R300_AT_ALPHA_TEST      1
 368 #define R300_AT_UNKNOWN         2
 369 #define R300_AT_CMDSIZE         3
 370
 371 #define R300_BLD_CMD_0          0
 372 #define R300_BLD_CBLEND         1
 373 #define R300_BLD_ABLEND         2
 374 #define R300_BLD_CMDSIZE        3
 375
 376 #define R300_CMK_CMD_0          0
 377 #define R300_CMK_COLORMASK      1
 378 #define R300_CMK_CMDSIZE        2
 379
 380 #define R300_CB_CMD_0           0
 381 #define R300_CB_OFFSET          1
 382 #define R300_CB_CMD_1           2
 383 #define R300_CB_PITCH           3
 384 #define R300_CB_CMDSIZE         4
 385
 386 #define R300_ZS_CMD_0           0
 387 #define R300_ZS_CNTL_0          1
 388 #define R300_ZS_CNTL_1          2
 389 #define R300_ZS_CNTL_2          3
 390 #define R300_ZS_CMDSIZE         4
 391
 392 #define R300_ZB_CMD_0           0
 393 #define R300_ZB_OFFSET          1
 394 #define R300_ZB_PITCH           2
 395 #define R300_ZB_CMDSIZE         3
 396
 397 #define R300_VPI_CMD_0          0
 398 #define R300_VPI_INSTR_0        1
 399 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 400
 401 #define R300_VPP_CMD_0          0
 402 #define R300_VPP_PARAM_0        1
 403 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 404
 405 #define R300_VPS_CMD_0          0
 406 #define R300_VPS_ZERO_0         1
 407 #define R300_VPS_ZERO_1         2
 408 #define R300_VPS_POINTSIZE      3
 409 #define R300_VPS_ZERO_3         4
 410 #define R300_VPS_CMDSIZE        5
 411
 412         /* the layout is common for all fields inside tex */
 413 #define R300_TEX_CMD_0          0
 414 #define R300_TEX_VALUE_0        1
 415 /* We don't really use this, instead specify mtu+1 dynamically
 416 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 417 */
 418
 419 /**
 420  * Cache for hardware register state.
 421  */
 422 struct r300_hw_state {
 423         struct r300_state_atom atomlist;
 424
 425         GLboolean       is_dirty;
 426         GLboolean       all_dirty;
 427         int             max_state_size; /* in dwords */
 428
 429         struct r300_state_atom vpt;     /* viewport (1D98) */
 430         struct r300_state_atom unk2080; /* (2080) */
 431         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 432         struct r300_state_atom vte;     /* (20B0) */
 433         struct r300_state_atom unk2134; /* (2134) */
 434         struct r300_state_atom unk2140; /* (2140) */
 435         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 436         struct r300_state_atom vic;     /* vap input control (2180) */
 437         struct r300_state_atom unk21DC; /* (21DC) */
 438         struct r300_state_atom unk221C; /* (221C) */
 439         struct r300_state_atom unk2220; /* (2220) */
 440         struct r300_state_atom unk2288; /* (2288) */
 441         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 442         struct r300_state_atom gb_enable; /* (4008) */
 443         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 444         struct r300_state_atom unk4200; /* (4200) */
 445         struct r300_state_atom unk4214; /* (4214) */
 446         struct r300_state_atom ps;      /* pointsize (421C) */
 447         struct r300_state_atom unk4230; /* (4230) */
 448         struct r300_state_atom lcntl;   /* line control */
 449         struct r300_state_atom unk4260; /* (4260) */
 450         struct r300_state_atom unk4274; /* (4274) */
 451         struct r300_state_atom unk4288; /* (4288) */
 452         struct r300_state_atom fogp;    /* fog parameters (4294) */
 453         struct r300_state_atom unk429C; /* (429C) */
 454         struct r300_state_atom unk42A0; /* (42A0) */
 455         struct r300_state_atom zbs;     /* zbias (42A4) */
 456         struct r300_state_atom unk42B4; /* (42B4) */
 457         struct r300_state_atom cul;     /* cull cntl (42B8) */
 458         struct r300_state_atom unk42C0; /* (42C0) */
 459         struct r300_state_atom rc;      /* rs control (4300) */
 460         struct r300_state_atom ri;      /* rs interpolators (4310) */
 461         struct r300_state_atom rr;      /* rs route (4330) */
 462         struct r300_state_atom unk43A4; /* (43A4) */
 463         struct r300_state_atom unk43E8; /* (43E8) */
 464         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 465         struct r300_state_atom fpt;     /* texi - (4620) */
 466         struct r300_state_atom unk46A4; /* (46A4) */
 467         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 468         struct r300_state_atom fogs;    /* fog state (4BC0) */
 469         struct r300_state_atom fogc;    /* fog color (4BC8) */
 470         struct r300_state_atom at;      /* alpha test (4BD4) */
 471         struct r300_state_atom unk4BD8; /* (4BD8) */
 472         struct r300_state_atom fpp;     /* 0x4C00 and following */
 473         struct r300_state_atom unk4E00; /* (4E00) */
 474         struct r300_state_atom bld;     /* blending (4E04) */
 475         struct r300_state_atom cmk;     /* colormask (4E0C) */
 476         struct r300_state_atom unk4E10; /* constant blend color + ??? (4E10) */
 477         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 478         struct r300_state_atom unk4E50; /* (4E50) */
 479         struct r300_state_atom unk4E88; /* (4E88) */
 480         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 481         struct r300_state_atom zs;      /* zstencil control (4F00) */
 482         struct r300_state_atom unk4F10; /* (4F10) */
 483         struct r300_state_atom zb;      /* z buffer (4F20) */
 484         struct r300_state_atom unk4F28; /* (4F28) */
 485         struct r300_state_atom unk4F30; /* (4F30) */
 486         struct r300_state_atom unk4F44; /* (4F44) */
 487         struct r300_state_atom unk4F54; /* (4F54) */
 488
 489         struct r300_state_atom vpi;     /* vp instructions */
 490         struct r300_state_atom vpp;     /* vp parameters */
 491         struct r300_state_atom vps;     /* vertex point size (?) */
 492                 /* 8 texture units */
 493                 /* the state is grouped by function and not by
 494                    texture unit. This makes single unit updates
 495                    really awkward - we are much better off
 496                    updating the whole thing at once */
 497         struct {
 498                 struct r300_state_atom filter;
 499                 struct r300_state_atom unknown1;
 500                 struct r300_state_atom size;
 501                 struct r300_state_atom format;
 502                 struct r300_state_atom pitch;
 503                 struct r300_state_atom offset;
 504                 struct r300_state_atom unknown4;
 505                 struct r300_state_atom border_color;
 506                 } tex;
 507         struct r300_state_atom txe;     /* tex enable (4104) */
 508 };
 509
 510
 511 /**
 512  * This structure holds the command buffer while it is being constructed.
 513  *
 514  * The first batch of commands in the buffer is always the state that needs
 515  * to be re-emitted when the context is lost. This batch can be skipped
 516  * otherwise.
 517  */
 518 struct r300_cmdbuf {
 519         int             size;           /* DWORDs allocated for buffer */
 520         uint32_t*       cmd_buf;
 521         int             count_used;     /* DWORDs filled so far */
 522         int             count_reemit;   /* size of re-emission batch */
 523 };
 524
 525
 526 /**
 527  * State cache
 528  */
 529
 530 struct r300_depthbuffer_state {
 531         GLfloat scale;
 532 };
 533
 534 struct r300_stencilbuffer_state {
 535         GLuint clear;
 536         GLboolean hw_stencil;
 537
 538 };
 539
 540 struct r300_vap_reg_state {
 541            /* input register assigments */
 542            int i_coords;
 543            int i_normal;
 544            int i_color[2];
 545            int i_fog;
 546            int i_tex[R300_MAX_TEXTURE_UNITS];
 547            int i_attrib[_TNL_NUM_GENERIC];
 548            int i_index;
 549            int i_pointsize;
 550         };
 551
 552 /* Vertex shader state */
 553
 554 /* Perhaps more if we store programs in vmem? */
 555 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 556 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 557
 558 /* Can be tested with colormat currently. */
 559 #define VSF_MAX_FRAGMENT_TEMPS (14)
 560
 561
 562 struct r300_vertex_shader_fragment {
 563         int length;
 564         union {
 565                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 566                 float f[VSF_MAX_FRAGMENT_LENGTH];
 567                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH/4];
 568                 } body;
 569         };
 570
 571 #define VSF_DEST_PROGRAM        0x0
 572 #define VSF_DEST_MATRIX0        0x200
 573 #define VSF_DEST_MATRIX1        0x204
 574 #define VSF_DEST_MATRIX2        0x208
 575 #define VSF_DEST_VECTOR0        0x20c
 576 #define VSF_DEST_VECTOR1        0x20d
 577 #define VSF_DEST_UNKNOWN1       0x400
 578 #define VSF_DEST_UNKNOWN2       0x406
 579
 580 struct r300_vertex_shader_state {
 581         struct r300_vertex_shader_fragment program;
 582
 583         /* a bit of a waste - each uses only a subset of allocated space..
 584             but easier to program */
 585         struct r300_vertex_shader_fragment matrix[3];
 586         struct r300_vertex_shader_fragment vector[2];
 587
 588         struct r300_vertex_shader_fragment unknown1;
 589         struct r300_vertex_shader_fragment unknown2;
 590
 591         int program_start;
 592         int unknown_ptr1;  /* pointer within program space */
 593         int program_end;
 594
 595         int param_offset;
 596         int param_count;
 597
 598         int unknown_ptr2;  /* pointer within program space */
 599         int unknown_ptr3;  /* pointer within program space */
 600         };
 601
 602 extern int hw_tcl_on;
 603
 604 #define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 605
 606 /* Should but doesnt work */
 607 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 608
 609 //#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && (OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit)))) :
 610 //      (r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit))))
 611 //#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit))) :
 612 //      ctx->Texture.Unit[unit]._ReallyEnabled && r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit)))
 613
 614 #define TMU_ENABLED(ctx, unit) (ctx->Texture.Unit[unit]._ReallyEnabled)
 615
 616 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 617  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 618  */
 619 struct r300_vertex_program {
 620         struct gl_vertex_program mesa_program; /* Must be first */
 621         int translated;
 622
 623         struct r300_vertex_shader_fragment program;
 624         struct r300_vertex_shader_fragment params;
 625
 626         int pos_end;
 627         int num_temporaries; /* Number of temp vars used by program */
 628         int inputs[VERT_ATTRIB_MAX];
 629         int outputs[VERT_RESULT_MAX];
 630         int native;
 631         int ref_count;
 632         int use_ref_count;
 633 };
 634
 635 #define PFS_MAX_ALU_INST        64
 636 #define PFS_MAX_TEX_INST        64
 637 #define PFS_MAX_TEX_INDIRECT 4
 638 #define PFS_NUM_TEMP_REGS       32
 639 #define PFS_NUM_CONST_REGS      16
 640
 641 /* Tracking data for Mesa registers */
 642 struct reg_acc {
 643        int reg;        /* Assigned hw temp */
 644        unsigned int refcount; /* Number of uses by mesa program */
 645 };
 646
 647 struct r300_pfs_compile_state {
 648        int v_pos, s_pos;       /* highest ALU slots used */
 649
 650        /* Track some information gathered during opcode
 651         * construction.
 652         *
 653         * NOTE: Data is only set by the code, and isn't used yet.
 654         */
 655        struct {
 656                int vsrc[3];
 657                int ssrc[3];
 658                int umask;
 659        } slot[PFS_MAX_ALU_INST];
 660
 661        /* Used to map Mesa's inputs/temps onto hardware temps */
 662        int temp_in_use;
 663        struct reg_acc temps[PFS_NUM_TEMP_REGS];
 664        struct reg_acc inputs[32]; /* don't actually need 32... */
 665
 666        /* Track usage of hardware temps, for register allocation,
 667         * indirection detection, etc. */
 668        int hwreg_in_use;
 669        GLuint used_in_node;
 670        GLuint dest_in_node;
 671 };
 672
 673 struct r300_fragment_program {
 674         struct gl_fragment_program mesa_program;
 675
 676         GLcontext *ctx;
 677         GLboolean translated;
 678         GLboolean error;
 679         struct r300_pfs_compile_state *cs;
 680
 681         struct {
 682                 int length;
 683                 GLuint inst[PFS_MAX_TEX_INST];
 684         } tex;
 685
 686         struct {
 687                 struct {
 688                         GLuint inst0;
 689                         GLuint inst1;
 690                         GLuint inst2;
 691                         GLuint inst3;
 692                 } inst[PFS_MAX_ALU_INST];
 693         } alu;
 694
 695         struct {
 696                 int tex_offset;
 697                 int tex_end;
 698                 int alu_offset;
 699                 int alu_end;
 700                 int flags;
 701         } node[4];
 702         int cur_node;
 703         int first_node_has_tex;
 704
 705         int alu_offset;
 706         int alu_end;
 707         int tex_offset;
 708         int tex_end;
 709
 710         /* Hardware constants */
 711         GLfloat constant[PFS_NUM_CONST_REGS][4];
 712         int const_nr;
 713
 714         /* Tracked parameters */
 715         struct {
 716                 int idx;                        /* hardware index */
 717                 GLfloat *values;        /* pointer to values */
 718         } param[PFS_NUM_CONST_REGS];
 719         int param_nr;
 720         GLboolean params_uptodate;
 721
 722         int max_temp_idx;
 723 };
 724
 725 #define R300_MAX_AOS_ARRAYS             16
 726
 727 #define AOS_FORMAT_FLOAT        1
 728 #define AOS_FORMAT_UBYTE        2
 729 #define AOS_FORMAT_FLOAT_COLOR  3
 730
 731 #define REG_COORDS      0
 732 #define REG_COLOR0      1
 733 #define REG_TEX0        2
 734
 735 struct dt {
 736         GLint size;
 737         GLenum type;
 738         GLsizei stride;
 739         void *data;
 740 };
 741
 742 struct radeon_vertex_buffer {
 743         int Count;
 744         void *Elts;
 745         int elt_size;
 746         int elt_min, elt_max; /* debug */
 747
 748         struct dt AttribPtr[VERT_ATTRIB_MAX];
 749
 750         struct tnl_prim  *Primitive;
 751         GLuint      PrimitiveCount;
 752         GLint LockFirst;
 753         GLsizei LockCount;
 754         int lock_uptodate;
 755 };
 756
 757 struct r300_aos_rec {
 758         GLuint offset;
 759         int element_size; /* in dwords */
 760         int stride;       /* distance between elements, in dwords */
 761
 762         int format;
 763
 764         int ncomponents; /* number of components - between 1 and 4, inclusive */
 765
 766         int reg; /* which register they are assigned to. */
 767
 768         };
 769
 770 struct r300_state {
 771         struct r300_depthbuffer_state depth;
 772         struct r300_texture_state texture;
 773         struct r300_vap_reg_state vap_reg;
 774         struct r300_vertex_shader_state vertex_shader;
 775         struct r300_pfs_compile_state pfs_compile;
 776         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 777         int aos_count;
 778         struct radeon_vertex_buffer VB;
 779
 780         GLuint *Elts;
 781         struct r300_dma_region elt_dma;
 782
 783         DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for.
 784                                  They are the same as tnl->render_inputs for fixed pipeline */
 785
 786         struct {
 787                 int transform_offset;  /* Transform matrix offset, -1 if none */
 788                 } vap_param;  /* vertex processor parameter allocation - tells where to write parameters */
 789
 790         struct r300_stencilbuffer_state stencil;
 791
 792 };
 793
 794 #define R300_FALLBACK_NONE 0
 795 #define R300_FALLBACK_TCL 1
 796 #define R300_FALLBACK_RAST 2
 797
 798 /**
 799  * R300 context structure.
 800  */
 801 struct r300_context {
 802         struct radeon_context radeon; /* parent class, must be first */
 803
 804         struct r300_hw_state hw;
 805         struct r300_cmdbuf cmdbuf;
 806         struct r300_state state;
 807         struct gl_vertex_program *curr_vp;
 808
 809         /* Vertex buffers
 810          */
 811         struct r300_dma dma;
 812         GLboolean save_on_next_unlock;
 813         GLuint NewGLState;
 814
 815         /* Texture object bookkeeping
 816          */
 817         unsigned nr_heaps;
 818         driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
 819         driTextureObject swapped;
 820         int texture_depth;
 821         float initialMaxAnisotropy;
 822
 823         /* Clientdata textures;
 824          */
 825         GLuint prefer_gart_client_texturing;
 826
 827 #ifdef USER_BUFFERS
 828         struct radeon_memory_manager *rmm;
 829         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 830         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 831 #endif
 832
 833         GLboolean texmicrotile;
 834         GLboolean span_dlocking;
 835 };
 836
 837 struct r300_buffer_object {
 838         struct gl_buffer_object mesa_obj;
 839         int id;
 840 };
 841
 842 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 843
 844 static __inline GLuint r300PackColor( GLuint cpp,
 845                                         GLubyte r, GLubyte g,
 846                                         GLubyte b, GLubyte a )
 847 {
 848    switch ( cpp ) {
 849    case 2:
 850       return PACK_COLOR_565( r, g, b );
 851    case 4:
 852       return PACK_COLOR_8888( r, g, b, a );
 853    default:
 854       return 0;
 855    }
 856 }
 857 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 858 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 859                                    __DRIcontextPrivate * driContextPriv,
 860                                    void *sharedContextPrivate);
 861
 862 void r300_translate_vertex_shader(struct r300_vertex_program *vp);
 863 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 864 extern int r300VertexProgUpdateParams(GLcontext *ctx, struct r300_vertex_program *vp, float *dst);
 865 extern int r300Fallback(GLcontext *ctx);
 866
 867 extern void radeon_vb_to_rvb(r300ContextPtr rmesa, struct radeon_vertex_buffer *rvb, struct vertex_buffer *vb);
 868 extern GLboolean r300_run_vb_render(GLcontext *ctx, struct tnl_pipeline_stage *stage);
 869
 870 #ifdef RADEON_VTXFMT_A
 871 extern void radeon_init_vtxfmt_a(r300ContextPtr rmesa);
 872 #endif
 873
 874 #ifdef HW_VBOS
 875 extern void r300_init_vbo_funcs(struct dd_function_table *functions);
 876 extern void r300_evict_vbos(GLcontext *ctx, int amount);
 877 #endif
 878
 879 #define RADEON_D_CAPTURE 0
 880 #define RADEON_D_PLAYBACK 1
 881 #define RADEON_D_PLAYBACK_RAW 2
 882 #define RADEON_D_T 3
 883
 884 #endif                          /* __R300_CONTEXT_H__ */