src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 #define USE_ARB_F_P 1
  51
  52 struct r300_context;
  53 typedef struct r300_context r300ContextRec;
  54 typedef struct r300_context *r300ContextPtr;
  55
  56 #include "radeon_lock.h"
  57 #include "mm.h"
  58
  59 /* Checkpoint.. for convenience */
  60 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  61 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  62    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  63    with other compilers ... GLUE!
  64 */
  65 #if 1
  66 #define WARN_ONCE(a, ...)       { \
  67         static int warn##__LINE__=1; \
  68         if(warn##__LINE__){ \
  69                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  70                 fprintf(stderr, "File %s function %s line %d\n", \
  71                         __FILE__, __FUNCTION__, __LINE__); \
  72                 fprintf(stderr,  a, ## __VA_ARGS__);\
  73                 fprintf(stderr, "***************************************************************************\n"); \
  74                 warn##__LINE__=0;\
  75                 } \
  76         }
  77 #else
  78 #define WARN_ONCE(a, ...) {}
  79 #endif
  80
  81 typedef GLuint uint32_t;
  82 typedef GLubyte uint8_t;
  83 struct r300_fragment_program;
  84
  85   /* We should probably change types within vertex_shader
  86       and pixel_shader structure later on */
  87 #define CARD32 GLuint
  88 #include "vertex_shader.h"
  89 #if USE_ARB_F_P == 1
  90 #include "r300_fragprog.h"
  91 #else
  92 #include "pixel_shader.h"
  93 #endif
  94 #undef CARD32
  95
  96 static __inline__ uint32_t r300PackFloat32(float fl)
  97 {
  98         union { float fl; uint32_t u; } u;
  99
 100         u.fl = fl;
 101         return u.u;
 102 }
 103
 104
 105 /************ DMA BUFFERS **************/
 106
 107 /* Need refcounting on dma buffers:
 108  */
 109 struct r300_dma_buffer {
 110         int refcount;           /* the number of retained regions in buf */
 111         drmBufPtr buf;
 112 };
 113
 114 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 115                         (rvb)->address - rmesa->dma.buf0_address +      \
 116                         (rvb)->start)
 117
 118 /* A retained region, eg vertices for indexed vertices.
 119  */
 120 struct r300_dma_region {
 121         struct r300_dma_buffer *buf;
 122         char *address;          /* == buf->address */
 123         int start, end, ptr;    /* offsets from start of buf */
 124
 125     int aos_offset;     /* address in GART memory */
 126     int aos_stride;     /* distance between elements, in dwords */
 127     int aos_size;       /* number of components (1-4) */
 128     int aos_format;     /* format of components */
 129     int aos_reg;        /* VAP register assignment */
 130 };
 131
 132 struct r300_dma {
 133         /* Active dma region.  Allocations for vertices and retained
 134          * regions come from here.  Also used for emitting random vertices,
 135          * these may be flushed by calling flush_current();
 136          */
 137         struct r300_dma_region current;
 138
 139         void (*flush) (r300ContextPtr);
 140
 141         char *buf0_address;     /* start of buf[0], for index calcs */
 142
 143         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 144          * for which a DISCARD command is currently queued in the command buffer.
 145          */
 146         GLuint nr_released_bufs;
 147 };
 148
 149        /* Texture related */
 150
 151 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 152
 153 /* Texture object in locally shared texture space.
 154  */
 155 struct r300_tex_obj {
 156         driTextureObject base;
 157
 158         GLuint bufAddr;         /* Offset to start of locally
 159                                    shared texture block */
 160
 161         GLuint dirty_state;     /* Flags (1 per texunit) for
 162                                    whether or not this texobj
 163                                    has dirty hardware state
 164                                    (pp_*) that needs to be
 165                                    brought into the
 166                                    texunit. */
 167
 168         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 169         /* Six, for the cube faces */
 170
 171
 172         /* hardware register values */
 173         /* Note that R200 has 8 registers per texture and R300 only 7 */
 174         GLuint filter;
 175         GLuint pitch; /* one of the unknown registers.. unknown 1 ?*/
 176         GLuint size;    /* npot only */
 177         GLuint format;
 178         GLuint offset;  /* Image location in the card's address space.
 179                                    All cube faces follow. */
 180         GLuint unknown4;
 181         GLuint unknown5;
 182         /* end hardware registers */
 183
 184         /* registers computed by r200 code - keep them here to
 185            compare against what is actually written.
 186
 187            to be removed later.. */
 188         GLuint pp_border_color;
 189         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 190         GLuint format_x;
 191
 192
 193         GLboolean border_fallback;
 194 };
 195
 196 struct r300_texture_env_state {
 197         r300TexObjPtr texobj;
 198         GLenum format;
 199         GLenum envMode;
 200 };
 201
 202 #define R300_MAX_TEXTURE_UNITS 8
 203
 204 struct r300_texture_state {
 205         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 206         int tc_count; /* number of incoming texture coordinates from VAP */
 207 };
 208
 209 /**
 210  * A block of hardware state.
 211  *
 212  * When check returns non-zero, the returned number of dwords must be
 213  * copied verbatim into the command buffer in order to update a state atom
 214  * when it is dirty.
 215  */
 216 struct r300_state_atom {
 217         struct r300_state_atom *next, *prev;
 218         const char* name;       /* for debug */
 219         int cmd_size;           /* maximum size in dwords */
 220         GLuint idx;             /* index in an array (e.g. textures) */
 221         uint32_t* cmd;
 222         GLboolean dirty;
 223
 224         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 225 };
 226
 227
 228 #define R300_VPT_CMD_0          0
 229 #define R300_VPT_XSCALE         1
 230 #define R300_VPT_XOFFSET        2
 231 #define R300_VPT_YSCALE         3
 232 #define R300_VPT_YOFFSET        4
 233 #define R300_VPT_ZSCALE         5
 234 #define R300_VPT_ZOFFSET        6
 235 #define R300_VPT_CMDSIZE        7
 236
 237 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 238 #define R300_VIR_CNTL_0         1
 239 #define R300_VIR_CNTL_1         2
 240 #define R300_VIR_CNTL_2         3
 241 #define R300_VIR_CNTL_3         4
 242 #define R300_VIR_CNTL_4         5
 243 #define R300_VIR_CNTL_5         6
 244 #define R300_VIR_CNTL_6         7
 245 #define R300_VIR_CNTL_7         8
 246 #define R300_VIR_CMDSIZE        9
 247
 248 #define R300_VIC_CMD_0          0
 249 #define R300_VIC_CNTL_0         1
 250 #define R300_VIC_CNTL_1         2
 251 #define R300_VIC_CMDSIZE        3
 252
 253 #define R300_VOF_CMD_0          0
 254 #define R300_VOF_CNTL_0         1
 255 #define R300_VOF_CNTL_1         2
 256 #define R300_VOF_CMDSIZE        3
 257
 258
 259 #define R300_PVS_CMD_0          0
 260 #define R300_PVS_CNTL_1         1
 261 #define R300_PVS_CNTL_2         2
 262 #define R300_PVS_CNTL_3         3
 263 #define R300_PVS_CMDSIZE        4
 264
 265 #define R300_GB_MISC_CMD_0              0
 266 #define R300_GB_MISC_MSPOS_0            1
 267 #define R300_GB_MISC_MSPOS_1            2
 268 #define R300_GB_MISC_TILE_CONFIG        3
 269 #define R300_GB_MISC_SELECT             4
 270 #define R300_GB_MISC_AA_CONFIG          5
 271 #define R300_GB_MISC_CMDSIZE            6
 272
 273 #define R300_TXE_CMD_0          0
 274 #define R300_TXE_ENABLE         1
 275 #define R300_TXE_CMDSIZE        2
 276
 277 #define R300_PS_CMD_0           0
 278 #define R300_PS_POINTSIZE       1
 279 #define R300_PS_CMDSIZE         2
 280
 281 #define R300_ZBS_CMD_0          0
 282 #define R300_ZBS_T_FACTOR       1
 283 #define R300_ZBS_T_CONSTANT     2
 284 #define R300_ZBS_W_FACTOR       3
 285 #define R300_ZBS_W_CONSTANT     4
 286 #define R300_ZBS_CMDSIZE        5
 287
 288 #define R300_CUL_CMD_0          0
 289 #define R300_CUL_CULL           1
 290 #define R300_CUL_CMDSIZE        2
 291
 292 #define R300_RC_CMD_0           0
 293 #define R300_RC_CNTL_0          1
 294 #define R300_RC_CNTL_1          2
 295 #define R300_RC_CMDSIZE         3
 296
 297 #define R300_RI_CMD_0           0
 298 #define R300_RI_INTERP_0        1
 299 #define R300_RI_INTERP_1        2
 300 #define R300_RI_INTERP_2        3
 301 #define R300_RI_INTERP_3        4
 302 #define R300_RI_INTERP_4        5
 303 #define R300_RI_INTERP_5        6
 304 #define R300_RI_INTERP_6        7
 305 #define R300_RI_INTERP_7        8
 306 #define R300_RI_CMDSIZE         9
 307
 308 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 309 #define R300_RR_ROUTE_0         1
 310 #define R300_RR_ROUTE_1         2
 311 #define R300_RR_ROUTE_2         3
 312 #define R300_RR_ROUTE_3         4
 313 #define R300_RR_ROUTE_4         5
 314 #define R300_RR_ROUTE_5         6
 315 #define R300_RR_ROUTE_6         7
 316 #define R300_RR_ROUTE_7         8
 317 #define R300_RR_CMDSIZE         9
 318
 319 #define R300_FP_CMD_0           0
 320 #define R300_FP_CNTL0           1
 321 #define R300_FP_CNTL1           2
 322 #define R300_FP_CNTL2           3
 323 #define R300_FP_CMD_1           4
 324 #define R300_FP_NODE0           5
 325 #define R300_FP_NODE1           6
 326 #define R300_FP_NODE2           7
 327 #define R300_FP_NODE3           8
 328 #define R300_FP_CMDSIZE         9
 329
 330 #define R300_FPT_CMD_0          0
 331 #define R300_FPT_INSTR_0        1
 332 #define R300_FPT_CMDSIZE        65
 333
 334 #define R300_FPI_CMD_0          0
 335 #define R300_FPI_INSTR_0        1
 336 #define R300_FPI_CMDSIZE        65
 337
 338 #define R300_FPP_CMD_0          0
 339 #define R300_FPP_PARAM_0        1
 340 #define R300_FPP_CMDSIZE        (32*4+1)
 341
 342 #define R300_AT_CMD_0           0
 343 #define R300_AT_ALPHA_TEST      1
 344 #define R300_AT_UNKNOWN         2
 345 #define R300_AT_CMDSIZE         3
 346
 347 #define R300_BLD_CMD_0          0
 348 #define R300_BLD_CBLEND         1
 349 #define R300_BLD_ABLEND         2
 350 #define R300_BLD_CMDSIZE        3
 351
 352 #define R300_CMK_CMD_0          0
 353 #define R300_CMK_COLORMASK      1
 354 #define R300_CMK_CMDSIZE        2
 355
 356 #define R300_CB_CMD_0           0
 357 #define R300_CB_OFFSET          1
 358 #define R300_CB_CMD_1           2
 359 #define R300_CB_PITCH           3
 360 #define R300_CB_CMDSIZE         4
 361
 362 #define R300_ZS_CMD_0           0
 363 #define R300_ZS_CNTL_0          1
 364 #define R300_ZS_CNTL_1          2
 365 #define R300_ZS_CNTL_2          3
 366 #define R300_ZS_CMDSIZE         4
 367
 368 #define R300_ZB_CMD_0           0
 369 #define R300_ZB_OFFSET          1
 370 #define R300_ZB_PITCH           2
 371 #define R300_ZB_CMDSIZE         3
 372
 373 #define R300_VPI_CMD_0          0
 374 #define R300_VPI_INSTR_0        1
 375 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 376
 377 #define R300_VPP_CMD_0          0
 378 #define R300_VPP_PARAM_0        1
 379 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 380
 381 #define R300_VPS_CMD_0          0
 382 #define R300_VPS_ZERO_0         1
 383 #define R300_VPS_ZERO_1         2
 384 #define R300_VPS_POINTSIZE      3
 385 #define R300_VPS_ZERO_3         4
 386 #define R300_VPS_CMDSIZE        5
 387
 388         /* the layout is common for all fields inside tex */
 389 #define R300_TEX_CMD_0          0
 390 #define R300_TEX_VALUE_0        1
 391 /* We don't really use this, instead specify mtu+1 dynamically
 392 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 393 */
 394
 395 /**
 396  * Cache for hardware register state.
 397  */
 398 struct r300_hw_state {
 399         struct r300_state_atom atomlist;
 400
 401         GLboolean       is_dirty;
 402         GLboolean       all_dirty;
 403         int             max_state_size; /* in dwords */
 404
 405         struct r300_state_atom vpt;     /* viewport (1D98) */
 406         struct r300_state_atom unk2080; /* (2080) */
 407         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 408         struct r300_state_atom vte;     /* (20B0) */
 409         struct r300_state_atom unk2134; /* (2134) */
 410         struct r300_state_atom unk2140; /* (2140) */
 411         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 412         struct r300_state_atom vic;     /* vap input control (2180) */
 413         struct r300_state_atom unk21DC; /* (21DC) */
 414         struct r300_state_atom unk221C; /* (221C) */
 415         struct r300_state_atom unk2220; /* (2220) */
 416         struct r300_state_atom unk2288; /* (2288) */
 417         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 418         struct r300_state_atom gb_enable; /* (4008) */
 419         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 420         struct r300_state_atom unk4200; /* (4200) */
 421         struct r300_state_atom unk4214; /* (4214) */
 422         struct r300_state_atom ps;      /* pointsize (421C) */
 423         struct r300_state_atom unk4230; /* (4230) */
 424         struct r300_state_atom lcntl;   /* line control */
 425         struct r300_state_atom unk4260; /* (4260) */
 426         struct r300_state_atom unk4274; /* (4274) */
 427         struct r300_state_atom unk4288; /* (4288) */
 428         struct r300_state_atom unk42A0; /* (42A0) */
 429         struct r300_state_atom zbs;     /* zbias (42A4) */
 430         struct r300_state_atom unk42B4; /* (42B4) */
 431         struct r300_state_atom cul;     /* cull cntl (42B8) */
 432         struct r300_state_atom unk42C0; /* (42C0) */
 433         struct r300_state_atom rc;      /* rs control (4300) */
 434         struct r300_state_atom ri;      /* rs interpolators (4310) */
 435         struct r300_state_atom rr;      /* rs route (4330) */
 436         struct r300_state_atom unk43A4; /* (43A4) */
 437         struct r300_state_atom unk43E8; /* (43E8) */
 438         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 439         struct r300_state_atom fpt;     /* texi - (4620) */
 440         struct r300_state_atom unk46A4; /* (46A4) */
 441         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 442         struct r300_state_atom unk4BC0; /* (4BC0) */
 443         struct r300_state_atom unk4BC8; /* (4BC8) */
 444         struct r300_state_atom at;      /* alpha test (4BD4) */
 445         struct r300_state_atom unk4BD8; /* (4BD8) */
 446         struct r300_state_atom fpp;     /* 0x4C00 and following */
 447         struct r300_state_atom unk4E00; /* (4E00) */
 448         struct r300_state_atom bld;     /* blending (4E04) */
 449         struct r300_state_atom cmk;     /* colormask (4E0C) */
 450         struct r300_state_atom unk4E10; /* (4E10) */
 451         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 452         struct r300_state_atom unk4E50; /* (4E50) */
 453         struct r300_state_atom unk4E88; /* (4E88) */
 454         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 455         struct r300_state_atom zs;      /* zstencil control (4F00) */
 456         struct r300_state_atom unk4F10; /* (4F10) */
 457         struct r300_state_atom zb;      /* z buffer (4F20) */
 458         struct r300_state_atom unk4F28; /* (4F28) */
 459         struct r300_state_atom unk4F30; /* (4F30) */
 460         struct r300_state_atom unk4F44; /* (4F44) */
 461         struct r300_state_atom unk4F54; /* (4F54) */
 462
 463         struct r300_state_atom vpi;     /* vp instructions */
 464         struct r300_state_atom vpp;     /* vp parameters */
 465         struct r300_state_atom vps;     /* vertex point size (?) */
 466                 /* 8 texture units */
 467                 /* the state is grouped by function and not by
 468                    texture unit. This makes single unit updates
 469                    really awkward - we are much better off
 470                    updating the whole thing at once */
 471         struct {
 472                 struct r300_state_atom filter;
 473                 struct r300_state_atom unknown1;
 474                 struct r300_state_atom size;
 475                 struct r300_state_atom format;
 476                 struct r300_state_atom offset;
 477                 struct r300_state_atom unknown4;
 478                 struct r300_state_atom border_color;
 479                 } tex;
 480         struct r300_state_atom txe;     /* tex enable (4104) */
 481 };
 482
 483
 484 /**
 485  * This structure holds the command buffer while it is being constructed.
 486  *
 487  * The first batch of commands in the buffer is always the state that needs
 488  * to be re-emitted when the context is lost. This batch can be skipped
 489  * otherwise.
 490  */
 491 struct r300_cmdbuf {
 492         int             size;           /* DWORDs allocated for buffer */
 493         uint32_t*       cmd_buf;
 494         int             count_used;     /* DWORDs filled so far */
 495         int             count_reemit;   /* size of re-emission batch */
 496 };
 497
 498
 499 /**
 500  * State cache
 501  */
 502
 503 struct r300_depthbuffer_state {
 504         GLfloat scale;
 505 };
 506
 507 struct r300_stencilbuffer_state {
 508         GLuint clear;
 509         GLboolean hw_stencil;
 510
 511 };
 512
 513 struct r300_vap_reg_state {
 514            /* input register assigments */
 515            int i_coords;
 516            int i_normal;
 517            int i_color[2];
 518            int i_fog;
 519            int i_tex[R300_MAX_TEXTURE_UNITS];
 520            int i_index;
 521            int i_pointsize;
 522         };
 523
 524 /* Vertex shader state */
 525
 526 /* Perhaps more if we store programs in vmem? */
 527 #define VSF_MAX_FRAGMENT_LENGTH (256*4)
 528
 529 /* Can be tested with colormat currently. */
 530 #define VSF_MAX_FRAGMENT_TEMPS (14)
 531
 532
 533 struct r300_vertex_shader_fragment {
 534         int length;
 535         union {
 536                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 537                 float f[VSF_MAX_FRAGMENT_LENGTH];
 538                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH/4];
 539                 } body;
 540         };
 541
 542 #define VSF_DEST_PROGRAM        0x0
 543 #define VSF_DEST_MATRIX0        0x200
 544 #define VSF_DEST_MATRIX1        0x204
 545 #define VSF_DEST_MATRIX2        0x208
 546 #define VSF_DEST_VECTOR0        0x20c
 547 #define VSF_DEST_VECTOR1        0x20d
 548 #define VSF_DEST_UNKNOWN1       0x400
 549 #define VSF_DEST_UNKNOWN2       0x406
 550
 551 struct r300_vertex_shader_state {
 552         struct r300_vertex_shader_fragment program;
 553
 554         /* a bit of a waste - each uses only a subset of allocated space..
 555             but easier to program */
 556         struct r300_vertex_shader_fragment matrix[3];
 557         struct r300_vertex_shader_fragment vector[2];
 558
 559         struct r300_vertex_shader_fragment unknown1;
 560         struct r300_vertex_shader_fragment unknown2;
 561
 562         int program_start;
 563         int unknown_ptr1;  /* pointer within program space */
 564         int program_end;
 565
 566         int param_offset;
 567         int param_count;
 568
 569         int unknown_ptr2;  /* pointer within program space */
 570         int unknown_ptr3;  /* pointer within program space */
 571         };
 572
 573 extern int hw_tcl_on;
 574
 575 #define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Enabled ? ctx->VertexProgram.Current : ctx->_TnlProgram)
 576
 577 //#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && (OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit)))) :
 578 //      (r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit))))
 579 #define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit))) : \
 580         ctx->Texture.Unit[unit]._ReallyEnabled && r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit)))
 581
 582 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 583  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 584  */
 585 struct r300_vertex_program {
 586         struct vertex_program mesa_program; /* Must be first */
 587         int translated;
 588
 589         struct r300_vertex_shader_fragment program;
 590         struct r300_vertex_shader_fragment params;
 591
 592         int pos_end;
 593         unsigned long num_temporaries; /* Number of temp vars used by program */
 594         int inputs[VERT_ATTRIB_MAX];
 595         int outputs[VERT_RESULT_MAX];
 596 };
 597
 598 #if USE_ARB_F_P == 1
 599 #define PFS_MAX_ALU_INST        64
 600 #define PFS_MAX_TEX_INST        64
 601 #define PFS_MAX_TEX_INDIRECT 4
 602 #define PFS_NUM_TEMP_REGS       32
 603 #define PFS_NUM_CONST_REGS      32
 604 struct r300_fragment_program {
 605         struct fragment_program mesa_program;
 606
 607         GLcontext *ctx;
 608         GLboolean translated;
 609         GLboolean error;
 610
 611         struct {
 612                 int length;
 613                 GLuint inst[PFS_MAX_TEX_INST];
 614         } tex;
 615
 616         struct {
 617                 struct {
 618                         GLuint inst0;
 619                         GLuint inst1;
 620                         GLuint inst2;
 621                         GLuint inst3;
 622                 } inst[PFS_MAX_ALU_INST];
 623         } alu;
 624         int v_pos;
 625         int s_pos;
 626
 627         struct {
 628                 int tex_offset;
 629                 int tex_end;
 630                 int alu_offset;
 631                 int alu_end;
 632         } node[4];
 633         int cur_node;
 634         int first_node_has_tex;
 635
 636         int alu_offset;
 637         int alu_end;
 638         int tex_offset;
 639         int tex_end;
 640
 641         /* Hardware constants */
 642         GLfloat constant[PFS_NUM_CONST_REGS][4];
 643         int const_nr;
 644
 645         /* Tracked parameters */
 646         struct {
 647                 int idx;                        /* hardware index */
 648                 GLfloat *values;        /* pointer to values */
 649         } param[PFS_NUM_CONST_REGS];
 650         int param_nr;
 651         GLboolean params_uptodate;
 652
 653         GLuint temps[PFS_NUM_TEMP_REGS];
 654         int temp_in_use;
 655         GLuint used_in_node;
 656         GLuint dest_in_node;
 657         GLuint inputs[32]; /* don't actually need 32... */
 658
 659         int hwreg_in_use;
 660         int max_temp_idx;
 661 };
 662
 663 #else
 664 /* 64 appears to be the maximum */
 665 #define PSF_MAX_PROGRAM_LENGTH 64
 666
 667 struct r300_pixel_shader_program {
 668         struct {
 669                 int length;
 670                 GLuint inst[PSF_MAX_PROGRAM_LENGTH];
 671                 } tex;
 672
 673         /* ALU intructions (logic and integer) */
 674         struct {
 675                 int length;
 676                 struct {
 677                         GLuint inst0;
 678                         GLuint inst1;
 679                         GLuint inst2;
 680                         GLuint inst3;
 681                         } inst[PSF_MAX_PROGRAM_LENGTH];
 682                 } alu;
 683
 684         /* node information */
 685         /* nodes are used to synchronize ALU and TEX streams */
 686         /* There could be up to 4 nodes each consisting of
 687            a number of TEX instructions followed by some ALU
 688            instructions */
 689         /* the last node of a program should always be node3 */
 690         struct {
 691                 int tex_offset;
 692                 int tex_end;
 693                 int alu_offset;
 694                 int alu_end;
 695                 } node[4];
 696
 697         int active_nodes;       /* must be between 1 and 4, inclusive */
 698         int first_node_has_tex;  /* other nodes always have it */
 699
 700         int temp_register_count;  /* magic value goes into PFS_CNTL_1 */
 701
 702         /* entire program */
 703         int tex_offset;
 704         int tex_end;
 705         int alu_offset;
 706         int alu_end;
 707
 708         };
 709
 710 #define MAX_PIXEL_SHADER_PARAMS 32
 711 struct r300_pixel_shader_state {
 712         struct r300_pixel_shader_program program;
 713
 714         int translated;
 715         int have_sample;
 716         GLuint color_reg;
 717         GLuint src_previous;
 718
 719         /* parameters */
 720         int param_length;  /* to limit the number of unnecessary writes */
 721         struct {
 722                 float x;
 723                 float y;
 724                 float z;
 725                 float w;
 726                 } param[MAX_PIXEL_SHADER_PARAMS];
 727         };
 728 #endif // USE_ARB_F_P
 729
 730 /* 8 is somewhat bogus... it is probably something like 24 */
 731 #define R300_MAX_AOS_ARRAYS             16
 732
 733 #define AOS_FORMAT_FLOAT        1
 734 #define AOS_FORMAT_UBYTE        2
 735 #define AOS_FORMAT_FLOAT_COLOR  3
 736
 737 #define REG_COORDS      0
 738 #define REG_COLOR0      1
 739 #define REG_TEX0        2
 740
 741 struct r300_aos_rec {
 742         GLuint offset;
 743         int element_size; /* in dwords */
 744         int stride;       /* distance between elements, in dwords */
 745
 746         int format;
 747
 748         int ncomponents; /* number of components - between 1 and 4, inclusive */
 749
 750         int reg; /* which register they are assigned to. */
 751
 752         };
 753
 754 struct r300_state {
 755         struct r300_depthbuffer_state depth;
 756         struct r300_texture_state texture;
 757         struct r300_vap_reg_state vap_reg;
 758         struct r300_vertex_shader_state vertex_shader;
 759 #if USE_ARB_F_P == 0
 760         struct r300_pixel_shader_state pixel_shader;
 761 #endif
 762         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 763         int aos_count;
 764
 765         GLuint *Elts;
 766         struct r300_dma_region elt_dma;
 767
 768         GLuint render_inputs; /* actual render inputs that R300 was configured for.
 769                                  They are the same as tnl->render_inputs for fixed pipeline */
 770
 771         struct {
 772                 int transform_offset;  /* Transform matrix offset, -1 if none */
 773                 } vap_param;  /* vertex processor parameter allocation - tells where to write parameters */
 774
 775         struct r300_stencilbuffer_state stencil;
 776
 777 };
 778
 779
 780 /**
 781  * R300 context structure.
 782  */
 783 struct r300_context {
 784         struct radeon_context radeon; /* parent class, must be first */
 785
 786         struct r300_hw_state hw;
 787         struct r300_cmdbuf cmdbuf;
 788         struct r300_state state;
 789
 790         /* Vertex buffers
 791          */
 792         struct r300_dma dma;
 793         GLboolean save_on_next_unlock;
 794
 795         /* Texture object bookkeeping
 796          */
 797         unsigned nr_heaps;
 798         driTexHeap *texture_heaps[R200_NR_TEX_HEAPS];
 799         driTextureObject swapped;
 800         int texture_depth;
 801         float initialMaxAnisotropy;
 802
 803         /* Clientdata textures;
 804          */
 805         GLuint prefer_gart_client_texturing;
 806
 807         /* TCL stuff
 808          */
 809         GLmatrix TexGenMatrix[R300_MAX_TEXTURE_UNITS];
 810         GLboolean recheck_texgen[R300_MAX_TEXTURE_UNITS];
 811         GLboolean TexGenNeedNormals[R300_MAX_TEXTURE_UNITS];
 812         GLuint TexMatEnabled;
 813         GLuint TexMatCompSel;
 814         GLuint TexGenEnabled;
 815         GLuint TexGenInputs;
 816         GLuint TexGenCompSel;
 817         GLmatrix tmpmat;
 818 };
 819
 820 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 821
 822 static __inline GLuint r300PackColor( GLuint cpp,
 823                                         GLubyte r, GLubyte g,
 824                                         GLubyte b, GLubyte a )
 825 {
 826    switch ( cpp ) {
 827    case 2:
 828       return PACK_COLOR_565( r, g, b );
 829    case 4:
 830       return PACK_COLOR_8888( r, g, b, a );
 831    default:
 832       return 0;
 833    }
 834 }
 835 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 836 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 837                                    __DRIcontextPrivate * driContextPriv,
 838                                    void *sharedContextPrivate);
 839
 840 void translate_vertex_shader(struct r300_vertex_program *vp);
 841 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 842 extern void r300VertexProgUpdateParams(GLcontext *ctx, struct r300_vertex_program *vp);
 843
 844 #endif                          /* __R300_CONTEXT_H__ */