src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 struct r300_context;
  51 typedef struct r300_context r300ContextRec;
  52 typedef struct r300_context *r300ContextPtr;
  53
  54 #include "radeon_lock.h"
  55 #include "mm.h"
  56
  57 /* Checkpoint.. for convenience */
  58 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  59 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  60    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  61    with other compilers ... GLUE!
  62 */
  63 #define WARN_ONCE(a, ...)       { \
  64         static int warn##__LINE__=1; \
  65         if(warn##__LINE__){ \
  66                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  67                 fprintf(stderr, "File %s function %s line %d\n", \
  68                         __FILE__, __FUNCTION__, __LINE__); \
  69                 fprintf(stderr,  a, ## __VA_ARGS__);\
  70                 fprintf(stderr, "***************************************************************************\n"); \
  71                 warn##__LINE__=0;\
  72                 } \
  73         }
  74
  75 typedef GLuint uint32_t;
  76 typedef GLubyte uint8_t;
  77
  78   /* We should probably change types within vertex_shader
  79       and pixel_shader structure later on */
  80 #define CARD32 GLuint
  81 #include "vertex_shader.h"
  82 #include "pixel_shader.h"
  83 #undef CARD32
  84
  85 static __inline__ uint32_t r300PackFloat32(float fl)
  86 {
  87         union { float fl; uint32_t u; } u;
  88
  89         u.fl = fl;
  90         return u.u;
  91 }
  92
  93
  94 /************ DMA BUFFERS **************/
  95
  96 /* Need refcounting on dma buffers:
  97  */
  98 struct r300_dma_buffer {
  99         int refcount;           /* the number of retained regions in buf */
 100         drmBufPtr buf;
 101 };
 102
 103 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 104                         (rvb)->address - rmesa->dma.buf0_address +      \
 105                         (rvb)->start)
 106
 107 /* A retained region, eg vertices for indexed vertices.
 108  */
 109 struct r300_dma_region {
 110         struct r300_dma_buffer *buf;
 111         char *address;          /* == buf->address */
 112         int start, end, ptr;    /* offsets from start of buf */
 113
 114     int aos_offset;     /* address in GART memory */
 115     int aos_stride;     /* distance between elements, in dwords */
 116     int aos_size;       /* number of components (1-4) */
 117     int aos_format;     /* format of components */
 118     int aos_reg;        /* VAP register assignment */
 119 };
 120
 121 struct r300_dma {
 122         /* Active dma region.  Allocations for vertices and retained
 123          * regions come from here.  Also used for emitting random vertices,
 124          * these may be flushed by calling flush_current();
 125          */
 126         struct r300_dma_region current;
 127
 128         void (*flush) (r300ContextPtr);
 129
 130         char *buf0_address;     /* start of buf[0], for index calcs */
 131
 132         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 133          * for which a DISCARD command is currently queued in the command buffer.
 134          */
 135         GLuint nr_released_bufs;
 136 };
 137
 138        /* Texture related */
 139
 140 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 141
 142 /* Texture object in locally shared texture space.
 143  */
 144 struct r300_tex_obj {
 145         driTextureObject base;
 146
 147         GLuint bufAddr;         /* Offset to start of locally
 148                                    shared texture block */
 149
 150         GLuint dirty_state;     /* Flags (1 per texunit) for
 151                                    whether or not this texobj
 152                                    has dirty hardware state
 153                                    (pp_*) that needs to be
 154                                    brought into the
 155                                    texunit. */
 156
 157         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 158         /* Six, for the cube faces */
 159
 160
 161         /* hardware register values */
 162         /* Note that R200 has 8 registers per texture and R300 only 7 */
 163         GLuint filter;
 164         GLuint pitch; /* one of the unknown registers.. unknown 1 ?*/
 165         GLuint size;    /* npot only */
 166         GLuint format;
 167         GLuint offset;  /* Image location in texmem.
 168                                    All cube faces follow. */
 169         GLuint unknown4;
 170         GLuint unknown5;
 171         /* end hardware registers */
 172
 173         /* registers computed by r200 code - keep them here to
 174            compare against what is actually written.
 175
 176            to be removed later.. */
 177         GLuint pp_border_color;
 178         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 179         GLuint format_x;
 180
 181
 182         GLboolean border_fallback;
 183 };
 184
 185 struct r300_texture_env_state {
 186         r300TexObjPtr texobj;
 187         GLenum format;
 188         GLenum envMode;
 189 };
 190
 191 #define R300_MAX_TEXTURE_UNITS 8
 192
 193 struct r300_texture_state {
 194         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 195         int tc_count; /* number of incoming texture coordinates from VAP */
 196 };
 197
 198 /**
 199  * A block of hardware state.
 200  *
 201  * When check returns non-zero, the returned number of dwords must be
 202  * copied verbatim into the command buffer in order to update a state atom
 203  * when it is dirty.
 204  */
 205 struct r300_state_atom {
 206         struct r300_state_atom *next, *prev;
 207         const char* name;       /* for debug */
 208         int cmd_size;           /* maximum size in dwords */
 209         GLuint idx;             /* index in an array (e.g. textures) */
 210         uint32_t* cmd;
 211         GLboolean dirty;
 212
 213         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 214 };
 215
 216
 217 #define R300_VPT_CMD_0          0
 218 #define R300_VPT_XSCALE         1
 219 #define R300_VPT_XOFFSET        2
 220 #define R300_VPT_YSCALE         3
 221 #define R300_VPT_YOFFSET        4
 222 #define R300_VPT_ZSCALE         5
 223 #define R300_VPT_ZOFFSET        6
 224 #define R300_VPT_CMDSIZE        7
 225
 226 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 227 #define R300_VIR_CNTL_0         1
 228 #define R300_VIR_CNTL_1         2
 229 #define R300_VIR_CNTL_2         3
 230 #define R300_VIR_CNTL_3         4
 231 #define R300_VIR_CNTL_4         5
 232 #define R300_VIR_CNTL_5         6
 233 #define R300_VIR_CNTL_6         7
 234 #define R300_VIR_CNTL_7         8
 235 #define R300_VIR_CMDSIZE        9
 236
 237 #define R300_VIC_CMD_0          0
 238 #define R300_VIC_CNTL_0         1
 239 #define R300_VIC_CNTL_1         2
 240 #define R300_VIC_CMDSIZE        3
 241
 242 #define R300_VOF_CMD_0          0
 243 #define R300_VOF_CNTL_0         1
 244 #define R300_VOF_CNTL_1         2
 245 #define R300_VOF_CMDSIZE        3
 246
 247
 248 #define R300_PVS_CMD_0          0
 249 #define R300_PVS_CNTL_1         1
 250 #define R300_PVS_CNTL_2         2
 251 #define R300_PVS_CNTL_3         3
 252 #define R300_PVS_CMDSIZE        4
 253
 254 #define R300_GB_MISC_CMD_0              0
 255 #define R300_GB_MISC_MSPOS_0            1
 256 #define R300_GB_MISC_MSPOS_1            2
 257 #define R300_GB_MISC_TILE_CONFIG        3
 258 #define R300_GB_MISC_SELECT             4
 259 #define R300_GB_MISC_AA_CONFIG          5
 260 #define R300_GB_MISC_CMDSIZE            6
 261
 262 #define R300_TXE_CMD_0          0
 263 #define R300_TXE_ENABLE         1
 264 #define R300_TXE_CMDSIZE        2
 265
 266 #define R300_PS_CMD_0           0
 267 #define R300_PS_POINTSIZE       1
 268 #define R300_PS_CMDSIZE         2
 269
 270 #define R300_ZBS_CMD_0          0
 271 #define R300_ZBS_T_FACTOR       1
 272 #define R300_ZBS_T_CONSTANT     2
 273 #define R300_ZBS_W_FACTOR       3
 274 #define R300_ZBS_W_CONSTANT     4
 275 #define R300_ZBS_CMDSIZE        5
 276
 277 #define R300_CUL_CMD_0          0
 278 #define R300_CUL_CULL           1
 279 #define R300_CUL_CMDSIZE        2
 280
 281 #define R300_RC_CMD_0           0
 282 #define R300_RC_CNTL_0          1
 283 #define R300_RC_CNTL_1          2
 284 #define R300_RC_CMDSIZE         3
 285
 286 #define R300_RI_CMD_0           0
 287 #define R300_RI_INTERP_0        1
 288 #define R300_RI_INTERP_1        2
 289 #define R300_RI_INTERP_2        3
 290 #define R300_RI_INTERP_3        4
 291 #define R300_RI_INTERP_4        5
 292 #define R300_RI_INTERP_5        6
 293 #define R300_RI_INTERP_6        7
 294 #define R300_RI_INTERP_7        8
 295 #define R300_RI_CMDSIZE         9
 296
 297 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 298 #define R300_RR_ROUTE_0         1
 299 #define R300_RR_ROUTE_1         2
 300 #define R300_RR_ROUTE_2         3
 301 #define R300_RR_ROUTE_3         4
 302 #define R300_RR_ROUTE_4         5
 303 #define R300_RR_ROUTE_5         6
 304 #define R300_RR_ROUTE_6         7
 305 #define R300_RR_ROUTE_7         8
 306 #define R300_RR_CMDSIZE         9
 307
 308 #define R300_FP_CMD_0           0
 309 #define R300_FP_CNTL0           1
 310 #define R300_FP_CNTL1           2
 311 #define R300_FP_CNTL2           3
 312 #define R300_FP_CMD_1           4
 313 #define R300_FP_NODE0           5
 314 #define R300_FP_NODE1           6
 315 #define R300_FP_NODE2           7
 316 #define R300_FP_NODE3           8
 317 #define R300_FP_CMDSIZE         9
 318
 319 #define R300_FPT_CMD_0          0
 320 #define R300_FPT_INSTR_0        1
 321 #define R300_FPT_CMDSIZE        65
 322
 323 #define R300_FPI_CMD_0          0
 324 #define R300_FPI_INSTR_0        1
 325 #define R300_FPI_CMDSIZE        65
 326
 327 #define R300_FPP_CMD_0          0
 328 #define R300_FPP_PARAM_0        1
 329 #define R300_FPP_CMDSIZE        (32*4+1)
 330
 331 #define R300_AT_CMD_0           0
 332 #define R300_AT_ALPHA_TEST      1
 333 #define R300_AT_UNKNOWN         2
 334 #define R300_AT_CMDSIZE         3
 335
 336 #define R300_BLD_CMD_0          0
 337 #define R300_BLD_CBLEND         1
 338 #define R300_BLD_ABLEND         2
 339 #define R300_BLD_CMDSIZE        3
 340
 341 #define R300_CMK_CMD_0          0
 342 #define R300_CMK_COLORMASK      1
 343 #define R300_CMK_CMDSIZE        2
 344
 345 #define R300_CB_CMD_0           0
 346 #define R300_CB_OFFSET          1
 347 #define R300_CB_CMD_1           2
 348 #define R300_CB_PITCH           3
 349 #define R300_CB_CMDSIZE         4
 350
 351 #define R300_ZS_CMD_0           0
 352 #define R300_ZS_CNTL_0          1
 353 #define R300_ZS_CNTL_1          2
 354 #define R300_ZS_CNTL_2          3
 355 #define R300_ZS_CMDSIZE         4
 356
 357 #define R300_ZB_CMD_0           0
 358 #define R300_ZB_OFFSET          1
 359 #define R300_ZB_PITCH           2
 360 #define R300_ZB_CMDSIZE         3
 361
 362 #define R300_VPI_CMD_0          0
 363 #define R300_VPI_INSTR_0        1
 364 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 365
 366 #define R300_VPP_CMD_0          0
 367 #define R300_VPP_PARAM_0        1
 368 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 369
 370 #define R300_VPS_CMD_0          0
 371 #define R300_VPS_ZERO_0         1
 372 #define R300_VPS_ZERO_1         2
 373 #define R300_VPS_POINTSIZE      3
 374 #define R300_VPS_ZERO_3         4
 375 #define R300_VPS_CMDSIZE        5
 376
 377         /* the layout is common for all fields inside tex */
 378 #define R300_TEX_CMD_0          0
 379 #define R300_TEX_VALUE_0        1
 380 /* We don't really use this, instead specify mtu+1 dynamically
 381 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 382 */
 383
 384 /**
 385  * Cache for hardware register state.
 386  */
 387 struct r300_hw_state {
 388         struct r300_state_atom atomlist;
 389
 390         GLboolean       is_dirty;
 391         GLboolean       all_dirty;
 392         int             max_state_size; /* in dwords */
 393
 394         struct r300_state_atom vpt;     /* viewport (1D98) */
 395         struct r300_state_atom unk2080; /* (2080) */
 396         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 397         struct r300_state_atom vte;     /* (20B0) */
 398         struct r300_state_atom unk2134; /* (2134) */
 399         struct r300_state_atom unk2140; /* (2140) */
 400         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 401         struct r300_state_atom vic;     /* vap input control (2180) */
 402         struct r300_state_atom unk21DC; /* (21DC) */
 403         struct r300_state_atom unk221C; /* (221C) */
 404         struct r300_state_atom unk2220; /* (2220) */
 405         struct r300_state_atom unk2288; /* (2288) */
 406         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 407         struct r300_state_atom gb_enable; /* (4008) */
 408         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 409         struct r300_state_atom unk4200; /* (4200) */
 410         struct r300_state_atom unk4214; /* (4214) */
 411         struct r300_state_atom ps;      /* pointsize (421C) */
 412         struct r300_state_atom unk4230; /* (4230) */
 413         struct r300_state_atom lcntl;   /* line control */
 414 #ifdef EXP_C
 415         struct r300_state_atom lsf;     /* line stipple factor */
 416 #endif
 417         struct r300_state_atom dummy[4];
 418         struct r300_state_atom unk4260; /* (4260) */
 419         struct r300_state_atom unk4274; /* (4274) */
 420         struct r300_state_atom unk4288; /* (4288) */
 421         struct r300_state_atom unk42A0; /* (42A0) */
 422         struct r300_state_atom zbs;     /* zbias (42A4) */
 423         struct r300_state_atom unk42B4; /* (42B4) */
 424         struct r300_state_atom cul;     /* cull cntl (42B8) */
 425         struct r300_state_atom unk42C0; /* (42C0) */
 426         struct r300_state_atom rc;      /* rs control (4300) */
 427         struct r300_state_atom ri;      /* rs interpolators (4310) */
 428         struct r300_state_atom rr;      /* rs route (4330) */
 429         struct r300_state_atom unk43A4; /* (43A4) */
 430         struct r300_state_atom unk43E8; /* (43E8) */
 431         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 432         struct r300_state_atom fpt;     /* texi - (4620) */
 433         struct r300_state_atom unk46A4; /* (46A4) */
 434         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 435         struct r300_state_atom unk4BC0; /* (4BC0) */
 436         struct r300_state_atom unk4BC8; /* (4BC8) */
 437         struct r300_state_atom at;      /* alpha test (4BD4) */
 438         struct r300_state_atom unk4BD8; /* (4BD8) */
 439         struct r300_state_atom fpp;     /* 0x4C00 and following */
 440         struct r300_state_atom unk4E00; /* (4E00) */
 441         struct r300_state_atom bld;     /* blending (4E04) */
 442         struct r300_state_atom cmk;     /* colormask (4E0C) */
 443         struct r300_state_atom unk4E10; /* (4E10) */
 444         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 445         struct r300_state_atom unk4E50; /* (4E50) */
 446         struct r300_state_atom unk4E88; /* (4E88) */
 447         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 448         struct r300_state_atom zs;      /* zstencil control (4F00) */
 449         struct r300_state_atom unk4F10; /* (4F10) */
 450         struct r300_state_atom zb;      /* z buffer (4F20) */
 451         struct r300_state_atom unk4F28; /* (4F28) */
 452         struct r300_state_atom unk4F30; /* (4F30) */
 453         struct r300_state_atom unk4F44; /* (4F44) */
 454         struct r300_state_atom unk4F54; /* (4F54) */
 455
 456         struct r300_state_atom vpi;     /* vp instructions */
 457         struct r300_state_atom vpp;     /* vp parameters */
 458         struct r300_state_atom vps;     /* vertex point size (?) */
 459
 460                 /* 8 texture units */
 461                 /* the state is grouped by function and not by
 462                    texture unit. This makes single unit updates
 463                    really awkward - we are much better off
 464                    updating the whole thing at once */
 465         struct {
 466                 struct r300_state_atom filter;
 467                 struct r300_state_atom unknown1;
 468                 struct r300_state_atom size;
 469                 struct r300_state_atom format;
 470                 struct r300_state_atom offset;
 471                 struct r300_state_atom unknown4;
 472                 struct r300_state_atom border_color;
 473                 } tex;
 474         struct r300_state_atom txe;     /* tex enable (4104) */
 475 };
 476
 477
 478 /**
 479  * This structure holds the command buffer while it is being constructed.
 480  *
 481  * The first batch of commands in the buffer is always the state that needs
 482  * to be re-emitted when the context is lost. This batch can be skipped
 483  * otherwise.
 484  */
 485 struct r300_cmdbuf {
 486         int             size;           /* DWORDs allocated for buffer */
 487         uint32_t*       cmd_buf;
 488         int             count_used;     /* DWORDs filled so far */
 489         int             count_reemit;   /* size of re-emission batch */
 490 };
 491
 492
 493 /**
 494  * State cache
 495  */
 496
 497 struct r300_depthbuffer_state {
 498         GLfloat scale;
 499 };
 500
 501 struct r300_vap_reg_state {
 502            /* input register assigments */
 503            int i_coords;
 504            int i_normal;
 505            int i_color[2];
 506            int i_fog;
 507            int i_tex[R300_MAX_TEXTURE_UNITS];
 508            int i_index;
 509            int i_pointsize;
 510         };
 511
 512 /* Vertex shader state */
 513
 514 /* 64 appears to be the maximum */
 515 #define VSF_MAX_FRAGMENT_LENGTH 64
 516
 517
 518 struct r300_vertex_shader_fragment {
 519         int length;
 520         union {
 521                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 522                 float f[VSF_MAX_FRAGMENT_LENGTH];
 523                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH/4];
 524                 } body;
 525         };
 526
 527 #define VSF_DEST_PROGRAM        0x0
 528 #define VSF_DEST_MATRIX0        0x200
 529 #define VSF_DEST_MATRIX1        0x204
 530 #define VSF_DEST_MATRIX2        0x208
 531 #define VSF_DEST_VECTOR0        0x20c
 532 #define VSF_DEST_VECTOR1        0x20d
 533 #define VSF_DEST_UNKNOWN1       0x400
 534 #define VSF_DEST_UNKNOWN2       0x406
 535
 536 struct r300_vertex_shader_state {
 537         struct r300_vertex_shader_fragment program;
 538
 539         /* a bit of a waste - each uses only a subset of allocated space..
 540             but easier to program */
 541         struct r300_vertex_shader_fragment matrix[3];
 542         struct r300_vertex_shader_fragment vector[2];
 543
 544         struct r300_vertex_shader_fragment unknown1;
 545         struct r300_vertex_shader_fragment unknown2;
 546
 547         int program_start;
 548         int unknown_ptr1;  /* pointer within program space */
 549         int program_end;
 550
 551         int param_offset;
 552         int param_count;
 553
 554         int unknown_ptr2;  /* pointer within program space */
 555         int unknown_ptr3;  /* pointer within program space */
 556         };
 557
 558 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 559  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 560  */
 561 struct r300_vertex_program {
 562         struct vertex_program mesa_program; /* Must be first */
 563         int translated;
 564
 565         struct r300_vertex_shader_fragment program;
 566         struct r300_vertex_shader_fragment params;
 567
 568         int t2rs;
 569         unsigned long num_temporaries; /* Number of temp vars used by program */
 570         int inputs[VERT_ATTRIB_MAX];
 571 };
 572
 573 /* 64 appears to be the maximum */
 574 #define PSF_MAX_PROGRAM_LENGTH 64
 575
 576 struct r300_pixel_shader_program {
 577         struct {
 578                 int length;
 579                 GLuint inst[PSF_MAX_PROGRAM_LENGTH];
 580                 } tex;
 581
 582         /* ALU intructions (logic and integer) */
 583         struct {
 584                 int length;
 585                 struct {
 586                         GLuint inst0;
 587                         GLuint inst1;
 588                         GLuint inst2;
 589                         GLuint inst3;
 590                         } inst[PSF_MAX_PROGRAM_LENGTH];
 591                 } alu;
 592
 593         /* node information */
 594         /* nodes are used to synchronize ALU and TEX streams */
 595         /* There could be up to 4 nodes each consisting of
 596            a number of TEX instructions followed by some ALU
 597            instructions */
 598         /* the last node of a program should always be node3 */
 599         struct {
 600                 int tex_offset;
 601                 int tex_end;
 602                 int alu_offset;
 603                 int alu_end;
 604                 } node[4];
 605
 606         int active_nodes;       /* must be between 1 and 4, inclusive */
 607         int first_node_has_tex;  /* other nodes always have it */
 608
 609         int temp_register_count;  /* magic value goes into PFS_CNTL_1 */
 610
 611         /* entire program */
 612         int tex_offset;
 613         int tex_end;
 614         int alu_offset;
 615         int alu_end;
 616
 617         };
 618
 619 #define MAX_PIXEL_SHADER_PARAMS 32
 620 struct r300_pixel_shader_state {
 621         struct r300_pixel_shader_program program;
 622
 623         /* parameters */
 624         int param_length;  /* to limit the number of unnecessary writes */
 625         struct {
 626                 float x;
 627                 float y;
 628                 float z;
 629                 float w;
 630                 } param[MAX_PIXEL_SHADER_PARAMS];
 631         };
 632
 633 /* 8 is somewhat bogus... it is probably something like 24 */
 634 #define R300_MAX_AOS_ARRAYS             8
 635
 636 #define AOS_FORMAT_FLOAT        1
 637 #define AOS_FORMAT_UBYTE        2
 638 #define AOS_FORMAT_FLOAT_COLOR  3
 639
 640 #define REG_COORDS      0
 641 #define REG_COLOR0      1
 642 #define REG_TEX0        2
 643
 644 struct r300_aos_rec {
 645         GLuint offset;
 646         int element_size; /* in dwords */
 647         int stride;       /* distance between elements, in dwords */
 648
 649         int format;
 650
 651         int ncomponents; /* number of components - between 1 and 4, inclusive */
 652
 653         int reg; /* which register they are assigned to. */
 654
 655         };
 656
 657 struct r300_state {
 658         struct r300_depthbuffer_state depth;
 659         struct r300_texture_state texture;
 660         struct r300_vap_reg_state vap_reg;
 661         struct r300_vertex_shader_state vertex_shader;
 662         struct r300_pixel_shader_state pixel_shader;
 663
 664         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 665         int aos_count;
 666
 667         GLuint *Elts;
 668         struct r300_dma_region elt_ao;
 669
 670         GLuint render_inputs; /* actual render inputs that R300 was configured for.
 671                                  They are the same as tnl->render_inputs for fixed pipeline */
 672
 673         int hw_stencil;
 674 };
 675
 676
 677 /**
 678  * R300 context structure.
 679  */
 680 struct r300_context {
 681         struct radeon_context radeon; /* parent class, must be first */
 682
 683         struct r300_hw_state hw;
 684         struct r300_cmdbuf cmdbuf;
 685         struct r300_state state;
 686
 687         /* Vertex buffers
 688          */
 689         struct r300_dma dma;
 690         GLboolean save_on_next_unlock;
 691
 692         /* Texture object bookkeeping
 693          */
 694         unsigned nr_heaps;
 695         driTexHeap *texture_heaps[R200_NR_TEX_HEAPS];
 696         driTextureObject swapped;
 697         int texture_depth;
 698         float initialMaxAnisotropy;
 699
 700         /* Clientdata textures;
 701          */
 702         GLuint prefer_gart_client_texturing;
 703
 704         /* TCL stuff
 705          */
 706         GLmatrix TexGenMatrix[R300_MAX_TEXTURE_UNITS];
 707         GLboolean recheck_texgen[R300_MAX_TEXTURE_UNITS];
 708         GLboolean TexGenNeedNormals[R300_MAX_TEXTURE_UNITS];
 709         GLuint TexMatEnabled;
 710         GLuint TexMatCompSel;
 711         GLuint TexGenEnabled;
 712         GLuint TexGenInputs;
 713         GLuint TexGenCompSel;
 714         GLmatrix tmpmat;
 715
 716         struct r300_vertex_program *current_vp;
 717 };
 718
 719 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 720
 721 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 722 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 723                                    __DRIcontextPrivate * driContextPriv,
 724                                    void *sharedContextPrivate);
 725
 726 extern void r300InitVertexProgFuncs(struct dd_function_table *functions);
 727 extern void r300VertexProgUpdateParams(GLcontext *ctx, struct r300_vertex_program *vp);
 728
 729 #endif                          /* __R300_CONTEXT_H__ */