src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 #define USER_BUFFERS
  51
  52 /* We don't handle 16 bits elts swapping yet */
  53 #ifdef MESA_BIG_ENDIAN
  54 #define FORCE_32BITS_ELTS
  55 #endif
  56
  57 //#define OPTIMIZE_ELTS
  58
  59 struct r300_context;
  60 typedef struct r300_context r300ContextRec;
  61 typedef struct r300_context *r300ContextPtr;
  62
  63 #include "radeon_lock.h"
  64 #include "mm.h"
  65
  66 /* Checkpoint.. for convenience */
  67 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  68 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  69    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  70    with other compilers ... GLUE!
  71 */
  72 #if 1
  73 #define WARN_ONCE(a, ...)       { \
  74         static int warn##__LINE__=1; \
  75         if(warn##__LINE__){ \
  76                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  77                 fprintf(stderr, "File %s function %s line %d\n", \
  78                         __FILE__, __FUNCTION__, __LINE__); \
  79                 fprintf(stderr,  a, ## __VA_ARGS__);\
  80                 fprintf(stderr, "***************************************************************************\n"); \
  81                 warn##__LINE__=0;\
  82                 } \
  83         }
  84 #else
  85 #define WARN_ONCE(a, ...) {}
  86 #endif
  87
  88 #include "r300_vertprog.h"
  89 #include "r300_fragprog.h"
  90
  91 static __inline__ uint32_t r300PackFloat32(float fl)
  92 {
  93         union {
  94                 float fl;
  95                 uint32_t u;
  96         } u;
  97
  98         u.fl = fl;
  99         return u.u;
 100 }
 101
 102 /************ DMA BUFFERS **************/
 103
 104 /* Need refcounting on dma buffers:
 105  */
 106 struct r300_dma_buffer {
 107         int refcount;           /* the number of retained regions in buf */
 108         drmBufPtr buf;
 109         int id;
 110 };
 111 #undef GET_START
 112 #ifdef USER_BUFFERS
 113 #define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start))
 114 #else
 115 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 116                         (rvb)->address - rmesa->dma.buf0_address +      \
 117                         (rvb)->start)
 118 #endif
 119 /* A retained region, eg vertices for indexed vertices.
 120  */
 121 struct r300_dma_region {
 122         struct r300_dma_buffer *buf;
 123         char *address;          /* == buf->address */
 124         int start, end, ptr;    /* offsets from start of buf */
 125
 126         int aos_offset;         /* address in GART memory */
 127         int aos_stride;         /* distance between elements, in dwords */
 128         int aos_size;           /* number of components (1-4) */
 129         int aos_reg;            /* VAP register assignment */
 130 };
 131
 132 struct r300_dma {
 133         /* Active dma region.  Allocations for vertices and retained
 134          * regions come from here.  Also used for emitting random vertices,
 135          * these may be flushed by calling flush_current();
 136          */
 137         struct r300_dma_region current;
 138
 139         void (*flush) (r300ContextPtr);
 140
 141         char *buf0_address;     /* start of buf[0], for index calcs */
 142
 143         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 144          * for which a DISCARD command is currently queued in the command buffer.
 145          */
 146         GLuint nr_released_bufs;
 147 };
 148
 149        /* Texture related */
 150
 151 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 152
 153 /* Texture object in locally shared texture space.
 154  */
 155 struct r300_tex_obj {
 156         driTextureObject base;
 157
 158         GLuint bufAddr;         /* Offset to start of locally
 159                                    shared texture block */
 160
 161         GLuint dirty_state;     /* Flags (1 per texunit) for
 162                                    whether or not this texobj
 163                                    has dirty hardware state
 164                                    (pp_*) that needs to be
 165                                    brought into the
 166                                    texunit. */
 167
 168         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 169         /* Six, for the cube faces */
 170
 171         GLuint pitch;           /* this isn't sent to hardware just used in calculations */
 172         /* hardware register values */
 173         /* Note that R200 has 8 registers per texture and R300 only 7 */
 174         GLuint filter;
 175         GLuint filter_1;
 176         GLuint pitch_reg;
 177         GLuint size;            /* npot only */
 178         GLuint format;
 179         GLuint offset;          /* Image location in the card's address space.
 180                                    All cube faces follow. */
 181         GLuint unknown4;
 182         GLuint unknown5;
 183         /* end hardware registers */
 184
 185         /* registers computed by r200 code - keep them here to
 186            compare against what is actually written.
 187
 188            to be removed later.. */
 189         GLuint pp_border_color;
 190         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 191         GLuint format_x;
 192
 193         GLboolean border_fallback;
 194
 195         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 196 };
 197
 198 struct r300_texture_env_state {
 199         r300TexObjPtr texobj;
 200         GLenum format;
 201         GLenum envMode;
 202 };
 203
 204 /* The blit width for texture uploads
 205  */
 206 #define R300_BLIT_WIDTH_BYTES 1024
 207 #define R300_MAX_TEXTURE_UNITS 8
 208
 209 struct r300_texture_state {
 210         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 211         int tc_count;           /* number of incoming texture coordinates from VAP */
 212 };
 213
 214 /**
 215  * A block of hardware state.
 216  *
 217  * When check returns non-zero, the returned number of dwords must be
 218  * copied verbatim into the command buffer in order to update a state atom
 219  * when it is dirty.
 220  */
 221 struct r300_state_atom {
 222         struct r300_state_atom *next, *prev;
 223         const char *name;       /* for debug */
 224         int cmd_size;           /* maximum size in dwords */
 225         GLuint idx;             /* index in an array (e.g. textures) */
 226         uint32_t *cmd;
 227         GLboolean dirty;
 228
 229         int (*check) (r300ContextPtr, struct r300_state_atom * atom);
 230 };
 231
 232 #define R300_VPT_CMD_0          0
 233 #define R300_VPT_XSCALE         1
 234 #define R300_VPT_XOFFSET        2
 235 #define R300_VPT_YSCALE         3
 236 #define R300_VPT_YOFFSET        4
 237 #define R300_VPT_ZSCALE         5
 238 #define R300_VPT_ZOFFSET        6
 239 #define R300_VPT_CMDSIZE        7
 240
 241 #define R300_VIR_CMD_0          0       /* vir is variable size (at least 1) */
 242 #define R300_VIR_CNTL_0         1
 243 #define R300_VIR_CNTL_1         2
 244 #define R300_VIR_CNTL_2         3
 245 #define R300_VIR_CNTL_3         4
 246 #define R300_VIR_CNTL_4         5
 247 #define R300_VIR_CNTL_5         6
 248 #define R300_VIR_CNTL_6         7
 249 #define R300_VIR_CNTL_7         8
 250 #define R300_VIR_CMDSIZE        9
 251
 252 #define R300_VIC_CMD_0          0
 253 #define R300_VIC_CNTL_0         1
 254 #define R300_VIC_CNTL_1         2
 255 #define R300_VIC_CMDSIZE        3
 256
 257 #define R300_VOF_CMD_0          0
 258 #define R300_VOF_CNTL_0         1
 259 #define R300_VOF_CNTL_1         2
 260 #define R300_VOF_CMDSIZE        3
 261
 262 #define R300_PVS_CMD_0          0
 263 #define R300_PVS_CNTL_1         1
 264 #define R300_PVS_CNTL_2         2
 265 #define R300_PVS_CNTL_3         3
 266 #define R300_PVS_CMDSIZE        4
 267
 268 #define R300_GB_MISC_CMD_0              0
 269 #define R300_GB_MISC_MSPOS_0            1
 270 #define R300_GB_MISC_MSPOS_1            2
 271 #define R300_GB_MISC_TILE_CONFIG        3
 272 #define R300_GB_MISC_SELECT             4
 273 #define R300_GB_MISC_AA_CONFIG          5
 274 #define R300_GB_MISC_CMDSIZE            6
 275
 276 #define R300_TXE_CMD_0          0
 277 #define R300_TXE_ENABLE         1
 278 #define R300_TXE_CMDSIZE        2
 279
 280 #define R300_PS_CMD_0           0
 281 #define R300_PS_POINTSIZE       1
 282 #define R300_PS_CMDSIZE         2
 283
 284 #define R300_ZBS_CMD_0          0
 285 #define R300_ZBS_T_FACTOR       1
 286 #define R300_ZBS_T_CONSTANT     2
 287 #define R300_ZBS_W_FACTOR       3
 288 #define R300_ZBS_W_CONSTANT     4
 289 #define R300_ZBS_CMDSIZE        5
 290
 291 #define R300_CUL_CMD_0          0
 292 #define R300_CUL_CULL           1
 293 #define R300_CUL_CMDSIZE        2
 294
 295 #define R300_RC_CMD_0           0
 296 #define R300_RC_CNTL_0          1
 297 #define R300_RC_CNTL_1          2
 298 #define R300_RC_CMDSIZE         3
 299
 300 #define R300_RI_CMD_0           0
 301 #define R300_RI_INTERP_0        1
 302 #define R300_RI_INTERP_1        2
 303 #define R300_RI_INTERP_2        3
 304 #define R300_RI_INTERP_3        4
 305 #define R300_RI_INTERP_4        5
 306 #define R300_RI_INTERP_5        6
 307 #define R300_RI_INTERP_6        7
 308 #define R300_RI_INTERP_7        8
 309 #define R300_RI_CMDSIZE         9
 310
 311 #define R300_RR_CMD_0           0       /* rr is variable size (at least 1) */
 312 #define R300_RR_ROUTE_0         1
 313 #define R300_RR_ROUTE_1         2
 314 #define R300_RR_ROUTE_2         3
 315 #define R300_RR_ROUTE_3         4
 316 #define R300_RR_ROUTE_4         5
 317 #define R300_RR_ROUTE_5         6
 318 #define R300_RR_ROUTE_6         7
 319 #define R300_RR_ROUTE_7         8
 320 #define R300_RR_CMDSIZE         9
 321
 322 #define R300_FP_CMD_0           0
 323 #define R300_FP_CNTL0           1
 324 #define R300_FP_CNTL1           2
 325 #define R300_FP_CNTL2           3
 326 #define R300_FP_CMD_1           4
 327 #define R300_FP_NODE0           5
 328 #define R300_FP_NODE1           6
 329 #define R300_FP_NODE2           7
 330 #define R300_FP_NODE3           8
 331 #define R300_FP_CMDSIZE         9
 332
 333 #define R300_FPT_CMD_0          0
 334 #define R300_FPT_INSTR_0        1
 335 #define R300_FPT_CMDSIZE        65
 336
 337 #define R300_FPI_CMD_0          0
 338 #define R300_FPI_INSTR_0        1
 339 #define R300_FPI_CMDSIZE        65
 340
 341 #define R300_FPP_CMD_0          0
 342 #define R300_FPP_PARAM_0        1
 343 #define R300_FPP_CMDSIZE        (32*4+1)
 344
 345 #define R300_FOGS_CMD_0         0
 346 #define R300_FOGS_STATE         1
 347 #define R300_FOGS_CMDSIZE       2
 348
 349 #define R300_FOGC_CMD_0         0
 350 #define R300_FOGC_R             1
 351 #define R300_FOGC_G             2
 352 #define R300_FOGC_B             3
 353 #define R300_FOGC_CMDSIZE       4
 354
 355 #define R300_FOGP_CMD_0         0
 356 #define R300_FOGP_SCALE         1
 357 #define R300_FOGP_START         2
 358 #define R300_FOGP_CMDSIZE       3
 359
 360 #define R300_AT_CMD_0           0
 361 #define R300_AT_ALPHA_TEST      1
 362 #define R300_AT_UNKNOWN         2
 363 #define R300_AT_CMDSIZE         3
 364
 365 #define R300_BLD_CMD_0          0
 366 #define R300_BLD_CBLEND         1
 367 #define R300_BLD_ABLEND         2
 368 #define R300_BLD_CMDSIZE        3
 369
 370 #define R300_CMK_CMD_0          0
 371 #define R300_CMK_COLORMASK      1
 372 #define R300_CMK_CMDSIZE        2
 373
 374 #define R300_CB_CMD_0           0
 375 #define R300_CB_OFFSET          1
 376 #define R300_CB_CMD_1           2
 377 #define R300_CB_PITCH           3
 378 #define R300_CB_CMDSIZE         4
 379
 380 #define R300_ZS_CMD_0           0
 381 #define R300_ZS_CNTL_0          1
 382 #define R300_ZS_CNTL_1          2
 383 #define R300_ZS_CNTL_2          3
 384 #define R300_ZS_CMDSIZE         4
 385
 386 #define R300_ZB_CMD_0           0
 387 #define R300_ZB_OFFSET          1
 388 #define R300_ZB_PITCH           2
 389 #define R300_ZB_CMDSIZE         3
 390
 391 #define R300_VPI_CMD_0          0
 392 #define R300_VPI_INSTR_0        1
 393 #define R300_VPI_CMDSIZE        1025    /* 256 16 byte instructions */
 394
 395 #define R300_VPP_CMD_0          0
 396 #define R300_VPP_PARAM_0        1
 397 #define R300_VPP_CMDSIZE        1025    /* 256 4-component parameters */
 398
 399 #define R300_VPS_CMD_0          0
 400 #define R300_VPS_ZERO_0         1
 401 #define R300_VPS_ZERO_1         2
 402 #define R300_VPS_POINTSIZE      3
 403 #define R300_VPS_ZERO_3         4
 404 #define R300_VPS_CMDSIZE        5
 405
 406         /* the layout is common for all fields inside tex */
 407 #define R300_TEX_CMD_0          0
 408 #define R300_TEX_VALUE_0        1
 409 /* We don't really use this, instead specify mtu+1 dynamically
 410 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 411 */
 412
 413 /**
 414  * Cache for hardware register state.
 415  */
 416 struct r300_hw_state {
 417         struct r300_state_atom atomlist;
 418
 419         GLboolean is_dirty;
 420         GLboolean all_dirty;
 421         int max_state_size;     /* in dwords */
 422
 423         struct r300_state_atom vpt;     /* viewport (1D98) */
 424         struct r300_state_atom vap_cntl;
 425         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 426         struct r300_state_atom vte;     /* (20B0) */
 427         struct r300_state_atom unk2134; /* (2134) */
 428         struct r300_state_atom vap_cntl_status;
 429         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 430         struct r300_state_atom vic;     /* vap input control (2180) */
 431         struct r300_state_atom unk21DC; /* (21DC) */
 432         struct r300_state_atom unk221C; /* (221C) */
 433         struct r300_state_atom unk2220; /* (2220) */
 434         struct r300_state_atom unk2288; /* (2288) */
 435         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 436         struct r300_state_atom gb_enable;       /* (4008) */
 437         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 438         struct r300_state_atom unk4200; /* (4200) */
 439         struct r300_state_atom unk4214; /* (4214) */
 440         struct r300_state_atom ps;      /* pointsize (421C) */
 441         struct r300_state_atom unk4230; /* (4230) */
 442         struct r300_state_atom lcntl;   /* line control */
 443         struct r300_state_atom unk4260; /* (4260) */
 444         struct r300_state_atom shade;
 445         struct r300_state_atom polygon_mode;
 446         struct r300_state_atom fogp;    /* fog parameters (4294) */
 447         struct r300_state_atom unk429C; /* (429C) */
 448         struct r300_state_atom zbias_cntl;
 449         struct r300_state_atom zbs;     /* zbias (42A4) */
 450         struct r300_state_atom occlusion_cntl;
 451         struct r300_state_atom cul;     /* cull cntl (42B8) */
 452         struct r300_state_atom unk42C0; /* (42C0) */
 453         struct r300_state_atom rc;      /* rs control (4300) */
 454         struct r300_state_atom ri;      /* rs interpolators (4310) */
 455         struct r300_state_atom rr;      /* rs route (4330) */
 456         struct r300_state_atom unk43A4; /* (43A4) */
 457         struct r300_state_atom unk43E8; /* (43E8) */
 458         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 459         struct r300_state_atom fpt;     /* texi - (4620) */
 460         struct r300_state_atom unk46A4; /* (46A4) */
 461         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 462         struct r300_state_atom fogs;    /* fog state (4BC0) */
 463         struct r300_state_atom fogc;    /* fog color (4BC8) */
 464         struct r300_state_atom at;      /* alpha test (4BD4) */
 465         struct r300_state_atom unk4BD8; /* (4BD8) */
 466         struct r300_state_atom fpp;     /* 0x4C00 and following */
 467         struct r300_state_atom unk4E00; /* (4E00) */
 468         struct r300_state_atom bld;     /* blending (4E04) */
 469         struct r300_state_atom cmk;     /* colormask (4E0C) */
 470         struct r300_state_atom blend_color;     /* constant blend color */
 471         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 472         struct r300_state_atom unk4E50; /* (4E50) */
 473         struct r300_state_atom unk4E88; /* (4E88) */
 474         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 475         struct r300_state_atom zs;      /* zstencil control (4F00) */
 476         struct r300_state_atom zstencil_format;
 477         struct r300_state_atom zb;      /* z buffer (4F20) */
 478         struct r300_state_atom unk4F28; /* (4F28) */
 479         struct r300_state_atom unk4F30; /* (4F30) */
 480         struct r300_state_atom unk4F44; /* (4F44) */
 481         struct r300_state_atom unk4F54; /* (4F54) */
 482
 483         struct r300_state_atom vpi;     /* vp instructions */
 484         struct r300_state_atom vpp;     /* vp parameters */
 485         struct r300_state_atom vps;     /* vertex point size (?) */
 486         /* 8 texture units */
 487         /* the state is grouped by function and not by
 488            texture unit. This makes single unit updates
 489            really awkward - we are much better off
 490            updating the whole thing at once */
 491         struct {
 492                 struct r300_state_atom filter;
 493                 struct r300_state_atom filter_1;
 494                 struct r300_state_atom size;
 495                 struct r300_state_atom format;
 496                 struct r300_state_atom pitch;
 497                 struct r300_state_atom offset;
 498                 struct r300_state_atom chroma_key;
 499                 struct r300_state_atom border_color;
 500         } tex;
 501         struct r300_state_atom txe;     /* tex enable (4104) */
 502 };
 503
 504 /**
 505  * This structure holds the command buffer while it is being constructed.
 506  *
 507  * The first batch of commands in the buffer is always the state that needs
 508  * to be re-emitted when the context is lost. This batch can be skipped
 509  * otherwise.
 510  */
 511 struct r300_cmdbuf {
 512         int size;               /* DWORDs allocated for buffer */
 513         uint32_t *cmd_buf;
 514         int count_used;         /* DWORDs filled so far */
 515         int count_reemit;       /* size of re-emission batch */
 516 };
 517
 518 /**
 519  * State cache
 520  */
 521
 522 struct r300_depthbuffer_state {
 523         GLfloat scale;
 524 };
 525
 526 struct r300_stencilbuffer_state {
 527         GLuint clear;
 528         GLboolean hw_stencil;
 529
 530 };
 531
 532 /* Vertex shader state */
 533
 534 /* Perhaps more if we store programs in vmem? */
 535 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 536 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 537
 538 /* Can be tested with colormat currently. */
 539 #define VSF_MAX_FRAGMENT_TEMPS (14)
 540
 541 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 542 #define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
 543
 544 struct r300_vertex_shader_fragment {
 545         int length;
 546         union {
 547                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 548                 float f[VSF_MAX_FRAGMENT_LENGTH];
 549                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH / 4];
 550         } body;
 551 };
 552
 553 #define VSF_DEST_PROGRAM        0x0
 554 #define VSF_DEST_MATRIX0        0x200
 555 #define VSF_DEST_MATRIX1        0x204
 556 #define VSF_DEST_MATRIX2        0x208
 557 #define VSF_DEST_VECTOR0        0x20c
 558 #define VSF_DEST_VECTOR1        0x20d
 559 #define VSF_DEST_UNKNOWN1       0x400
 560 #define VSF_DEST_UNKNOWN2       0x406
 561
 562 struct r300_vertex_shader_state {
 563         struct r300_vertex_shader_fragment program;
 564
 565         struct r300_vertex_shader_fragment unknown1;
 566         struct r300_vertex_shader_fragment unknown2;
 567
 568         int program_start;
 569         int unknown_ptr1;       /* pointer within program space */
 570         int program_end;
 571
 572         int param_offset;
 573         int param_count;
 574
 575         int unknown_ptr2;       /* pointer within program space */
 576         int unknown_ptr3;       /* pointer within program space */
 577 };
 578
 579 extern int hw_tcl_on;
 580
 581 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 582 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 583
 584 /* Should but doesnt work */
 585 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 586
 587 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 588  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 589  */
 590
 591 struct r300_vertex_program_key {
 592         GLuint InputsRead;
 593         GLuint OutputsWritten;
 594 };
 595
 596 struct r300_vertex_program {
 597         struct r300_vertex_program *next;
 598         struct r300_vertex_program_key key;
 599         int translated;
 600
 601         struct r300_vertex_shader_fragment program;
 602
 603         int pos_end;
 604         int num_temporaries;    /* Number of temp vars used by program */
 605         int wpos_idx;
 606         int inputs[VERT_ATTRIB_MAX];
 607         int outputs[VERT_RESULT_MAX];
 608         int native;
 609         int ref_count;
 610         int use_ref_count;
 611 };
 612
 613 struct r300_vertex_program_cont {
 614         struct gl_vertex_program mesa_program;  /* Must be first */
 615         struct r300_vertex_shader_fragment params;
 616         struct r300_vertex_program *progs;
 617 };
 618
 619 #define PFS_MAX_ALU_INST        64
 620 #define PFS_MAX_TEX_INST        64
 621 #define PFS_MAX_TEX_INDIRECT 4
 622 #define PFS_NUM_TEMP_REGS       32
 623 #define PFS_NUM_CONST_REGS      16
 624
 625 /* Mapping Mesa registers to R300 temporaries */
 626 struct reg_acc {
 627         int reg;                /* Assigned hw temp */
 628         unsigned int refcount;  /* Number of uses by mesa program */
 629 };
 630
 631 /**
 632  * Describe the current lifetime information for an R300 temporary
 633  */
 634 struct reg_lifetime {
 635         /* Index of the first slot where this register is free in the sense
 636            that it can be used as a new destination register.
 637            This is -1 if the register has been assigned to a Mesa register
 638            and the last access to the register has not yet been emitted */
 639         int free;
 640
 641         /* Index of the first slot where this register is currently reserved.
 642            This is used to stop e.g. a scalar operation from being moved
 643            before the allocation time of a register that was first allocated
 644            for a vector operation. */
 645         int reserved;
 646
 647         /* Index of the first slot in which the register can be used as a
 648            source without losing the value that is written by the last
 649            emitted instruction that writes to the register */
 650         int vector_valid;
 651         int scalar_valid;
 652
 653         /* Index to the slot where the register was last read.
 654            This is also the first slot in which the register may be written again */
 655         int vector_lastread;
 656         int scalar_lastread;
 657 };
 658
 659 /**
 660  * Store usage information about an ALU instruction slot during the
 661  * compilation of a fragment program.
 662  */
 663 #define SLOT_SRC_VECTOR  (1<<0)
 664 #define SLOT_SRC_SCALAR  (1<<3)
 665 #define SLOT_SRC_BOTH    (SLOT_SRC_VECTOR | SLOT_SRC_SCALAR)
 666 #define SLOT_OP_VECTOR   (1<<16)
 667 #define SLOT_OP_SCALAR   (1<<17)
 668 #define SLOT_OP_BOTH     (SLOT_OP_VECTOR | SLOT_OP_SCALAR)
 669
 670 struct r300_pfs_compile_slot {
 671         /* Bitmask indicating which parts of the slot are used, using SLOT_ constants
 672            defined above */
 673         unsigned int used;
 674
 675         /* Selected sources */
 676         int vsrc[3];
 677         int ssrc[3];
 678 };
 679
 680 /**
 681  * Store information during compilation of fragment programs.
 682  */
 683 struct r300_pfs_compile_state {
 684         int nrslots;            /* number of ALU slots used so far */
 685
 686         /* Track which (parts of) slots are already filled with instructions */
 687         struct r300_pfs_compile_slot slot[PFS_MAX_ALU_INST];
 688
 689         /* Track the validity of R300 temporaries */
 690         struct reg_lifetime hwtemps[PFS_NUM_TEMP_REGS];
 691
 692         /* Used to map Mesa's inputs/temps onto hardware temps */
 693         int temp_in_use;
 694         struct reg_acc temps[PFS_NUM_TEMP_REGS];
 695         struct reg_acc inputs[32];      /* don't actually need 32... */
 696
 697         /* Track usage of hardware temps, for register allocation,
 698          * indirection detection, etc. */
 699         GLuint used_in_node;
 700         GLuint dest_in_node;
 701 };
 702
 703 /**
 704  * Store everything about a fragment program that is needed
 705  * to render with that program.
 706  */
 707 struct r300_fragment_program {
 708         struct gl_fragment_program mesa_program;
 709
 710         GLcontext *ctx;
 711         GLboolean translated;
 712         GLboolean error;
 713         struct r300_pfs_compile_state *cs;
 714
 715         struct {
 716                 int length;
 717                 GLuint inst[PFS_MAX_TEX_INST];
 718         } tex;
 719
 720         struct {
 721                 struct {
 722                         GLuint inst0;
 723                         GLuint inst1;
 724                         GLuint inst2;
 725                         GLuint inst3;
 726                 } inst[PFS_MAX_ALU_INST];
 727         } alu;
 728
 729         struct {
 730                 int tex_offset;
 731                 int tex_end;
 732                 int alu_offset;
 733                 int alu_end;
 734                 int flags;
 735         } node[4];
 736         int cur_node;
 737         int first_node_has_tex;
 738
 739         int alu_offset;
 740         int alu_end;
 741         int tex_offset;
 742         int tex_end;
 743
 744         /* Hardware constants.
 745          * Contains a pointer to the value. The destination of the pointer
 746          * is supposed to be updated when GL state changes.
 747          * Typically, this is either a pointer into
 748          * gl_program_parameter_list::ParameterValues, or a pointer to a
 749          * global constant (e.g. for sin/cos-approximation)
 750          */
 751         const GLfloat *constant[PFS_NUM_CONST_REGS];
 752         int const_nr;
 753
 754         int max_temp_idx;
 755
 756         GLuint optimization;
 757 };
 758
 759 #define R300_MAX_AOS_ARRAYS             16
 760
 761 #define AOS_FORMAT_USHORT       0
 762 #define AOS_FORMAT_FLOAT        1
 763 #define AOS_FORMAT_UBYTE        2
 764 #define AOS_FORMAT_FLOAT_COLOR  3
 765
 766 #define REG_COORDS      0
 767 #define REG_COLOR0      1
 768 #define REG_TEX0        2
 769
 770 struct dt {
 771         GLint size;
 772         GLenum type;
 773         GLsizei stride;
 774         void *data;
 775 };
 776
 777 struct radeon_vertex_buffer {
 778         int Count;
 779         void *Elts;
 780         int elt_size;
 781         int elt_min, elt_max;   /* debug */
 782
 783         struct dt AttribPtr[VERT_ATTRIB_MAX];
 784
 785         const struct _mesa_prim *Primitive;
 786         GLuint PrimitiveCount;
 787         GLint LockFirst;
 788         GLsizei LockCount;
 789         int lock_uptodate;
 790 };
 791
 792 struct r300_aos_rec {
 793         GLuint offset;
 794         int element_size;       /* in dwords */
 795         int stride;             /* distance between elements, in dwords */
 796
 797         int format;
 798
 799         int ncomponents;        /* number of components - between 1 and 4, inclusive */
 800
 801         int reg;                /* which register they are assigned to. */
 802
 803 };
 804
 805 struct r300_state {
 806         struct r300_depthbuffer_state depth;
 807         struct r300_texture_state texture;
 808         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 809         struct r300_vertex_shader_state vertex_shader;
 810         struct r300_pfs_compile_state pfs_compile;
 811         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 812         int aos_count;
 813         struct radeon_vertex_buffer VB;
 814
 815         GLuint *Elts;
 816         struct r300_dma_region elt_dma;
 817
 818          DECLARE_RENDERINPUTS(render_inputs_bitset);    /* actual render inputs that R300 was configured for.
 819                                                            They are the same as tnl->render_inputs for fixed pipeline */
 820
 821         struct {
 822                 int transform_offset;   /* Transform matrix offset, -1 if none */
 823         } vap_param;            /* vertex processor parameter allocation - tells where to write parameters */
 824
 825         struct r300_stencilbuffer_state stencil;
 826
 827 };
 828
 829 #define R300_FALLBACK_NONE 0
 830 #define R300_FALLBACK_TCL 1
 831 #define R300_FALLBACK_RAST 2
 832
 833 /**
 834  * R300 context structure.
 835  */
 836 struct r300_context {
 837         struct radeon_context radeon;   /* parent class, must be first */
 838
 839         struct r300_hw_state hw;
 840         struct r300_cmdbuf cmdbuf;
 841         struct r300_state state;
 842         struct gl_vertex_program *curr_vp;
 843         struct r300_vertex_program *selected_vp;
 844
 845         /* Vertex buffers
 846          */
 847         struct r300_dma dma;
 848         GLboolean save_on_next_unlock;
 849         GLuint NewGLState;
 850
 851         /* Texture object bookkeeping
 852          */
 853         unsigned nr_heaps;
 854         driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
 855         driTextureObject swapped;
 856         int texture_depth;
 857         float initialMaxAnisotropy;
 858
 859         /* Clientdata textures;
 860          */
 861         GLuint prefer_gart_client_texturing;
 862
 863 #ifdef USER_BUFFERS
 864         struct radeon_memory_manager *rmm;
 865         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 866         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 867 #endif
 868
 869         GLboolean texmicrotile;
 870         GLboolean span_dlocking;
 871         GLboolean disable_lowimpact_fallback;
 872 };
 873
 874 struct r300_buffer_object {
 875         struct gl_buffer_object mesa_obj;
 876         int id;
 877 };
 878
 879 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 880
 881 static __inline GLuint r300PackColor(GLuint cpp,
 882                                      GLubyte r, GLubyte g, GLubyte b, GLubyte a)
 883 {
 884         switch (cpp) {
 885         case 2:
 886                 return PACK_COLOR_565(r, g, b);
 887         case 4:
 888                 return PACK_COLOR_8888(r, g, b, a);
 889         default:
 890                 return 0;
 891         }
 892 }
 893 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 894 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 895                                    __DRIcontextPrivate * driContextPriv,
 896                                    void *sharedContextPrivate);
 897
 898 extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim);
 899
 900 extern void r300SelectVertexShader(r300ContextPtr r300);
 901 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 902 extern int r300VertexProgUpdateParams(GLcontext * ctx,
 903                                       struct r300_vertex_program_cont *vp,
 904                                       float *dst);
 905 extern int r300Fallback(GLcontext * ctx);
 906
 907 extern GLboolean r300RunRender(GLcontext * ctx,
 908                                struct tnl_pipeline_stage *stage);
 909
 910 #define RADEON_D_CAPTURE 0
 911 #define RADEON_D_PLAYBACK 1
 912 #define RADEON_D_PLAYBACK_RAW 2
 913 #define RADEON_D_T 3
 914
 915 #endif                          /* __R300_CONTEXT_H__ */