src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 #define USER_BUFFERS
  51 /* KW: Disable this code.  Driver should hook into vbo module
  52  * directly, see i965 driver for example.
  53  */
  54 /* #define RADEON_VTXFMT_A */
  55 #define HW_VBOS
  56
  57 /* We don't handle 16 bits elts swapping yet */
  58 #ifdef MESA_BIG_ENDIAN
  59 #define FORCE_32BITS_ELTS
  60 #endif
  61
  62 //#define OPTIMIZE_ELTS
  63
  64 struct r300_context;
  65 typedef struct r300_context r300ContextRec;
  66 typedef struct r300_context *r300ContextPtr;
  67
  68 #include "radeon_lock.h"
  69 #include "mm.h"
  70
  71 /* Checkpoint.. for convenience */
  72 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  73 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  74    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  75    with other compilers ... GLUE!
  76 */
  77 #if 1
  78 #define WARN_ONCE(a, ...)       { \
  79         static int warn##__LINE__=1; \
  80         if(warn##__LINE__){ \
  81                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  82                 fprintf(stderr, "File %s function %s line %d\n", \
  83                         __FILE__, __FUNCTION__, __LINE__); \
  84                 fprintf(stderr,  a, ## __VA_ARGS__);\
  85                 fprintf(stderr, "***************************************************************************\n"); \
  86                 warn##__LINE__=0;\
  87                 } \
  88         }
  89 #else
  90 #define WARN_ONCE(a, ...) {}
  91 #endif
  92
  93   /* We should probably change types within vertex_shader
  94       and pixel_shader structure later on */
  95 #define CARD32 GLuint
  96 #include "vertex_shader.h"
  97 #include "r300_fragprog.h"
  98 #undef CARD32
  99
 100 static __inline__ uint32_t r300PackFloat32(float fl)
 101 {
 102         union { float fl; uint32_t u; } u;
 103
 104         u.fl = fl;
 105         return u.u;
 106 }
 107
 108
 109 /************ DMA BUFFERS **************/
 110
 111 /* Need refcounting on dma buffers:
 112  */
 113 struct r300_dma_buffer {
 114         int refcount;           /* the number of retained regions in buf */
 115         drmBufPtr buf;
 116         int id;
 117 };
 118 #undef GET_START
 119 #ifdef USER_BUFFERS
 120 #define GET_START(rvb) (r300GartOffsetFromVirtual(rmesa, (rvb)->address+(rvb)->start))
 121 #else
 122 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 123                         (rvb)->address - rmesa->dma.buf0_address +      \
 124                         (rvb)->start)
 125 #endif
 126 /* A retained region, eg vertices for indexed vertices.
 127  */
 128 struct r300_dma_region {
 129         struct r300_dma_buffer *buf;
 130         char *address;          /* == buf->address */
 131         int start, end, ptr;    /* offsets from start of buf */
 132
 133     int aos_offset;     /* address in GART memory */
 134     int aos_stride;     /* distance between elements, in dwords */
 135     int aos_size;       /* number of components (1-4) */
 136     int aos_reg;        /* VAP register assignment */
 137 };
 138
 139 struct r300_dma {
 140         /* Active dma region.  Allocations for vertices and retained
 141          * regions come from here.  Also used for emitting random vertices,
 142          * these may be flushed by calling flush_current();
 143          */
 144         struct r300_dma_region current;
 145
 146         void (*flush) (r300ContextPtr);
 147
 148         char *buf0_address;     /* start of buf[0], for index calcs */
 149
 150         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 151          * for which a DISCARD command is currently queued in the command buffer.
 152          */
 153         GLuint nr_released_bufs;
 154 };
 155
 156        /* Texture related */
 157
 158 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 159
 160 /* Texture object in locally shared texture space.
 161  */
 162 struct r300_tex_obj {
 163         driTextureObject base;
 164
 165         GLuint bufAddr;         /* Offset to start of locally
 166                                    shared texture block */
 167
 168         GLuint dirty_state;     /* Flags (1 per texunit) for
 169                                    whether or not this texobj
 170                                    has dirty hardware state
 171                                    (pp_*) that needs to be
 172                                    brought into the
 173                                    texunit. */
 174
 175         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 176         /* Six, for the cube faces */
 177
 178
 179         GLuint pitch; /* this isn't sent to hardware just used in calculations */
 180         /* hardware register values */
 181         /* Note that R200 has 8 registers per texture and R300 only 7 */
 182         GLuint filter;
 183         GLuint pitch_reg;
 184         GLuint size;    /* npot only */
 185         GLuint format;
 186         GLuint offset;  /* Image location in the card's address space.
 187                                    All cube faces follow. */
 188         GLuint unknown4;
 189         GLuint unknown5;
 190         /* end hardware registers */
 191
 192         /* registers computed by r200 code - keep them here to
 193            compare against what is actually written.
 194
 195            to be removed later.. */
 196         GLuint pp_border_color;
 197         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 198         GLuint format_x;
 199
 200
 201         GLboolean border_fallback;
 202
 203         GLuint tile_bits; /* hw texture tile bits used on this texture */
 204 };
 205
 206 struct r300_texture_env_state {
 207         r300TexObjPtr texobj;
 208         GLenum format;
 209         GLenum envMode;
 210 };
 211
 212
 213 /* The blit width for texture uploads
 214  */
 215 #define R300_BLIT_WIDTH_BYTES 1024
 216 #define R300_MAX_TEXTURE_UNITS 8
 217
 218 struct r300_texture_state {
 219         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 220         int tc_count; /* number of incoming texture coordinates from VAP */
 221 };
 222
 223 /**
 224  * A block of hardware state.
 225  *
 226  * When check returns non-zero, the returned number of dwords must be
 227  * copied verbatim into the command buffer in order to update a state atom
 228  * when it is dirty.
 229  */
 230 struct r300_state_atom {
 231         struct r300_state_atom *next, *prev;
 232         const char* name;       /* for debug */
 233         int cmd_size;           /* maximum size in dwords */
 234         GLuint idx;             /* index in an array (e.g. textures) */
 235         uint32_t* cmd;
 236         GLboolean dirty;
 237
 238         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 239 };
 240
 241
 242 #define R300_VPT_CMD_0          0
 243 #define R300_VPT_XSCALE         1
 244 #define R300_VPT_XOFFSET        2
 245 #define R300_VPT_YSCALE         3
 246 #define R300_VPT_YOFFSET        4
 247 #define R300_VPT_ZSCALE         5
 248 #define R300_VPT_ZOFFSET        6
 249 #define R300_VPT_CMDSIZE        7
 250
 251 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 252 #define R300_VIR_CNTL_0         1
 253 #define R300_VIR_CNTL_1         2
 254 #define R300_VIR_CNTL_2         3
 255 #define R300_VIR_CNTL_3         4
 256 #define R300_VIR_CNTL_4         5
 257 #define R300_VIR_CNTL_5         6
 258 #define R300_VIR_CNTL_6         7
 259 #define R300_VIR_CNTL_7         8
 260 #define R300_VIR_CMDSIZE        9
 261
 262 #define R300_VIC_CMD_0          0
 263 #define R300_VIC_CNTL_0         1
 264 #define R300_VIC_CNTL_1         2
 265 #define R300_VIC_CMDSIZE        3
 266
 267 #define R300_VOF_CMD_0          0
 268 #define R300_VOF_CNTL_0         1
 269 #define R300_VOF_CNTL_1         2
 270 #define R300_VOF_CMDSIZE        3
 271
 272
 273 #define R300_PVS_CMD_0          0
 274 #define R300_PVS_CNTL_1         1
 275 #define R300_PVS_CNTL_2         2
 276 #define R300_PVS_CNTL_3         3
 277 #define R300_PVS_CMDSIZE        4
 278
 279 #define R300_GB_MISC_CMD_0              0
 280 #define R300_GB_MISC_MSPOS_0            1
 281 #define R300_GB_MISC_MSPOS_1            2
 282 #define R300_GB_MISC_TILE_CONFIG        3
 283 #define R300_GB_MISC_SELECT             4
 284 #define R300_GB_MISC_AA_CONFIG          5
 285 #define R300_GB_MISC_CMDSIZE            6
 286
 287 #define R300_TXE_CMD_0          0
 288 #define R300_TXE_ENABLE         1
 289 #define R300_TXE_CMDSIZE        2
 290
 291 #define R300_PS_CMD_0           0
 292 #define R300_PS_POINTSIZE       1
 293 #define R300_PS_CMDSIZE         2
 294
 295 #define R300_ZBS_CMD_0          0
 296 #define R300_ZBS_T_FACTOR       1
 297 #define R300_ZBS_T_CONSTANT     2
 298 #define R300_ZBS_W_FACTOR       3
 299 #define R300_ZBS_W_CONSTANT     4
 300 #define R300_ZBS_CMDSIZE        5
 301
 302 #define R300_CUL_CMD_0          0
 303 #define R300_CUL_CULL           1
 304 #define R300_CUL_CMDSIZE        2
 305
 306 #define R300_RC_CMD_0           0
 307 #define R300_RC_CNTL_0          1
 308 #define R300_RC_CNTL_1          2
 309 #define R300_RC_CMDSIZE         3
 310
 311 #define R300_RI_CMD_0           0
 312 #define R300_RI_INTERP_0        1
 313 #define R300_RI_INTERP_1        2
 314 #define R300_RI_INTERP_2        3
 315 #define R300_RI_INTERP_3        4
 316 #define R300_RI_INTERP_4        5
 317 #define R300_RI_INTERP_5        6
 318 #define R300_RI_INTERP_6        7
 319 #define R300_RI_INTERP_7        8
 320 #define R300_RI_CMDSIZE         9
 321
 322 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 323 #define R300_RR_ROUTE_0         1
 324 #define R300_RR_ROUTE_1         2
 325 #define R300_RR_ROUTE_2         3
 326 #define R300_RR_ROUTE_3         4
 327 #define R300_RR_ROUTE_4         5
 328 #define R300_RR_ROUTE_5         6
 329 #define R300_RR_ROUTE_6         7
 330 #define R300_RR_ROUTE_7         8
 331 #define R300_RR_CMDSIZE         9
 332
 333 #define R300_FP_CMD_0           0
 334 #define R300_FP_CNTL0           1
 335 #define R300_FP_CNTL1           2
 336 #define R300_FP_CNTL2           3
 337 #define R300_FP_CMD_1           4
 338 #define R300_FP_NODE0           5
 339 #define R300_FP_NODE1           6
 340 #define R300_FP_NODE2           7
 341 #define R300_FP_NODE3           8
 342 #define R300_FP_CMDSIZE         9
 343
 344 #define R300_FPT_CMD_0          0
 345 #define R300_FPT_INSTR_0        1
 346 #define R300_FPT_CMDSIZE        65
 347
 348 #define R300_FPI_CMD_0          0
 349 #define R300_FPI_INSTR_0        1
 350 #define R300_FPI_CMDSIZE        65
 351
 352 #define R300_FPP_CMD_0          0
 353 #define R300_FPP_PARAM_0        1
 354 #define R300_FPP_CMDSIZE        (32*4+1)
 355
 356 #define R300_FOGS_CMD_0         0
 357 #define R300_FOGS_STATE         1
 358 #define R300_FOGS_CMDSIZE       2
 359
 360 #define R300_FOGC_CMD_0         0
 361 #define R300_FOGC_R             1
 362 #define R300_FOGC_G             2
 363 #define R300_FOGC_B             3
 364 #define R300_FOGC_CMDSIZE       4
 365
 366 #define R300_FOGP_CMD_0         0
 367 #define R300_FOGP_SCALE         1
 368 #define R300_FOGP_START         2
 369 #define R300_FOGP_CMDSIZE       3
 370
 371 #define R300_AT_CMD_0           0
 372 #define R300_AT_ALPHA_TEST      1
 373 #define R300_AT_UNKNOWN         2
 374 #define R300_AT_CMDSIZE         3
 375
 376 #define R300_BLD_CMD_0          0
 377 #define R300_BLD_CBLEND         1
 378 #define R300_BLD_ABLEND         2
 379 #define R300_BLD_CMDSIZE        3
 380
 381 #define R300_CMK_CMD_0          0
 382 #define R300_CMK_COLORMASK      1
 383 #define R300_CMK_CMDSIZE        2
 384
 385 #define R300_CB_CMD_0           0
 386 #define R300_CB_OFFSET          1
 387 #define R300_CB_CMD_1           2
 388 #define R300_CB_PITCH           3
 389 #define R300_CB_CMDSIZE         4
 390
 391 #define R300_ZS_CMD_0           0
 392 #define R300_ZS_CNTL_0          1
 393 #define R300_ZS_CNTL_1          2
 394 #define R300_ZS_CNTL_2          3
 395 #define R300_ZS_CMDSIZE         4
 396
 397 #define R300_ZB_CMD_0           0
 398 #define R300_ZB_OFFSET          1
 399 #define R300_ZB_PITCH           2
 400 #define R300_ZB_CMDSIZE         3
 401
 402 #define R300_VPI_CMD_0          0
 403 #define R300_VPI_INSTR_0        1
 404 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 405
 406 #define R300_VPP_CMD_0          0
 407 #define R300_VPP_PARAM_0        1
 408 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 409
 410 #define R300_VPS_CMD_0          0
 411 #define R300_VPS_ZERO_0         1
 412 #define R300_VPS_ZERO_1         2
 413 #define R300_VPS_POINTSIZE      3
 414 #define R300_VPS_ZERO_3         4
 415 #define R300_VPS_CMDSIZE        5
 416
 417         /* the layout is common for all fields inside tex */
 418 #define R300_TEX_CMD_0          0
 419 #define R300_TEX_VALUE_0        1
 420 /* We don't really use this, instead specify mtu+1 dynamically
 421 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 422 */
 423
 424 /**
 425  * Cache for hardware register state.
 426  */
 427 struct r300_hw_state {
 428         struct r300_state_atom atomlist;
 429
 430         GLboolean       is_dirty;
 431         GLboolean       all_dirty;
 432         int             max_state_size; /* in dwords */
 433
 434         struct r300_state_atom vpt;     /* viewport (1D98) */
 435         struct r300_state_atom unk2080; /* (2080) */
 436         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 437         struct r300_state_atom vte;     /* (20B0) */
 438         struct r300_state_atom unk2134; /* (2134) */
 439         struct r300_state_atom unk2140; /* (2140) */
 440         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 441         struct r300_state_atom vic;     /* vap input control (2180) */
 442         struct r300_state_atom unk21DC; /* (21DC) */
 443         struct r300_state_atom unk221C; /* (221C) */
 444         struct r300_state_atom unk2220; /* (2220) */
 445         struct r300_state_atom unk2288; /* (2288) */
 446         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 447         struct r300_state_atom gb_enable; /* (4008) */
 448         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 449         struct r300_state_atom unk4200; /* (4200) */
 450         struct r300_state_atom unk4214; /* (4214) */
 451         struct r300_state_atom ps;      /* pointsize (421C) */
 452         struct r300_state_atom unk4230; /* (4230) */
 453         struct r300_state_atom lcntl;   /* line control */
 454         struct r300_state_atom unk4260; /* (4260) */
 455         struct r300_state_atom unk4274; /* (4274) */
 456         struct r300_state_atom unk4288; /* (4288) */
 457         struct r300_state_atom fogp;    /* fog parameters (4294) */
 458         struct r300_state_atom unk429C; /* (429C) */
 459         struct r300_state_atom unk42A0; /* (42A0) */
 460         struct r300_state_atom zbs;     /* zbias (42A4) */
 461         struct r300_state_atom unk42B4; /* (42B4) */
 462         struct r300_state_atom cul;     /* cull cntl (42B8) */
 463         struct r300_state_atom unk42C0; /* (42C0) */
 464         struct r300_state_atom rc;      /* rs control (4300) */
 465         struct r300_state_atom ri;      /* rs interpolators (4310) */
 466         struct r300_state_atom rr;      /* rs route (4330) */
 467         struct r300_state_atom unk43A4; /* (43A4) */
 468         struct r300_state_atom unk43E8; /* (43E8) */
 469         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 470         struct r300_state_atom fpt;     /* texi - (4620) */
 471         struct r300_state_atom unk46A4; /* (46A4) */
 472         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 473         struct r300_state_atom fogs;    /* fog state (4BC0) */
 474         struct r300_state_atom fogc;    /* fog color (4BC8) */
 475         struct r300_state_atom at;      /* alpha test (4BD4) */
 476         struct r300_state_atom unk4BD8; /* (4BD8) */
 477         struct r300_state_atom fpp;     /* 0x4C00 and following */
 478         struct r300_state_atom unk4E00; /* (4E00) */
 479         struct r300_state_atom bld;     /* blending (4E04) */
 480         struct r300_state_atom cmk;     /* colormask (4E0C) */
 481         struct r300_state_atom unk4E10; /* constant blend color + ??? (4E10) */
 482         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 483         struct r300_state_atom unk4E50; /* (4E50) */
 484         struct r300_state_atom unk4E88; /* (4E88) */
 485         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 486         struct r300_state_atom zs;      /* zstencil control (4F00) */
 487         struct r300_state_atom unk4F10; /* (4F10) */
 488         struct r300_state_atom zb;      /* z buffer (4F20) */
 489         struct r300_state_atom unk4F28; /* (4F28) */
 490         struct r300_state_atom unk4F30; /* (4F30) */
 491         struct r300_state_atom unk4F44; /* (4F44) */
 492         struct r300_state_atom unk4F54; /* (4F54) */
 493
 494         struct r300_state_atom vpi;     /* vp instructions */
 495         struct r300_state_atom vpp;     /* vp parameters */
 496         struct r300_state_atom vps;     /* vertex point size (?) */
 497                 /* 8 texture units */
 498                 /* the state is grouped by function and not by
 499                    texture unit. This makes single unit updates
 500                    really awkward - we are much better off
 501                    updating the whole thing at once */
 502         struct {
 503                 struct r300_state_atom filter;
 504                 struct r300_state_atom unknown1;
 505                 struct r300_state_atom size;
 506                 struct r300_state_atom format;
 507                 struct r300_state_atom pitch;
 508                 struct r300_state_atom offset;
 509                 struct r300_state_atom unknown4;
 510                 struct r300_state_atom border_color;
 511                 } tex;
 512         struct r300_state_atom txe;     /* tex enable (4104) */
 513 };
 514
 515
 516 /**
 517  * This structure holds the command buffer while it is being constructed.
 518  *
 519  * The first batch of commands in the buffer is always the state that needs
 520  * to be re-emitted when the context is lost. This batch can be skipped
 521  * otherwise.
 522  */
 523 struct r300_cmdbuf {
 524         int             size;           /* DWORDs allocated for buffer */
 525         uint32_t*       cmd_buf;
 526         int             count_used;     /* DWORDs filled so far */
 527         int             count_reemit;   /* size of re-emission batch */
 528 };
 529
 530
 531 /**
 532  * State cache
 533  */
 534
 535 struct r300_depthbuffer_state {
 536         GLfloat scale;
 537 };
 538
 539 struct r300_stencilbuffer_state {
 540         GLuint clear;
 541         GLboolean hw_stencil;
 542
 543 };
 544
 545 /* Vertex shader state */
 546
 547 /* Perhaps more if we store programs in vmem? */
 548 /* drm_r300_cmd_header_t->vpu->count is unsigned char */
 549 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
 550
 551 /* Can be tested with colormat currently. */
 552 #define VSF_MAX_FRAGMENT_TEMPS (14)
 553
 554 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
 555
 556 struct r300_vertex_shader_fragment {
 557         int length;
 558         union {
 559                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 560                 float f[VSF_MAX_FRAGMENT_LENGTH];
 561                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH/4];
 562                 } body;
 563         };
 564
 565 #define VSF_DEST_PROGRAM        0x0
 566 #define VSF_DEST_MATRIX0        0x200
 567 #define VSF_DEST_MATRIX1        0x204
 568 #define VSF_DEST_MATRIX2        0x208
 569 #define VSF_DEST_VECTOR0        0x20c
 570 #define VSF_DEST_VECTOR1        0x20d
 571 #define VSF_DEST_UNKNOWN1       0x400
 572 #define VSF_DEST_UNKNOWN2       0x406
 573
 574 struct r300_vertex_shader_state {
 575         struct r300_vertex_shader_fragment program;
 576
 577         /* a bit of a waste - each uses only a subset of allocated space..
 578             but easier to program */
 579         struct r300_vertex_shader_fragment matrix[3];
 580         struct r300_vertex_shader_fragment vector[2];
 581
 582         struct r300_vertex_shader_fragment unknown1;
 583         struct r300_vertex_shader_fragment unknown2;
 584
 585         int program_start;
 586         int unknown_ptr1;  /* pointer within program space */
 587         int program_end;
 588
 589         int param_offset;
 590         int param_count;
 591
 592         int unknown_ptr2;  /* pointer within program space */
 593         int unknown_ptr3;  /* pointer within program space */
 594         };
 595
 596 extern int hw_tcl_on;
 597
 598 //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 599 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 600
 601 /* Should but doesnt work */
 602 //#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
 603
 604 //#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && (OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit)))) :
 605 //      (r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit))))
 606 //#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit))) :
 607 //      ctx->Texture.Unit[unit]._ReallyEnabled && r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit)))
 608
 609 #define TMU_ENABLED(ctx, unit) (ctx->Texture.Unit[unit]._ReallyEnabled)
 610
 611 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 612  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 613  */
 614
 615 struct r300_vertex_program_key {
 616         GLuint InputsRead;
 617         GLuint OutputsWritten;
 618 };
 619
 620 struct r300_vertex_program {
 621         struct r300_vertex_program *next;
 622         struct r300_vertex_program_key key;
 623         int translated;
 624
 625         struct r300_vertex_shader_fragment program;
 626
 627         int pos_end;
 628         int num_temporaries; /* Number of temp vars used by program */
 629         int wpos_idx;
 630         int inputs[VERT_ATTRIB_MAX];
 631         int outputs[VERT_RESULT_MAX];
 632         int native;
 633         int ref_count;
 634         int use_ref_count;
 635 };
 636
 637 struct r300_vertex_program_cont {
 638         struct gl_vertex_program mesa_program; /* Must be first */
 639         struct r300_vertex_shader_fragment params;
 640         struct r300_vertex_program *progs;
 641 };
 642
 643 #define PFS_MAX_ALU_INST        64
 644 #define PFS_MAX_TEX_INST        64
 645 #define PFS_MAX_TEX_INDIRECT 4
 646 #define PFS_NUM_TEMP_REGS       32
 647 #define PFS_NUM_CONST_REGS      16
 648
 649 /* Tracking data for Mesa registers */
 650 struct reg_acc {
 651        int reg;        /* Assigned hw temp */
 652        unsigned int refcount; /* Number of uses by mesa program */
 653 };
 654
 655 struct r300_pfs_compile_state {
 656        int v_pos, s_pos;       /* highest ALU slots used */
 657
 658        /* Track some information gathered during opcode
 659         * construction.
 660         *
 661         * NOTE: Data is only set by the code, and isn't used yet.
 662         */
 663        struct {
 664                int vsrc[3];
 665                int ssrc[3];
 666                int umask;
 667        } slot[PFS_MAX_ALU_INST];
 668
 669        /* Used to map Mesa's inputs/temps onto hardware temps */
 670        int temp_in_use;
 671        struct reg_acc temps[PFS_NUM_TEMP_REGS];
 672        struct reg_acc inputs[32]; /* don't actually need 32... */
 673
 674        /* Track usage of hardware temps, for register allocation,
 675         * indirection detection, etc. */
 676        int hwreg_in_use;
 677        GLuint used_in_node;
 678        GLuint dest_in_node;
 679 };
 680
 681 struct r300_fragment_program {
 682         struct gl_fragment_program mesa_program;
 683
 684         GLcontext *ctx;
 685         GLboolean translated;
 686         GLboolean error;
 687         struct r300_pfs_compile_state *cs;
 688
 689         struct {
 690                 int length;
 691                 GLuint inst[PFS_MAX_TEX_INST];
 692         } tex;
 693
 694         struct {
 695                 struct {
 696                         GLuint inst0;
 697                         GLuint inst1;
 698                         GLuint inst2;
 699                         GLuint inst3;
 700                 } inst[PFS_MAX_ALU_INST];
 701         } alu;
 702
 703         struct {
 704                 int tex_offset;
 705                 int tex_end;
 706                 int alu_offset;
 707                 int alu_end;
 708                 int flags;
 709         } node[4];
 710         int cur_node;
 711         int first_node_has_tex;
 712
 713         int alu_offset;
 714         int alu_end;
 715         int tex_offset;
 716         int tex_end;
 717
 718         /* Hardware constants */
 719         GLfloat constant[PFS_NUM_CONST_REGS][4];
 720         int const_nr;
 721
 722         /* Tracked parameters */
 723         struct {
 724                 int idx;                        /* hardware index */
 725                 GLfloat *values;        /* pointer to values */
 726         } param[PFS_NUM_CONST_REGS];
 727         int param_nr;
 728         GLboolean params_uptodate;
 729
 730         int max_temp_idx;
 731
 732         /* the index of the sin constant is stored here */
 733         GLint const_sin[2];
 734
 735         GLuint optimization;
 736 };
 737
 738 #define R300_MAX_AOS_ARRAYS             16
 739
 740 #define AOS_FORMAT_USHORT       0
 741 #define AOS_FORMAT_FLOAT        1
 742 #define AOS_FORMAT_UBYTE        2
 743 #define AOS_FORMAT_FLOAT_COLOR  3
 744
 745 #define REG_COORDS      0
 746 #define REG_COLOR0      1
 747 #define REG_TEX0        2
 748
 749 struct dt {
 750         GLint size;
 751         GLenum type;
 752         GLsizei stride;
 753         void *data;
 754 };
 755
 756 struct radeon_vertex_buffer {
 757         int Count;
 758         void *Elts;
 759         int elt_size;
 760         int elt_min, elt_max; /* debug */
 761
 762         struct dt AttribPtr[VERT_ATTRIB_MAX];
 763
 764         const struct _mesa_prim  *Primitive;
 765         GLuint      PrimitiveCount;
 766         GLint LockFirst;
 767         GLsizei LockCount;
 768         int lock_uptodate;
 769 };
 770
 771 struct r300_aos_rec {
 772         GLuint offset;
 773         int element_size; /* in dwords */
 774         int stride;       /* distance between elements, in dwords */
 775
 776         int format;
 777
 778         int ncomponents; /* number of components - between 1 and 4, inclusive */
 779
 780         int reg; /* which register they are assigned to. */
 781
 782         };
 783
 784 struct r300_state {
 785         struct r300_depthbuffer_state depth;
 786         struct r300_texture_state texture;
 787         int sw_tcl_inputs[VERT_ATTRIB_MAX];
 788         struct r300_vertex_shader_state vertex_shader;
 789         struct r300_pfs_compile_state pfs_compile;
 790         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 791         int aos_count;
 792         struct radeon_vertex_buffer VB;
 793
 794         GLuint *Elts;
 795         struct r300_dma_region elt_dma;
 796
 797         DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for.
 798                                  They are the same as tnl->render_inputs for fixed pipeline */
 799
 800         struct {
 801                 int transform_offset;  /* Transform matrix offset, -1 if none */
 802                 } vap_param;  /* vertex processor parameter allocation - tells where to write parameters */
 803
 804         struct r300_stencilbuffer_state stencil;
 805
 806 };
 807
 808 #define R300_FALLBACK_NONE 0
 809 #define R300_FALLBACK_TCL 1
 810 #define R300_FALLBACK_RAST 2
 811
 812 /**
 813  * R300 context structure.
 814  */
 815 struct r300_context {
 816         struct radeon_context radeon; /* parent class, must be first */
 817
 818         struct r300_hw_state hw;
 819         struct r300_cmdbuf cmdbuf;
 820         struct r300_state state;
 821         struct gl_vertex_program *curr_vp;
 822         struct r300_vertex_program *selected_vp;
 823
 824         /* Vertex buffers
 825          */
 826         struct r300_dma dma;
 827         GLboolean save_on_next_unlock;
 828         GLuint NewGLState;
 829
 830         /* Texture object bookkeeping
 831          */
 832         unsigned nr_heaps;
 833         driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
 834         driTextureObject swapped;
 835         int texture_depth;
 836         float initialMaxAnisotropy;
 837
 838         /* Clientdata textures;
 839          */
 840         GLuint prefer_gart_client_texturing;
 841
 842 #ifdef USER_BUFFERS
 843         struct radeon_memory_manager *rmm;
 844         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 845         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 846 #endif
 847
 848         GLboolean texmicrotile;
 849         GLboolean span_dlocking;
 850         GLboolean disable_lowimpact_fallback;
 851 };
 852
 853 struct r300_buffer_object {
 854         struct gl_buffer_object mesa_obj;
 855         int id;
 856 };
 857
 858 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 859
 860 static __inline GLuint r300PackColor( GLuint cpp,
 861                                         GLubyte r, GLubyte g,
 862                                         GLubyte b, GLubyte a )
 863 {
 864    switch ( cpp ) {
 865    case 2:
 866       return PACK_COLOR_565( r, g, b );
 867    case 4:
 868       return PACK_COLOR_8888( r, g, b, a );
 869    default:
 870       return 0;
 871    }
 872 }
 873 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 874 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 875                                    __DRIcontextPrivate * driContextPriv,
 876                                    void *sharedContextPrivate);
 877
 878 extern int r300_get_num_verts(r300ContextPtr rmesa, int num_verts, int prim);
 879
 880 extern void r300_select_vertex_shader(r300ContextPtr r300);
 881 extern void r300InitShaderFuncs(struct dd_function_table *functions);
 882 extern int r300VertexProgUpdateParams(GLcontext *ctx, struct r300_vertex_program_cont *vp, float *dst);
 883 extern int r300Fallback(GLcontext *ctx);
 884
 885 extern void radeon_vb_to_rvb(r300ContextPtr rmesa, struct radeon_vertex_buffer *rvb, struct vertex_buffer *vb);
 886 extern GLboolean r300_run_vb_render(GLcontext *ctx, struct tnl_pipeline_stage *stage);
 887
 888 #ifdef RADEON_VTXFMT_A
 889 extern void radeon_init_vtxfmt_a(r300ContextPtr rmesa);
 890 #endif
 891
 892 #ifdef HW_VBOS
 893 extern void r300_init_vbo_funcs(struct dd_function_table *functions);
 894 extern void r300_evict_vbos(GLcontext *ctx, int amount);
 895 #endif
 896
 897 #define RADEON_D_CAPTURE 0
 898 #define RADEON_D_PLAYBACK 1
 899 #define RADEON_D_PLAYBACK_RAW 2
 900 #define RADEON_D_T 3
 901
 902 #endif                          /* __R300_CONTEXT_H__ */