src/mesa/drivers/dri/r300/r300_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *   Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R300_CONTEXT_H__
  37 #define __R300_CONTEXT_H__
  38
  39 #include "tnl/t_vertex.h"
  40 #include "drm.h"
  41 #include "radeon_drm.h"
  42 #include "dri_util.h"
  43 #include "texmem.h"
  44
  45 #include "macros.h"
  46 #include "mtypes.h"
  47 #include "colormac.h"
  48 #include "radeon_context.h"
  49
  50 struct r300_context;
  51 typedef struct r300_context r300ContextRec;
  52 typedef struct r300_context *r300ContextPtr;
  53
  54 #include "radeon_lock.h"
  55 #include "mm.h"
  56
  57 /* Checkpoint.. for convenience */
  58 #define CPT     { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
  59 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  60    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  61    with other compilers ... GLUE!
  62 */
  63 #define WARN_ONCE(a, ...)       { \
  64         static int warn##__LINE__=1; \
  65         if(warn##__LINE__){ \
  66                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  67                 fprintf(stderr, "File %s function %s line %d\n", \
  68                         __FILE__, __FUNCTION__, __LINE__); \
  69                 fprintf(stderr,  a, ## __VA_ARGS__);\
  70                 fprintf(stderr, "***************************************************************************\n"); \
  71                 warn##__LINE__=0;\
  72                 } \
  73         }
  74
  75 typedef GLuint uint32_t;
  76 typedef GLubyte uint8_t;
  77
  78   /* We should probably change types within vertex_shader
  79       and pixel_shader structure later on */
  80 #define CARD32 GLuint
  81 #include "vertex_shader.h"
  82 #include "pixel_shader.h"
  83 #undef CARD32
  84
  85 static __inline__ uint32_t r300PackFloat32(float fl)
  86 {
  87         union { float fl; uint32_t u; } u;
  88
  89         u.fl = fl;
  90         return u.u;
  91 }
  92
  93
  94 /************ DMA BUFFERS **************/
  95
  96 /* Need refcounting on dma buffers:
  97  */
  98 struct r300_dma_buffer {
  99         int refcount;           /* the number of retained regions in buf */
 100         drmBufPtr buf;
 101 };
 102
 103 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset +                \
 104                         (rvb)->address - rmesa->dma.buf0_address +      \
 105                         (rvb)->start)
 106
 107 /* A retained region, eg vertices for indexed vertices.
 108  */
 109 struct r300_dma_region {
 110         struct r300_dma_buffer *buf;
 111         char *address;          /* == buf->address */
 112         int start, end, ptr;    /* offsets from start of buf */
 113
 114     int aos_offset;     /* address in GART memory */
 115     int aos_stride;     /* distance between elements, in dwords */
 116     int aos_size;       /* number of components (1-4) */
 117     int aos_format;     /* format of components */
 118     int aos_reg;        /* VAP register assignment */
 119
 120 /* Left here so immediate mode still works unmodified */
 121         int element_size;
 122         int stride;
 123         int offset;
 124         int ncomponents;
 125         int reg;
 126         int format;
 127 };
 128
 129 struct r300_dma {
 130         /* Active dma region.  Allocations for vertices and retained
 131          * regions come from here.  Also used for emitting random vertices,
 132          * these may be flushed by calling flush_current();
 133          */
 134         struct r300_dma_region current;
 135
 136         void (*flush) (r300ContextPtr);
 137
 138         char *buf0_address;     /* start of buf[0], for index calcs */
 139         GLuint nr_released_bufs;        /* flush after so many buffers released */
 140 };
 141
 142        /* Texture related */
 143
 144 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
 145
 146 /* Texture object in locally shared texture space.
 147  */
 148 struct r300_tex_obj {
 149         driTextureObject base;
 150
 151         GLuint bufAddr;         /* Offset to start of locally
 152                                    shared texture block */
 153
 154         GLuint dirty_state;     /* Flags (1 per texunit) for
 155                                    whether or not this texobj
 156                                    has dirty hardware state
 157                                    (pp_*) that needs to be
 158                                    brought into the
 159                                    texunit. */
 160
 161         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 162         /* Six, for the cube faces */
 163
 164
 165         /* hardware register values */
 166         /* Note that R200 has 8 registers per texture and R300 only 7 */
 167         GLuint filter;
 168         GLuint pitch; /* one of the unknown registers.. unknown 1 ?*/
 169         GLuint size;    /* npot only */
 170         GLuint format;
 171         GLuint offset;  /* Image location in texmem.
 172                                    All cube faces follow. */
 173         GLuint unknown4;
 174         GLuint unknown5;
 175         /* end hardware registers */
 176
 177         /* registers computed by r200 code - keep them here to
 178            compare against what is actually written.
 179
 180            to be removed later.. */
 181         GLuint pp_border_color;
 182         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 183         GLuint format_x;
 184
 185
 186         GLboolean border_fallback;
 187 };
 188
 189 struct r300_texture_env_state {
 190         r300TexObjPtr texobj;
 191         GLenum format;
 192         GLenum envMode;
 193 };
 194
 195 #define R300_MAX_TEXTURE_UNITS 8
 196
 197 struct r300_texture_state {
 198         struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
 199         int tc_count; /* number of incoming texture coordinates from VAP */
 200 };
 201
 202 /**
 203  * A block of hardware state.
 204  *
 205  * When check returns non-zero, the returned number of dwords must be
 206  * copied verbatim into the command buffer in order to update a state atom
 207  * when it is dirty.
 208  */
 209 struct r300_state_atom {
 210         struct r300_state_atom *next, *prev;
 211         const char* name;       /* for debug */
 212         int cmd_size;           /* maximum size in dwords */
 213         GLuint idx;             /* index in an array (e.g. textures) */
 214         uint32_t* cmd;
 215         GLboolean dirty;
 216
 217         int (*check)(r300ContextPtr, struct r300_state_atom* atom);
 218 };
 219
 220
 221 #define R300_VPT_CMD_0          0
 222 #define R300_VPT_XSCALE         1
 223 #define R300_VPT_XOFFSET        2
 224 #define R300_VPT_YSCALE         3
 225 #define R300_VPT_YOFFSET        4
 226 #define R300_VPT_ZSCALE         5
 227 #define R300_VPT_ZOFFSET        6
 228 #define R300_VPT_CMDSIZE        7
 229
 230 #define R300_VIR_CMD_0          0 /* vir is variable size (at least 1) */
 231 #define R300_VIR_CNTL_0         1
 232 #define R300_VIR_CNTL_1         2
 233 #define R300_VIR_CNTL_2         3
 234 #define R300_VIR_CNTL_3         4
 235 #define R300_VIR_CNTL_4         5
 236 #define R300_VIR_CNTL_5         6
 237 #define R300_VIR_CNTL_6         7
 238 #define R300_VIR_CNTL_7         8
 239 #define R300_VIR_CMDSIZE        9
 240
 241 #define R300_VIC_CMD_0          0
 242 #define R300_VIC_CNTL_0         1
 243 #define R300_VIC_CNTL_1         2
 244 #define R300_VIC_CMDSIZE        3
 245
 246 #define R300_VOF_CMD_0          0
 247 #define R300_VOF_CNTL_0         1
 248 #define R300_VOF_CNTL_1         2
 249 #define R300_VOF_CMDSIZE        3
 250
 251
 252 #define R300_PVS_CMD_0          0
 253 #define R300_PVS_CNTL_1         1
 254 #define R300_PVS_CNTL_2         2
 255 #define R300_PVS_CNTL_3         3
 256 #define R300_PVS_CMDSIZE        4
 257
 258 #define R300_GB_MISC_CMD_0              0
 259 #define R300_GB_MISC_MSPOS_0            1
 260 #define R300_GB_MISC_MSPOS_1            2
 261 #define R300_GB_MISC_TILE_CONFIG        3
 262 #define R300_GB_MISC_SELECT             4
 263 #define R300_GB_MISC_AA_CONFIG          5
 264 #define R300_GB_MISC_CMDSIZE            6
 265
 266 #define R300_TXE_CMD_0          0
 267 #define R300_TXE_ENABLE         1
 268 #define R300_TXE_CMDSIZE        2
 269
 270 #define R300_PS_CMD_0           0
 271 #define R300_PS_POINTSIZE       1
 272 #define R300_PS_CMDSIZE         2
 273
 274 #define R300_ZBS_CMD_0          0
 275 #define R300_ZBS_T_FACTOR       1
 276 #define R300_ZBS_T_CONSTANT     2
 277 #define R300_ZBS_W_FACTOR       3
 278 #define R300_ZBS_W_CONSTANT     4
 279 #define R300_ZBS_CMDSIZE        5
 280
 281 #define R300_CUL_CMD_0          0
 282 #define R300_CUL_CULL           1
 283 #define R300_CUL_CMDSIZE        2
 284
 285 #define R300_RC_CMD_0           0
 286 #define R300_RC_CNTL_0          1
 287 #define R300_RC_CNTL_1          2
 288 #define R300_RC_CMDSIZE         3
 289
 290 #define R300_RI_CMD_0           0
 291 #define R300_RI_INTERP_0        1
 292 #define R300_RI_INTERP_1        2
 293 #define R300_RI_INTERP_2        3
 294 #define R300_RI_INTERP_3        4
 295 #define R300_RI_INTERP_4        5
 296 #define R300_RI_INTERP_5        6
 297 #define R300_RI_INTERP_6        7
 298 #define R300_RI_INTERP_7        8
 299 #define R300_RI_CMDSIZE         9
 300
 301 #define R300_RR_CMD_0           0 /* rr is variable size (at least 1) */
 302 #define R300_RR_ROUTE_0         1
 303 #define R300_RR_ROUTE_1         2
 304 #define R300_RR_ROUTE_2         3
 305 #define R300_RR_ROUTE_3         4
 306 #define R300_RR_ROUTE_4         5
 307 #define R300_RR_ROUTE_5         6
 308 #define R300_RR_ROUTE_6         7
 309 #define R300_RR_ROUTE_7         8
 310 #define R300_RR_CMDSIZE         9
 311
 312 #define R300_FP_CMD_0           0
 313 #define R300_FP_CNTL0           1
 314 #define R300_FP_CNTL1           2
 315 #define R300_FP_CNTL2           3
 316 #define R300_FP_CMD_1           4
 317 #define R300_FP_NODE0           5
 318 #define R300_FP_NODE1           6
 319 #define R300_FP_NODE2           7
 320 #define R300_FP_NODE3           8
 321 #define R300_FP_CMDSIZE         9
 322
 323 #define R300_FPT_CMD_0          0
 324 #define R300_FPT_INSTR_0        1
 325 #define R300_FPT_CMDSIZE        65
 326
 327 #define R300_FPI_CMD_0          0
 328 #define R300_FPI_INSTR_0        1
 329 #define R300_FPI_CMDSIZE        65
 330
 331 #define R300_FPP_CMD_0          0
 332 #define R300_FPP_PARAM_0        1
 333 #define R300_FPP_CMDSIZE        (32*4+1)
 334
 335 #define R300_AT_CMD_0           0
 336 #define R300_AT_ALPHA_TEST      1
 337 #define R300_AT_UNKNOWN         2
 338 #define R300_AT_CMDSIZE         3
 339
 340 #define R300_BLD_CMD_0          0
 341 #define R300_BLD_CBLEND         1
 342 #define R300_BLD_ABLEND         2
 343 #define R300_BLD_CMDSIZE        3
 344
 345 #define R300_CMK_CMD_0          0
 346 #define R300_CMK_COLORMASK      1
 347 #define R300_CMK_CMDSIZE        2
 348
 349 #define R300_CB_CMD_0           0
 350 #define R300_CB_OFFSET          1
 351 #define R300_CB_CMD_1           2
 352 #define R300_CB_PITCH           3
 353 #define R300_CB_CMDSIZE         4
 354
 355 #define R300_ZS_CMD_0           0
 356 #define R300_ZS_CNTL_0          1
 357 #define R300_ZS_CNTL_1          2
 358 #define R300_ZS_CNTL_2          3
 359 #define R300_ZS_CMDSIZE         4
 360
 361 #define R300_ZB_CMD_0           0
 362 #define R300_ZB_OFFSET          1
 363 #define R300_ZB_PITCH           2
 364 #define R300_ZB_CMDSIZE         3
 365
 366 #define R300_VPI_CMD_0          0
 367 #define R300_VPI_INSTR_0        1
 368 #define R300_VPI_CMDSIZE        1025 /* 256 16 byte instructions */
 369
 370 #define R300_VPP_CMD_0          0
 371 #define R300_VPP_PARAM_0        1
 372 #define R300_VPP_CMDSIZE        1025 /* 256 4-component parameters */
 373
 374 #define R300_VPS_CMD_0          0
 375 #define R300_VPS_ZERO_0         1
 376 #define R300_VPS_ZERO_1         2
 377 #define R300_VPS_POINTSIZE      3
 378 #define R300_VPS_ZERO_3         4
 379 #define R300_VPS_CMDSIZE        5
 380
 381         /* the layout is common for all fields inside tex */
 382 #define R300_TEX_CMD_0          0
 383 #define R300_TEX_VALUE_0        1
 384 /* We don't really use this, instead specify mtu+1 dynamically
 385 #define R300_TEX_CMDSIZE        (MAX_TEXTURE_UNITS+1)
 386 */
 387
 388 /**
 389  * Cache for hardware register state.
 390  */
 391 struct r300_hw_state {
 392         struct r300_state_atom atomlist;
 393
 394         GLboolean       is_dirty;
 395         GLboolean       all_dirty;
 396         int             max_state_size; /* in dwords */
 397
 398         struct r300_state_atom vpt;     /* viewport (1D98) */
 399         struct r300_state_atom unk2080; /* (2080) */
 400         struct r300_state_atom vof;     /* VAP output format register 0x2090 */
 401         struct r300_state_atom vte;     /* (20B0) */
 402         struct r300_state_atom unk2134; /* (2134) */
 403         struct r300_state_atom unk2140; /* (2140) */
 404         struct r300_state_atom vir[2];  /* vap input route (2150/21E0) */
 405         struct r300_state_atom vic;     /* vap input control (2180) */
 406         struct r300_state_atom unk21DC; /* (21DC) */
 407         struct r300_state_atom unk221C; /* (221C) */
 408         struct r300_state_atom unk2220; /* (2220) */
 409         struct r300_state_atom unk2288; /* (2288) */
 410         struct r300_state_atom pvs;     /* pvs_cntl (22D0) */
 411         struct r300_state_atom gb_enable; /* (4008) */
 412         struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
 413         struct r300_state_atom unk4200; /* (4200) */
 414         struct r300_state_atom unk4214; /* (4214) */
 415         struct r300_state_atom ps;      /* pointsize (421C) */
 416         struct r300_state_atom unk4230; /* (4230) */
 417         struct r300_state_atom lcntl;   /* line control */
 418 #ifdef EXP_C
 419         struct r300_state_atom lsf;     /* line stipple factor */
 420 #endif
 421         struct r300_state_atom dummy[4];
 422         struct r300_state_atom unk4260; /* (4260) */
 423         struct r300_state_atom unk4274; /* (4274) */
 424         struct r300_state_atom unk4288; /* (4288) */
 425         struct r300_state_atom unk42A0; /* (42A0) */
 426         struct r300_state_atom zbs;     /* zbias (42A4) */
 427         struct r300_state_atom unk42B4; /* (42B4) */
 428         struct r300_state_atom cul;     /* cull cntl (42B8) */
 429         struct r300_state_atom unk42C0; /* (42C0) */
 430         struct r300_state_atom rc;      /* rs control (4300) */
 431         struct r300_state_atom ri;      /* rs interpolators (4310) */
 432         struct r300_state_atom rr;      /* rs route (4330) */
 433         struct r300_state_atom unk43A4; /* (43A4) */
 434         struct r300_state_atom unk43E8; /* (43E8) */
 435         struct r300_state_atom fp;      /* fragment program cntl + nodes (4600) */
 436         struct r300_state_atom fpt;     /* texi - (4620) */
 437         struct r300_state_atom unk46A4; /* (46A4) */
 438         struct r300_state_atom fpi[4];  /* fp instructions (46C0/47C0/48C0/49C0) */
 439         struct r300_state_atom unk4BC0; /* (4BC0) */
 440         struct r300_state_atom unk4BC8; /* (4BC8) */
 441         struct r300_state_atom at;      /* alpha test (4BD4) */
 442         struct r300_state_atom unk4BD8; /* (4BD8) */
 443         struct r300_state_atom fpp;     /* 0x4C00 and following */
 444         struct r300_state_atom unk4E00; /* (4E00) */
 445         struct r300_state_atom bld;     /* blending (4E04) */
 446         struct r300_state_atom cmk;     /* colormask (4E0C) */
 447         struct r300_state_atom unk4E10; /* (4E10) */
 448         struct r300_state_atom cb;      /* colorbuffer (4E28) */
 449         struct r300_state_atom unk4E50; /* (4E50) */
 450         struct r300_state_atom unk4E88; /* (4E88) */
 451         struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware..  */
 452         struct r300_state_atom zs;      /* zstencil control (4F00) */
 453         struct r300_state_atom unk4F10; /* (4F10) */
 454         struct r300_state_atom zb;      /* z buffer (4F20) */
 455         struct r300_state_atom unk4F28; /* (4F28) */
 456         struct r300_state_atom unk4F30; /* (4F30) */
 457         struct r300_state_atom unk4F44; /* (4F44) */
 458         struct r300_state_atom unk4F54; /* (4F54) */
 459
 460         struct r300_state_atom vpi;     /* vp instructions */
 461         struct r300_state_atom vpp;     /* vp parameters */
 462         struct r300_state_atom vps;     /* vertex point size (?) */
 463
 464                 /* 8 texture units */
 465                 /* the state is grouped by function and not by
 466                    texture unit. This makes single unit updates
 467                    really awkward - we are much better off
 468                    updating the whole thing at once */
 469         struct {
 470                 struct r300_state_atom filter;
 471                 struct r300_state_atom unknown1;
 472                 struct r300_state_atom size;
 473                 struct r300_state_atom format;
 474                 struct r300_state_atom offset;
 475                 struct r300_state_atom unknown4;
 476                 struct r300_state_atom border_color;
 477                 } tex;
 478         struct r300_state_atom txe;     /* tex enable (4104) */
 479 };
 480
 481
 482 /**
 483  * This structure holds the command buffer while it is being constructed.
 484  *
 485  * The first batch of commands in the buffer is always the state that needs
 486  * to be re-emitted when the context is lost. This batch can be skipped
 487  * otherwise.
 488  */
 489 struct r300_cmdbuf {
 490         int             size;           /* DWORDs allocated for buffer */
 491         uint32_t*       cmd_buf;
 492         int             count_used;     /* DWORDs filled so far */
 493         int             count_reemit;   /* size of re-emission batch */
 494 };
 495
 496
 497 /**
 498  * State cache
 499  */
 500
 501 struct r300_depthbuffer_state {
 502         GLfloat scale;
 503 };
 504
 505 struct r300_vap_reg_state {
 506            /* input register assigments */
 507            int i_coords;
 508            int i_normal;
 509            int i_color[2];
 510            int i_fog;
 511            int i_tex[R300_MAX_TEXTURE_UNITS];
 512            int i_index;
 513            int i_pointsize;
 514         };
 515
 516 /* Vertex shader state */
 517
 518 /* 64 appears to be the maximum */
 519 #define VSF_MAX_FRAGMENT_LENGTH 64
 520
 521
 522 struct r300_vertex_shader_fragment {
 523         int length;
 524         union {
 525                 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
 526                 float f[VSF_MAX_FRAGMENT_LENGTH];
 527                 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH/4];
 528                 } body;
 529         };
 530
 531 #define VSF_DEST_PROGRAM        0x0
 532 #define VSF_DEST_MATRIX0        0x200
 533 #define VSF_DEST_MATRIX1        0x204
 534 #define VSF_DEST_MATRIX2        0x208
 535 #define VSF_DEST_VECTOR0        0x20c
 536 #define VSF_DEST_VECTOR1        0x20d
 537 #define VSF_DEST_UNKNOWN1       0x400
 538 #define VSF_DEST_UNKNOWN2       0x406
 539
 540 struct r300_vertex_shader_state {
 541         struct r300_vertex_shader_fragment program;
 542
 543         /* a bit of a waste - each uses only a subset of allocated space..
 544             but easier to program */
 545         struct r300_vertex_shader_fragment matrix[3];
 546         struct r300_vertex_shader_fragment vector[2];
 547
 548         struct r300_vertex_shader_fragment unknown1;
 549         struct r300_vertex_shader_fragment unknown2;
 550
 551         int program_start;
 552         int unknown_ptr1;  /* pointer within program space */
 553         int program_end;
 554
 555         int param_offset;
 556         int param_count;
 557
 558         int unknown_ptr2;  /* pointer within program space */
 559         int unknown_ptr3;  /* pointer within program space */
 560         };
 561
 562 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
 563  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
 564  */
 565 struct r300_vertex_program {
 566         struct vertex_program mesa_program; /* Must be first */
 567         int translated;
 568
 569         struct r300_vertex_shader_fragment program;
 570         struct r300_vertex_shader_fragment params;
 571
 572         int t2rs;
 573         unsigned long num_temporaries; /* Number of temp vars used by program */
 574         int inputs[VERT_ATTRIB_MAX];
 575 };
 576
 577 /* 64 appears to be the maximum */
 578 #define PSF_MAX_PROGRAM_LENGTH 64
 579
 580 struct r300_pixel_shader_program {
 581         struct {
 582                 int length;
 583                 GLuint inst[PSF_MAX_PROGRAM_LENGTH];
 584                 } tex;
 585
 586         /* ALU intructions (logic and integer) */
 587         struct {
 588                 int length;
 589                 struct {
 590                         GLuint inst0;
 591                         GLuint inst1;
 592                         GLuint inst2;
 593                         GLuint inst3;
 594                         } inst[PSF_MAX_PROGRAM_LENGTH];
 595                 } alu;
 596
 597         /* node information */
 598         /* nodes are used to synchronize ALU and TEX streams */
 599         /* There could be up to 4 nodes each consisting of
 600            a number of TEX instructions followed by some ALU
 601            instructions */
 602         /* the last node of a program should always be node3 */
 603         struct {
 604                 int tex_offset;
 605                 int tex_end;
 606                 int alu_offset;
 607                 int alu_end;
 608                 } node[4];
 609
 610         int active_nodes;       /* must be between 1 and 4, inclusive */
 611         int first_node_has_tex;  /* other nodes always have it */
 612
 613         int temp_register_count;  /* magic value goes into PFS_CNTL_1 */
 614
 615         /* entire program */
 616         int tex_offset;
 617         int tex_end;
 618         int alu_offset;
 619         int alu_end;
 620
 621         };
 622
 623 #define MAX_PIXEL_SHADER_PARAMS 32
 624 struct r300_pixel_shader_state {
 625         struct r300_pixel_shader_program program;
 626
 627         /* parameters */
 628         int param_length;  /* to limit the number of unnecessary writes */
 629         struct {
 630                 float x;
 631                 float y;
 632                 float z;
 633                 float w;
 634                 } param[MAX_PIXEL_SHADER_PARAMS];
 635         };
 636
 637 /* 8 is somewhat bogus... it is probably something like 24 */
 638 #define R300_MAX_AOS_ARRAYS             8
 639
 640 #define AOS_FORMAT_FLOAT        1
 641 #define AOS_FORMAT_UBYTE        2
 642 #define AOS_FORMAT_FLOAT_COLOR  3
 643
 644 #define REG_COORDS      0
 645 #define REG_COLOR0      1
 646 #define REG_TEX0        2
 647
 648 struct r300_aos_rec {
 649         GLuint offset;
 650         int element_size; /* in dwords */
 651         int stride;       /* distance between elements, in dwords */
 652
 653         int format;
 654
 655         int ncomponents; /* number of components - between 1 and 4, inclusive */
 656
 657         int reg; /* which register they are assigned to. */
 658
 659         };
 660
 661 struct r300_state {
 662         struct r300_depthbuffer_state depth;
 663         struct r300_texture_state texture;
 664         struct r300_vap_reg_state vap_reg;
 665         struct r300_vertex_shader_state vertex_shader;
 666         struct r300_pixel_shader_state pixel_shader;
 667
 668         struct r300_dma_region aos[R300_MAX_AOS_ARRAYS];
 669         int aos_count;
 670
 671         GLuint *Elts;
 672
 673         GLuint render_inputs; /* actual render inputs that R300 was configured for.
 674                                  They are the same as tnl->render_inputs for fixed pipeline */
 675
 676         int hw_stencil;
 677 };
 678
 679
 680 /**
 681  * R300 context structure.
 682  */
 683 struct r300_context {
 684         struct radeon_context radeon; /* parent class, must be first */
 685
 686         struct r300_hw_state hw;
 687         struct r300_cmdbuf cmdbuf;
 688         struct r300_state state;
 689
 690         /* Vertex buffers
 691          */
 692         struct r300_dma dma;
 693         GLboolean save_on_next_unlock;
 694
 695         /* Texture object bookkeeping
 696          */
 697         unsigned nr_heaps;
 698         driTexHeap *texture_heaps[R200_NR_TEX_HEAPS];
 699         driTextureObject swapped;
 700         int texture_depth;
 701         float initialMaxAnisotropy;
 702
 703         /* Clientdata textures;
 704          */
 705         GLuint prefer_gart_client_texturing;
 706
 707         /* TCL stuff
 708          */
 709         GLmatrix TexGenMatrix[R300_MAX_TEXTURE_UNITS];
 710         GLboolean recheck_texgen[R300_MAX_TEXTURE_UNITS];
 711         GLboolean TexGenNeedNormals[R300_MAX_TEXTURE_UNITS];
 712         GLuint TexMatEnabled;
 713         GLuint TexMatCompSel;
 714         GLuint TexGenEnabled;
 715         GLuint TexGenInputs;
 716         GLuint TexGenCompSel;
 717         GLmatrix tmpmat;
 718
 719         struct r300_vertex_program *current_vp;
 720 };
 721
 722 #define R300_CONTEXT(ctx)               ((r300ContextPtr)(ctx->DriverCtx))
 723
 724 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
 725 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 726                                    __DRIcontextPrivate * driContextPriv,
 727                                    void *sharedContextPrivate);
 728
 729 extern void r300InitVertexProgFuncs(struct dd_function_table *functions);
 730 extern void r300VertexProgUpdateParams(GLcontext *ctx, struct r300_vertex_program *vp);
 731
 732 #endif                          /* __R300_CONTEXT_H__ */