2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
33 * Nicolai Haehnle <prefect_@gmx.net>
36 #ifndef __R300_CONTEXT_H__
37 #define __R300_CONTEXT_H__
39 #include "tnl/t_vertex.h"
41 #include "radeon_drm.h"
48 #include "radeon_context.h"
51 typedef struct r300_context r300ContextRec
;
52 typedef struct r300_context
*r300ContextPtr
;
54 #include "radeon_lock.h"
57 /* Checkpoint.. for convenience */
58 #define CPT { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
59 /* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
60 I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
61 with other compilers ... GLUE!
63 #define WARN_ONCE(a, ...) { \
64 static int warn##__LINE__=1; \
66 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
67 fprintf(stderr, "File %s function %s line %d\n", \
68 __FILE__, __FUNCTION__, __LINE__); \
69 fprintf(stderr, a, ## __VA_ARGS__);\
70 fprintf(stderr, "***************************************************************************\n"); \
75 typedef GLuint
uint32_t;
76 typedef GLubyte
uint8_t;
78 /* We should probably change types within vertex_shader
79 and pixel_shader structure later on */
81 #include "vertex_shader.h"
82 #include "pixel_shader.h"
85 static __inline__
uint32_t r300PackFloat32(float fl
)
87 union { float fl
; uint32_t u
; } u
;
94 /************ DMA BUFFERS **************/
96 /* Need refcounting on dma buffers:
98 struct r300_dma_buffer
{
99 int refcount
; /* the number of retained regions in buf */
103 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \
104 (rvb)->address - rmesa->dma.buf0_address + \
107 /* A retained region, eg vertices for indexed vertices.
109 struct r300_dma_region
{
110 struct r300_dma_buffer
*buf
;
111 char *address
; /* == buf->address */
112 int start
, end
, ptr
; /* offsets from start of buf */
114 int aos_offset
; /* address in GART memory */
115 int aos_stride
; /* distance between elements, in dwords */
116 int aos_size
; /* number of components (1-4) */
117 int aos_format
; /* format of components */
118 int aos_reg
; /* VAP register assignment */
122 /* Active dma region. Allocations for vertices and retained
123 * regions come from here. Also used for emitting random vertices,
124 * these may be flushed by calling flush_current();
126 struct r300_dma_region current
;
128 void (*flush
) (r300ContextPtr
);
130 char *buf0_address
; /* start of buf[0], for index calcs */
132 /* Number of "in-flight" DMA buffers, i.e. the number of buffers
133 * for which a DISCARD command is currently queued in the command buffer.
135 GLuint nr_released_bufs
;
138 /* Texture related */
140 typedef struct r300_tex_obj r300TexObj
, *r300TexObjPtr
;
142 /* Texture object in locally shared texture space.
144 struct r300_tex_obj
{
145 driTextureObject base
;
147 GLuint bufAddr
; /* Offset to start of locally
148 shared texture block */
150 GLuint dirty_state
; /* Flags (1 per texunit) for
151 whether or not this texobj
152 has dirty hardware state
153 (pp_*) that needs to be
157 drm_radeon_tex_image_t image
[6][RADEON_MAX_TEXTURE_LEVELS
];
158 /* Six, for the cube faces */
161 /* hardware register values */
162 /* Note that R200 has 8 registers per texture and R300 only 7 */
164 GLuint pitch
; /* one of the unknown registers.. unknown 1 ?*/
165 GLuint size
; /* npot only */
167 GLuint offset
; /* Image location in texmem.
168 All cube faces follow. */
171 /* end hardware registers */
173 /* registers computed by r200 code - keep them here to
174 compare against what is actually written.
176 to be removed later.. */
177 GLuint pp_border_color
;
178 GLuint pp_cubic_faces
; /* cube face 1,2,3,4 log2 sizes */
182 GLboolean border_fallback
;
185 struct r300_texture_env_state
{
186 r300TexObjPtr texobj
;
191 #define R300_MAX_TEXTURE_UNITS 8
193 struct r300_texture_state
{
194 struct r300_texture_env_state unit
[R300_MAX_TEXTURE_UNITS
];
195 int tc_count
; /* number of incoming texture coordinates from VAP */
199 * A block of hardware state.
201 * When check returns non-zero, the returned number of dwords must be
202 * copied verbatim into the command buffer in order to update a state atom
205 struct r300_state_atom
{
206 struct r300_state_atom
*next
, *prev
;
207 const char* name
; /* for debug */
208 int cmd_size
; /* maximum size in dwords */
209 GLuint idx
; /* index in an array (e.g. textures) */
213 int (*check
)(r300ContextPtr
, struct r300_state_atom
* atom
);
217 #define R300_VPT_CMD_0 0
218 #define R300_VPT_XSCALE 1
219 #define R300_VPT_XOFFSET 2
220 #define R300_VPT_YSCALE 3
221 #define R300_VPT_YOFFSET 4
222 #define R300_VPT_ZSCALE 5
223 #define R300_VPT_ZOFFSET 6
224 #define R300_VPT_CMDSIZE 7
226 #define R300_VIR_CMD_0 0 /* vir is variable size (at least 1) */
227 #define R300_VIR_CNTL_0 1
228 #define R300_VIR_CNTL_1 2
229 #define R300_VIR_CNTL_2 3
230 #define R300_VIR_CNTL_3 4
231 #define R300_VIR_CNTL_4 5
232 #define R300_VIR_CNTL_5 6
233 #define R300_VIR_CNTL_6 7
234 #define R300_VIR_CNTL_7 8
235 #define R300_VIR_CMDSIZE 9
237 #define R300_VIC_CMD_0 0
238 #define R300_VIC_CNTL_0 1
239 #define R300_VIC_CNTL_1 2
240 #define R300_VIC_CMDSIZE 3
242 #define R300_VOF_CMD_0 0
243 #define R300_VOF_CNTL_0 1
244 #define R300_VOF_CNTL_1 2
245 #define R300_VOF_CMDSIZE 3
248 #define R300_PVS_CMD_0 0
249 #define R300_PVS_CNTL_1 1
250 #define R300_PVS_CNTL_2 2
251 #define R300_PVS_CNTL_3 3
252 #define R300_PVS_CMDSIZE 4
254 #define R300_GB_MISC_CMD_0 0
255 #define R300_GB_MISC_MSPOS_0 1
256 #define R300_GB_MISC_MSPOS_1 2
257 #define R300_GB_MISC_TILE_CONFIG 3
258 #define R300_GB_MISC_SELECT 4
259 #define R300_GB_MISC_AA_CONFIG 5
260 #define R300_GB_MISC_CMDSIZE 6
262 #define R300_TXE_CMD_0 0
263 #define R300_TXE_ENABLE 1
264 #define R300_TXE_CMDSIZE 2
266 #define R300_PS_CMD_0 0
267 #define R300_PS_POINTSIZE 1
268 #define R300_PS_CMDSIZE 2
270 #define R300_ZBS_CMD_0 0
271 #define R300_ZBS_T_FACTOR 1
272 #define R300_ZBS_T_CONSTANT 2
273 #define R300_ZBS_W_FACTOR 3
274 #define R300_ZBS_W_CONSTANT 4
275 #define R300_ZBS_CMDSIZE 5
277 #define R300_CUL_CMD_0 0
278 #define R300_CUL_CULL 1
279 #define R300_CUL_CMDSIZE 2
281 #define R300_RC_CMD_0 0
282 #define R300_RC_CNTL_0 1
283 #define R300_RC_CNTL_1 2
284 #define R300_RC_CMDSIZE 3
286 #define R300_RI_CMD_0 0
287 #define R300_RI_INTERP_0 1
288 #define R300_RI_INTERP_1 2
289 #define R300_RI_INTERP_2 3
290 #define R300_RI_INTERP_3 4
291 #define R300_RI_INTERP_4 5
292 #define R300_RI_INTERP_5 6
293 #define R300_RI_INTERP_6 7
294 #define R300_RI_INTERP_7 8
295 #define R300_RI_CMDSIZE 9
297 #define R300_RR_CMD_0 0 /* rr is variable size (at least 1) */
298 #define R300_RR_ROUTE_0 1
299 #define R300_RR_ROUTE_1 2
300 #define R300_RR_ROUTE_2 3
301 #define R300_RR_ROUTE_3 4
302 #define R300_RR_ROUTE_4 5
303 #define R300_RR_ROUTE_5 6
304 #define R300_RR_ROUTE_6 7
305 #define R300_RR_ROUTE_7 8
306 #define R300_RR_CMDSIZE 9
308 #define R300_FP_CMD_0 0
309 #define R300_FP_CNTL0 1
310 #define R300_FP_CNTL1 2
311 #define R300_FP_CNTL2 3
312 #define R300_FP_CMD_1 4
313 #define R300_FP_NODE0 5
314 #define R300_FP_NODE1 6
315 #define R300_FP_NODE2 7
316 #define R300_FP_NODE3 8
317 #define R300_FP_CMDSIZE 9
319 #define R300_FPT_CMD_0 0
320 #define R300_FPT_INSTR_0 1
321 #define R300_FPT_CMDSIZE 65
323 #define R300_FPI_CMD_0 0
324 #define R300_FPI_INSTR_0 1
325 #define R300_FPI_CMDSIZE 65
327 #define R300_FPP_CMD_0 0
328 #define R300_FPP_PARAM_0 1
329 #define R300_FPP_CMDSIZE (32*4+1)
331 #define R300_AT_CMD_0 0
332 #define R300_AT_ALPHA_TEST 1
333 #define R300_AT_UNKNOWN 2
334 #define R300_AT_CMDSIZE 3
336 #define R300_BLD_CMD_0 0
337 #define R300_BLD_CBLEND 1
338 #define R300_BLD_ABLEND 2
339 #define R300_BLD_CMDSIZE 3
341 #define R300_CMK_CMD_0 0
342 #define R300_CMK_COLORMASK 1
343 #define R300_CMK_CMDSIZE 2
345 #define R300_CB_CMD_0 0
346 #define R300_CB_OFFSET 1
347 #define R300_CB_CMD_1 2
348 #define R300_CB_PITCH 3
349 #define R300_CB_CMDSIZE 4
351 #define R300_ZS_CMD_0 0
352 #define R300_ZS_CNTL_0 1
353 #define R300_ZS_CNTL_1 2
354 #define R300_ZS_CNTL_2 3
355 #define R300_ZS_CMDSIZE 4
357 #define R300_ZB_CMD_0 0
358 #define R300_ZB_OFFSET 1
359 #define R300_ZB_PITCH 2
360 #define R300_ZB_CMDSIZE 3
362 #define R300_VPI_CMD_0 0
363 #define R300_VPI_INSTR_0 1
364 #define R300_VPI_CMDSIZE 1025 /* 256 16 byte instructions */
366 #define R300_VPP_CMD_0 0
367 #define R300_VPP_PARAM_0 1
368 #define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */
370 #define R300_VPS_CMD_0 0
371 #define R300_VPS_ZERO_0 1
372 #define R300_VPS_ZERO_1 2
373 #define R300_VPS_POINTSIZE 3
374 #define R300_VPS_ZERO_3 4
375 #define R300_VPS_CMDSIZE 5
377 /* the layout is common for all fields inside tex */
378 #define R300_TEX_CMD_0 0
379 #define R300_TEX_VALUE_0 1
380 /* We don't really use this, instead specify mtu+1 dynamically
381 #define R300_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1)
385 * Cache for hardware register state.
387 struct r300_hw_state
{
388 struct r300_state_atom atomlist
;
392 int max_state_size
; /* in dwords */
394 struct r300_state_atom vpt
; /* viewport (1D98) */
395 struct r300_state_atom unk2080
; /* (2080) */
396 struct r300_state_atom vof
; /* VAP output format register 0x2090 */
397 struct r300_state_atom vte
; /* (20B0) */
398 struct r300_state_atom unk2134
; /* (2134) */
399 struct r300_state_atom unk2140
; /* (2140) */
400 struct r300_state_atom vir
[2]; /* vap input route (2150/21E0) */
401 struct r300_state_atom vic
; /* vap input control (2180) */
402 struct r300_state_atom unk21DC
; /* (21DC) */
403 struct r300_state_atom unk221C
; /* (221C) */
404 struct r300_state_atom unk2220
; /* (2220) */
405 struct r300_state_atom unk2288
; /* (2288) */
406 struct r300_state_atom pvs
; /* pvs_cntl (22D0) */
407 struct r300_state_atom gb_enable
; /* (4008) */
408 struct r300_state_atom gb_misc
; /* Multisampling position shifts ? (4010) */
409 struct r300_state_atom unk4200
; /* (4200) */
410 struct r300_state_atom unk4214
; /* (4214) */
411 struct r300_state_atom ps
; /* pointsize (421C) */
412 struct r300_state_atom unk4230
; /* (4230) */
413 struct r300_state_atom lcntl
; /* line control */
415 struct r300_state_atom lsf
; /* line stipple factor */
417 struct r300_state_atom unk4260
; /* (4260) */
418 struct r300_state_atom unk4274
; /* (4274) */
419 struct r300_state_atom unk4288
; /* (4288) */
420 struct r300_state_atom unk42A0
; /* (42A0) */
421 struct r300_state_atom zbs
; /* zbias (42A4) */
422 struct r300_state_atom unk42B4
; /* (42B4) */
423 struct r300_state_atom cul
; /* cull cntl (42B8) */
424 struct r300_state_atom unk42C0
; /* (42C0) */
425 struct r300_state_atom rc
; /* rs control (4300) */
426 struct r300_state_atom ri
; /* rs interpolators (4310) */
427 struct r300_state_atom rr
; /* rs route (4330) */
428 struct r300_state_atom unk43A4
; /* (43A4) */
429 struct r300_state_atom unk43E8
; /* (43E8) */
430 struct r300_state_atom fp
; /* fragment program cntl + nodes (4600) */
431 struct r300_state_atom fpt
; /* texi - (4620) */
432 struct r300_state_atom unk46A4
; /* (46A4) */
433 struct r300_state_atom fpi
[4]; /* fp instructions (46C0/47C0/48C0/49C0) */
434 struct r300_state_atom unk4BC0
; /* (4BC0) */
435 struct r300_state_atom unk4BC8
; /* (4BC8) */
436 struct r300_state_atom at
; /* alpha test (4BD4) */
437 struct r300_state_atom unk4BD8
; /* (4BD8) */
438 struct r300_state_atom fpp
; /* 0x4C00 and following */
439 struct r300_state_atom unk4E00
; /* (4E00) */
440 struct r300_state_atom bld
; /* blending (4E04) */
441 struct r300_state_atom cmk
; /* colormask (4E0C) */
442 struct r300_state_atom unk4E10
; /* (4E10) */
443 struct r300_state_atom cb
; /* colorbuffer (4E28) */
444 struct r300_state_atom unk4E50
; /* (4E50) */
445 struct r300_state_atom unk4E88
; /* (4E88) */
446 struct r300_state_atom unk4EA0
; /* (4E88) I saw it only written on RV350 hardware.. */
447 struct r300_state_atom zs
; /* zstencil control (4F00) */
448 struct r300_state_atom unk4F10
; /* (4F10) */
449 struct r300_state_atom zb
; /* z buffer (4F20) */
450 struct r300_state_atom unk4F28
; /* (4F28) */
451 struct r300_state_atom unk4F30
; /* (4F30) */
452 struct r300_state_atom unk4F44
; /* (4F44) */
453 struct r300_state_atom unk4F54
; /* (4F54) */
455 struct r300_state_atom vpi
; /* vp instructions */
456 struct r300_state_atom vpp
; /* vp parameters */
457 struct r300_state_atom vps
; /* vertex point size (?) */
458 /* 8 texture units */
459 /* the state is grouped by function and not by
460 texture unit. This makes single unit updates
461 really awkward - we are much better off
462 updating the whole thing at once */
464 struct r300_state_atom filter
;
465 struct r300_state_atom unknown1
;
466 struct r300_state_atom size
;
467 struct r300_state_atom format
;
468 struct r300_state_atom offset
;
469 struct r300_state_atom unknown4
;
470 struct r300_state_atom border_color
;
472 struct r300_state_atom txe
; /* tex enable (4104) */
477 * This structure holds the command buffer while it is being constructed.
479 * The first batch of commands in the buffer is always the state that needs
480 * to be re-emitted when the context is lost. This batch can be skipped
484 int size
; /* DWORDs allocated for buffer */
486 int count_used
; /* DWORDs filled so far */
487 int count_reemit
; /* size of re-emission batch */
495 struct r300_depthbuffer_state
{
499 struct r300_vap_reg_state
{
500 /* input register assigments */
505 int i_tex
[R300_MAX_TEXTURE_UNITS
];
510 /* Vertex shader state */
512 /* 64 appears to be the maximum */
513 #define VSF_MAX_FRAGMENT_LENGTH 64
516 struct r300_vertex_shader_fragment
{
519 GLuint d
[VSF_MAX_FRAGMENT_LENGTH
];
520 float f
[VSF_MAX_FRAGMENT_LENGTH
];
521 VERTEX_SHADER_INSTRUCTION i
[VSF_MAX_FRAGMENT_LENGTH
/4];
525 #define VSF_DEST_PROGRAM 0x0
526 #define VSF_DEST_MATRIX0 0x200
527 #define VSF_DEST_MATRIX1 0x204
528 #define VSF_DEST_MATRIX2 0x208
529 #define VSF_DEST_VECTOR0 0x20c
530 #define VSF_DEST_VECTOR1 0x20d
531 #define VSF_DEST_UNKNOWN1 0x400
532 #define VSF_DEST_UNKNOWN2 0x406
534 struct r300_vertex_shader_state
{
535 struct r300_vertex_shader_fragment program
;
537 /* a bit of a waste - each uses only a subset of allocated space..
538 but easier to program */
539 struct r300_vertex_shader_fragment matrix
[3];
540 struct r300_vertex_shader_fragment vector
[2];
542 struct r300_vertex_shader_fragment unknown1
;
543 struct r300_vertex_shader_fragment unknown2
;
546 int unknown_ptr1
; /* pointer within program space */
552 int unknown_ptr2
; /* pointer within program space */
553 int unknown_ptr3
; /* pointer within program space */
556 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
557 * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
559 struct r300_vertex_program
{
560 struct vertex_program mesa_program
; /* Must be first */
563 struct r300_vertex_shader_fragment program
;
564 struct r300_vertex_shader_fragment params
;
567 unsigned long num_temporaries
; /* Number of temp vars used by program */
568 int inputs
[VERT_ATTRIB_MAX
];
571 /* 64 appears to be the maximum */
572 #define PSF_MAX_PROGRAM_LENGTH 64
574 struct r300_pixel_shader_program
{
577 GLuint inst
[PSF_MAX_PROGRAM_LENGTH
];
580 /* ALU intructions (logic and integer) */
588 } inst
[PSF_MAX_PROGRAM_LENGTH
];
591 /* node information */
592 /* nodes are used to synchronize ALU and TEX streams */
593 /* There could be up to 4 nodes each consisting of
594 a number of TEX instructions followed by some ALU
596 /* the last node of a program should always be node3 */
604 int active_nodes
; /* must be between 1 and 4, inclusive */
605 int first_node_has_tex
; /* other nodes always have it */
607 int temp_register_count
; /* magic value goes into PFS_CNTL_1 */
617 #define MAX_PIXEL_SHADER_PARAMS 32
618 struct r300_pixel_shader_state
{
619 struct r300_pixel_shader_program program
;
622 int param_length
; /* to limit the number of unnecessary writes */
628 } param
[MAX_PIXEL_SHADER_PARAMS
];
631 /* 8 is somewhat bogus... it is probably something like 24 */
632 #define R300_MAX_AOS_ARRAYS 8
634 #define AOS_FORMAT_FLOAT 1
635 #define AOS_FORMAT_UBYTE 2
636 #define AOS_FORMAT_FLOAT_COLOR 3
642 struct r300_aos_rec
{
644 int element_size
; /* in dwords */
645 int stride
; /* distance between elements, in dwords */
649 int ncomponents
; /* number of components - between 1 and 4, inclusive */
651 int reg
; /* which register they are assigned to. */
656 struct r300_depthbuffer_state depth
;
657 struct r300_texture_state texture
;
658 struct r300_vap_reg_state vap_reg
;
659 struct r300_vertex_shader_state vertex_shader
;
660 struct r300_pixel_shader_state pixel_shader
;
662 struct r300_dma_region aos
[R300_MAX_AOS_ARRAYS
];
666 struct r300_dma_region elt_ao
;
668 GLuint render_inputs
; /* actual render inputs that R300 was configured for.
669 They are the same as tnl->render_inputs for fixed pipeline */
676 * R300 context structure.
678 struct r300_context
{
679 struct radeon_context radeon
; /* parent class, must be first */
681 struct r300_hw_state hw
;
682 struct r300_cmdbuf cmdbuf
;
683 struct r300_state state
;
688 GLboolean save_on_next_unlock
;
690 /* Texture object bookkeeping
693 driTexHeap
*texture_heaps
[R200_NR_TEX_HEAPS
];
694 driTextureObject swapped
;
696 float initialMaxAnisotropy
;
698 /* Clientdata textures;
700 GLuint prefer_gart_client_texturing
;
704 GLmatrix TexGenMatrix
[R300_MAX_TEXTURE_UNITS
];
705 GLboolean recheck_texgen
[R300_MAX_TEXTURE_UNITS
];
706 GLboolean TexGenNeedNormals
[R300_MAX_TEXTURE_UNITS
];
707 GLuint TexMatEnabled
;
708 GLuint TexMatCompSel
;
709 GLuint TexGenEnabled
;
711 GLuint TexGenCompSel
;
714 struct r300_vertex_program
*current_vp
;
717 #define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx))
719 extern void r300DestroyContext(__DRIcontextPrivate
* driContextPriv
);
720 extern GLboolean
r300CreateContext(const __GLcontextModes
* glVisual
,
721 __DRIcontextPrivate
* driContextPriv
,
722 void *sharedContextPrivate
);
724 extern void r300InitVertexProgFuncs(struct dd_function_table
*functions
);
725 extern void r300VertexProgUpdateParams(GLcontext
*ctx
, struct r300_vertex_program
*vp
);
727 #endif /* __R300_CONTEXT_H__ */